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From: Fei Gao <gaofei@eswincomputing.com>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com,
	sinan.lin@linux.alibaba.com, jiawei@iscas.ac.cn,
	Fei Gao <gaofei@eswincomputing.com>
Subject: [PATCH 2/2] [RISC-V] Enalble zcmp for -Os
Date: Thu, 31 Aug 2023 06:24:02 +0000	[thread overview]
Message-ID: <20230831062402.6810-3-gaofei@eswincomputing.com> (raw)
In-Reply-To: <20230831062402.6810-1-gaofei@eswincomputing.com>

Enalble zcmp for -Os and shrink-warp-separate for
the speed perfered optimization by default.

To force enabling zcmp multi push/pop in speed perfered case,
fno-shrink-wrap-separate has to be explictly given.

gcc/ChangeLog:

        * config/riscv/riscv.cc 
	(riscv_avoid_shrink_wrapping_separate): wrap the condition check in
        riscv_avoid_shrink_wrapping_separate.
        (riscv_avoid_multi_push):avoid multi push if shrink_wrapping_separate
          is active.
        (riscv_get_separate_components):call riscv_avoid_shrink_wrapping_separate

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rv32e_zcmp.c: remove -fno-shrink-wrap-separate
        * gcc.target/riscv/rv32i_zcmp.c: likewise
        * gcc.target/riscv/zcmp_push_fpr.c: likewise
        * gcc.target/riscv/zcmp_stack_alignment.c: likewise
        * gcc.target/riscv/zcmp_shrink_wrap_separate.c: New test.
        * gcc.target/riscv/zcmp_shrink_wrap_separate2.c: New test.
---
 gcc/config/riscv/riscv.cc                     | 21 ++++-
 gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c   |  2 +-
 gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c   |  2 +-
 .../gcc.target/riscv/zcmp_push_fpr.c          |  2 +-
 .../riscv/zcmp_shrink_wrap_separate.c         | 93 +++++++++++++++++++
 .../riscv/zcmp_shrink_wrap_separate2.c        | 93 +++++++++++++++++++
 .../gcc.target/riscv/zcmp_stack_alignment.c   |  2 +-
 7 files changed, 207 insertions(+), 8 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate2.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 78600ba73b6..3f71000c88b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -64,6 +64,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "cfghooks.h"
 #include "cfgloop.h"
 #include "cfgrtl.h"
+#include "shrink-wrap.h"
 #include "sel-sched.h"
 #include "sched-int.h"
 #include "fold-const.h"
@@ -372,6 +373,7 @@ static const struct riscv_tune_param optimize_size_tune_info = {
   false,					/* use_divmod_expansion */
 };
 
+static bool riscv_avoid_shrink_wrapping_separate ();
 static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
 static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
 
@@ -5569,7 +5571,9 @@ riscv_avoid_multi_push (const struct riscv_frame_info *frame)
 {
   if (!TARGET_ZCMP || crtl->calls_eh_return || frame_pointer_needed
       || cfun->machine->interrupt_handler_p || cfun->machine->varargs_size != 0
-      || crtl->args.pretend_args_size != 0 || flag_shrink_wrap_separate
+      || crtl->args.pretend_args_size != 0
+      || (use_shrink_wrapping_separate ()
+	  && !riscv_avoid_shrink_wrapping_separate ())
       || (frame->mask & ~MULTI_PUSH_GPR_MASK))
     return true;
 
@@ -6831,6 +6835,17 @@ riscv_epilogue_uses (unsigned int regno)
   return false;
 }
 
+static bool
+riscv_avoid_shrink_wrapping_separate ()
+{
+  if (riscv_use_save_libcall (&cfun->machine->frame)
+      || cfun->machine->interrupt_handler_p
+      || !cfun->machine->frame.gp_sp_offset.is_constant ())
+    return true;
+
+  return false;
+}
+
 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS.  */
 
 static sbitmap
@@ -6840,9 +6855,7 @@ riscv_get_separate_components (void)
   sbitmap components = sbitmap_alloc (FIRST_PSEUDO_REGISTER);
   bitmap_clear (components);
 
-  if (riscv_use_save_libcall (&cfun->machine->frame)
-      || cfun->machine->interrupt_handler_p
-      || !cfun->machine->frame.gp_sp_offset.is_constant ())
+  if (riscv_avoid_shrink_wrapping_separate ())
     return components;
 
   offset = cfun->machine->frame.gp_sp_offset.to_constant ();
diff --git a/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c b/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c
index 394459c4ed7..50e443573ad 100644
--- a/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c
+++ b/gcc/testsuite/gcc.target/riscv/rv32e_zcmp.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options " -Os -march=rv32e_zca_zcmp -mabi=ilp32e -mcmodel=medlow -fno-shrink-wrap-separate" } */
+/* { dg-options " -Os -march=rv32e_zca_zcmp -mabi=ilp32e -mcmodel=medlow" } */
 /* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-O2" "-Og" "-O3" "-Oz" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c
index f00338a9d17..ea562b7a233 100644
--- a/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c
+++ b/gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options " -Os -march=rv32imaf_zca_zcmp -mabi=ilp32f -mcmodel=medlow -fno-shrink-wrap-separate" }*/
+/* { dg-options " -Os -march=rv32imaf_zca_zcmp -mabi=ilp32f -mcmodel=medlow" }*/
 /* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-O2" "-Og" "-O3" "-Oz" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
diff --git a/gcc/testsuite/gcc.target/riscv/zcmp_push_fpr.c b/gcc/testsuite/gcc.target/riscv/zcmp_push_fpr.c
index 530b35b53dd..c9d79205b31 100644
--- a/gcc/testsuite/gcc.target/riscv/zcmp_push_fpr.c
+++ b/gcc/testsuite/gcc.target/riscv/zcmp_push_fpr.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64imafd_zicsr_zifencei_zca_zcmp -mabi=lp64d -Os -fno-shrink-wrap-separate" } */
+/* { dg-options "-march=rv64imafd_zicsr_zifencei_zca_zcmp -mabi=lp64d -Os" } */
 /* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-O2" "-Og" "-O3" "-Oz" "-flto"} } */
 
 typedef struct
diff --git a/gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate.c b/gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate.c
new file mode 100644
index 00000000000..035bc32cec5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate.c
@@ -0,0 +1,93 @@
+/* { dg-do compile } */
+/* { dg-options " -O2 -march=rv32imaf_zca_zcmp -mabi=ilp32f" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Os" "-Og" "-O3" "-Oz" "-flto"} } */
+
+typedef struct MAT_PARAMS_S
+{
+  int N;
+  signed short *A;
+  signed short *B;
+  signed int *C;
+} mat_params;
+
+typedef struct CORE_PORTABLE_S
+{
+  unsigned char portable_id;
+} core_portable;
+
+typedef struct RESULTS_S
+{
+  /* inputs */
+  signed short seed1;	   /* Initializing seed */
+  signed short seed2;	   /* Initializing seed */
+  signed short seed3;	   /* Initializing seed */
+  void *memblock[4];	   /* Pointer to safe memory location */
+  unsigned int size;	   /* Size of the data */
+  unsigned int iterations; /* Number of iterations to execute */
+  unsigned int execs;	   /* Bitmask of operations to execute */
+  struct list_head_s *list;
+  mat_params mat;
+  /* outputs */
+  unsigned short crc;
+  unsigned short crclist;
+  unsigned short crcmatrix;
+  unsigned short crcstate;
+  signed short err;
+  /* ultithread specific */
+  core_portable port;
+} core_results;
+
+extern signed short
+core_bench_state (unsigned int, void *, signed short, signed short,
+		  signed short, unsigned short);
+
+extern signed short
+core_bench_matrix (mat_params *, signed short, unsigned short);
+
+extern unsigned short
+crcu16 (signed short, unsigned short);
+
+signed short
+calc_func (signed short *pdata, core_results *res)
+{
+  signed short data = *pdata;
+  signed short retval;
+  unsigned char optype
+    = (data >> 7)
+      & 1;    /* bit 7 indicates if the function result has been cached */
+  if (optype) /* if cached, use cache */
+    return (data & 0x007f);
+  else
+    { /* otherwise calculate and cache the result */
+      signed short flag
+	= data & 0x7; /* bits 0-2 is type of function to perform */
+      signed short dtype
+	= ((data >> 3) & 0xf); /* bits 3-6 is specific data for the operation */
+      dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */
+      switch (flag)
+	{
+	case 0:
+	  if (dtype < 0x22) /* set min period for bit corruption */
+	    dtype = 0x22;
+	  retval = core_bench_state (res->size, res->memblock[3], res->seed1,
+				     res->seed2, dtype, res->crc);
+	  if (res->crcstate == 0)
+	    res->crcstate = retval;
+	  break;
+	case 1:
+	  retval = core_bench_matrix (&(res->mat), dtype, res->crc);
+	  if (res->crcmatrix == 0)
+	    res->crcmatrix = retval;
+	  break;
+	default:
+	  retval = data;
+	  break;
+	}
+      res->crc = crcu16 (retval, res->crc);
+      retval &= 0x007f;
+      *pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */
+      return retval;
+    }
+}
+
+/* { dg-final { scan-assembler-not "cm\.push" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate2.c b/gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate2.c
new file mode 100644
index 00000000000..47c78886052
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zcmp_shrink_wrap_separate2.c
@@ -0,0 +1,93 @@
+/* { dg-do compile } */
+/* { dg-options " -O2 -fno-shrink-wrap-separate -march=rv32imaf_zca_zcmp -mabi=ilp32f" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Os" "-Og" "-O3" "-Oz" "-flto"} } */
+
+typedef struct MAT_PARAMS_S
+{
+  int N;
+  signed short *A;
+  signed short *B;
+  signed int *C;
+} mat_params;
+
+typedef struct CORE_PORTABLE_S
+{
+  unsigned char portable_id;
+} core_portable;
+
+typedef struct RESULTS_S
+{
+  /* inputs */
+  signed short seed1;	   /* Initializing seed */
+  signed short seed2;	   /* Initializing seed */
+  signed short seed3;	   /* Initializing seed */
+  void *memblock[4];	   /* Pointer to safe memory location */
+  unsigned int size;	   /* Size of the data */
+  unsigned int iterations; /* Number of iterations to execute */
+  unsigned int execs;	   /* Bitmask of operations to execute */
+  struct list_head_s *list;
+  mat_params mat;
+  /* outputs */
+  unsigned short crc;
+  unsigned short crclist;
+  unsigned short crcmatrix;
+  unsigned short crcstate;
+  signed short err;
+  /* ultithread specific */
+  core_portable port;
+} core_results;
+
+extern signed short
+core_bench_state (unsigned int, void *, signed short, signed short,
+		  signed short, unsigned short);
+
+extern signed short
+core_bench_matrix (mat_params *, signed short, unsigned short);
+
+extern unsigned short
+crcu16 (signed short, unsigned short);
+
+signed short
+calc_func (signed short *pdata, core_results *res)
+{
+  signed short data = *pdata;
+  signed short retval;
+  unsigned char optype
+    = (data >> 7)
+      & 1;    /* bit 7 indicates if the function result has been cached */
+  if (optype) /* if cached, use cache */
+    return (data & 0x007f);
+  else
+    { /* otherwise calculate and cache the result */
+      signed short flag
+	= data & 0x7; /* bits 0-2 is type of function to perform */
+      signed short dtype
+	= ((data >> 3) & 0xf); /* bits 3-6 is specific data for the operation */
+      dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */
+      switch (flag)
+	{
+	case 0:
+	  if (dtype < 0x22) /* set min period for bit corruption */
+	    dtype = 0x22;
+	  retval = core_bench_state (res->size, res->memblock[3], res->seed1,
+				     res->seed2, dtype, res->crc);
+	  if (res->crcstate == 0)
+	    res->crcstate = retval;
+	  break;
+	case 1:
+	  retval = core_bench_matrix (&(res->mat), dtype, res->crc);
+	  if (res->crcmatrix == 0)
+	    res->crcmatrix = retval;
+	  break;
+	default:
+	  retval = data;
+	  break;
+	}
+      res->crc = crcu16 (retval, res->crc);
+      retval &= 0x007f;
+      *pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */
+      return retval;
+    }
+}
+
+/* { dg-final { scan-assembler "cm\.push" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c b/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c
index 2f2fa55baac..f7d8f446b79 100644
--- a/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c
+++ b/gcc/testsuite/gcc.target/riscv/zcmp_stack_alignment.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options " -O0 -march=rv32e_zca_zcb_zcmp -mabi=ilp32e -mcmodel=medlow -fomit-frame-pointer -fno-shrink-wrap-separate" } */
+/* { dg-options " -O0 -march=rv32e_zca_zcb_zcmp -mabi=ilp32e -mcmodel=medlow -fomit-frame-pointer" } */
 /* { dg-skip-if "" { *-*-* } {"-O2" "-O1" "-Os" "-Og" "-O3" "-Oz" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-- 
2.17.1


  parent reply	other threads:[~2023-08-31  6:24 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-31  6:24 [PATCH 0/2] resolve confilct between zcmp multi push/pop and shrink-wrap-separate Fei Gao
2023-08-31  6:24 ` [PATCH 1/2] allow targets to check shrink-wrap-separate enabled or not Fei Gao
2023-08-31  6:24 ` Fei Gao [this message]
2023-09-05 12:02   ` [PATCH 2/2] [RISC-V] Enalble zcmp for -Os Kito Cheng
2023-09-06  1:47     ` Fei Gao
2023-09-06  8:06       ` Kito Cheng
2023-09-12  0:56         ` Fei Gao

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