* [PATCH 1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api
2023-09-01 5:45 [PATCH 0/4] Add conditional autovec convert patterns Lehua Ding
@ 2023-09-01 5:45 ` Lehua Ding
2023-09-01 10:00 ` Robin Dapp
2023-09-01 5:45 ` [PATCH 2/4] RISC-V: Add conditional autovec convert(INT<->INT) patterns Lehua Ding
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Lehua Ding @ 2023-09-01 5:45 UTC (permalink / raw)
To: gcc-patches, rdapp.gcc; +Cc: juzhe.zhong, kito.cheng, palmer, jeffreyalaw
This patch change expand_cond_len_{unary,binop}'s argument `rtx_code code`
to `unsigned icode` and use the icode directly to determine whether the
rounding_mode operand is required.
gcc/ChangeLog:
* config/riscv/autovec.md: Adjust.
* config/riscv/riscv-protos.h (expand_cond_len_unop): Ditto.
(expand_cond_len_binop): Ditto.
* config/riscv/riscv-v.cc (needs_fp_rounding): Ditto.
(expand_cond_len_op): Ditto.
(expand_cond_len_unop): Ditto.
(expand_cond_len_binop): Ditto.
(expand_cond_len_ternop): Ditto.
---
gcc/config/riscv/autovec.md | 18 +++++++++++------
gcc/config/riscv/riscv-protos.h | 4 ++--
gcc/config/riscv/riscv-v.cc | 34 +++++++++++++++++++--------------
3 files changed, 34 insertions(+), 22 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index ebe1b10aa12..006e174ebd5 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1551,7 +1551,8 @@
(match_operand 5 "const_0_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_cond_len_unop (<CODE>, operands);
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_len_unop (icode, operands);
DONE;
})
@@ -1588,7 +1589,8 @@
(match_operand 5 "const_0_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_cond_len_unop (<CODE>, operands);
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_len_unop (icode, operands);
DONE;
})
@@ -1627,7 +1629,8 @@
(match_operand 6 "const_0_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_cond_len_binop (<CODE>, operands);
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_len_binop (icode, operands);
DONE;
})
@@ -1667,7 +1670,8 @@
(match_operand 6 "const_0_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_cond_len_binop (<CODE>, operands);
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_len_binop (icode, operands);
DONE;
})
@@ -1707,7 +1711,8 @@
(match_operand 6 "const_0_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_cond_len_binop (<CODE>, operands);
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_len_binop (icode, operands);
DONE;
})
@@ -1745,7 +1750,8 @@
(match_operand 6 "const_0_operand")]
"TARGET_VECTOR"
{
- riscv_vector::expand_cond_len_binop (<CODE>, operands);
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ riscv_vector::expand_cond_len_binop (icode, operands);
DONE;
})
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index e145ee6c69b..dd7aa360ec5 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -426,8 +426,8 @@ bool neg_simm5_p (rtx);
bool has_vi_variant_p (rtx_code, rtx);
void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
-void expand_cond_len_unop (rtx_code, rtx *);
-void expand_cond_len_binop (rtx_code, rtx *);
+void expand_cond_len_unop (unsigned, rtx *);
+void expand_cond_len_binop (unsigned, rtx *);
void expand_reduction (rtx_code, rtx *, rtx,
reduction_type = reduction_type::UNORDERED);
#endif
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 6228ff3d92e..89ac4743f40 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -245,6 +245,12 @@ public:
always Pmode. */
if (mode == VOIDmode)
mode = Pmode;
+ else
+ /* Early assertion ensures same mode since maybe_legitimize_operand
+ will check this. */
+ gcc_assert (GET_MODE (ops[opno]) == VOIDmode
+ || GET_MODE (ops[opno]) == mode);
+
add_input_operand (ops[opno], mode);
}
@@ -291,6 +297,7 @@ public:
if (m_insn_flags & FRM_DYN_P)
add_rounding_mode_operand (FRM_DYN);
+ gcc_assert (insn_data[(int) icode].n_operands == m_opno);
expand (icode, any_mem_p);
}
@@ -2951,17 +2958,20 @@ expand_load_store (rtx *ops, bool is_load)
/* Return true if the operation is the floating-point operation need FRM. */
static bool
-needs_fp_rounding (rtx_code code, machine_mode mode)
+needs_fp_rounding (unsigned icode, machine_mode mode)
{
if (!FLOAT_MODE_P (mode))
return false;
- return code != SMIN && code != SMAX && code != NEG && code != ABS;
+
+ return icode != maybe_code_for_pred (SMIN, mode)
+ && icode != maybe_code_for_pred (SMAX, mode)
+ && icode != maybe_code_for_pred (NEG, mode)
+ && icode != maybe_code_for_pred (ABS, mode);
}
/* Subroutine to expand COND_LEN_* patterns. */
static void
-expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops,
- rtx len)
+expand_cond_len_op (unsigned icode, insn_flags op_type, rtx *ops, rtx len)
{
rtx dest = ops[0];
rtx mask = ops[1];
@@ -2980,7 +2990,7 @@ expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops,
else
insn_flags |= TU_POLICY_P | MU_POLICY_P;
- if (needs_fp_rounding (code, mode))
+ if (needs_fp_rounding (icode, mode))
insn_flags |= FRM_DYN_P;
if (is_vlmax_len)
@@ -2991,7 +3001,7 @@ expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx *ops,
/* Expand unary ops COND_LEN_*. */
void
-expand_cond_len_unop (rtx_code code, rtx *ops)
+expand_cond_len_unop (unsigned icode, rtx *ops)
{
rtx dest = ops[0];
rtx mask = ops[1];
@@ -2999,15 +3009,13 @@ expand_cond_len_unop (rtx_code code, rtx *ops)
rtx merge = ops[3];
rtx len = ops[4];
- machine_mode mode = GET_MODE (dest);
- insn_code icode = code_for_pred (code, mode);
rtx cond_ops[] = {dest, mask, merge, src};
- expand_cond_len_op (code, icode, UNARY_OP_P, cond_ops, len);
+ expand_cond_len_op (icode, UNARY_OP_P, cond_ops, len);
}
/* Expand binary ops COND_LEN_*. */
void
-expand_cond_len_binop (rtx_code code, rtx *ops)
+expand_cond_len_binop (unsigned icode, rtx *ops)
{
rtx dest = ops[0];
rtx mask = ops[1];
@@ -3016,10 +3024,8 @@ expand_cond_len_binop (rtx_code code, rtx *ops)
rtx merge = ops[4];
rtx len = ops[5];
- machine_mode mode = GET_MODE (dest);
- insn_code icode = code_for_pred (code, mode);
rtx cond_ops[] = {dest, mask, merge, src1, src2};
- expand_cond_len_op (code, icode, BINARY_OP_P, cond_ops, len);
+ expand_cond_len_op (icode, BINARY_OP_P, cond_ops, len);
}
/* Prepare insn_code for gather_load/scatter_store according to
@@ -3191,7 +3197,7 @@ expand_cond_len_ternop (unsigned icode, rtx *ops)
rtx len = ops[6];
rtx cond_ops[] = {dest, mask, src1, src2, src3, merge};
- expand_cond_len_op (UNSPEC, icode, TERNARY_OP_P, cond_ops, len);
+ expand_cond_len_op (icode, TERNARY_OP_P, cond_ops, len);
}
/* Expand reduction operations. */
--
2.36.3
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api
2023-09-01 5:45 ` [PATCH 1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api Lehua Ding
@ 2023-09-01 10:00 ` Robin Dapp
2023-09-01 11:34 ` Lehua Ding
0 siblings, 1 reply; 10+ messages in thread
From: Robin Dapp @ 2023-09-01 10:00 UTC (permalink / raw)
To: Lehua Ding, gcc-patches
Cc: rdapp.gcc, juzhe.zhong, kito.cheng, palmer, jeffreyalaw
Thanks, LGTM.
Btw. I haven't forgotten to respond to your last refactor but just didn't find
the time yet. I figured I should have some proper draft before suggesting
more things :)
Regards
Robin
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api
2023-09-01 10:00 ` Robin Dapp
@ 2023-09-01 11:34 ` Lehua Ding
0 siblings, 0 replies; 10+ messages in thread
From: Lehua Ding @ 2023-09-01 11:34 UTC (permalink / raw)
To: Robin Dapp, gcc-patches; +Cc: kito.cheng, juzhe.zhong
On 2023/9/1 18:00, Robin Dapp via Gcc-patches wrote:
> Thanks, LGTM.
Thanks, committed these patches.
> Btw. I haven't forgotten to respond to your last refactor but just didn't find
> the time yet. I figured I should have some proper draft before suggesting
> more things :)
Well, let's talk about it when you're free. Thanks in advance for more
comments and suggestions later.
--
Best,
Lehua
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/4] RISC-V: Add conditional autovec convert(INT<->INT) patterns
2023-09-01 5:45 [PATCH 0/4] Add conditional autovec convert patterns Lehua Ding
2023-09-01 5:45 ` [PATCH 1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api Lehua Ding
@ 2023-09-01 5:45 ` Lehua Ding
2023-09-01 10:05 ` Robin Dapp
2023-09-01 5:45 ` [PATCH 3/4] RISC-V: Add conditional autovec convert(FP<->FP) patterns Lehua Ding
2023-09-01 5:45 ` [PATCH 4/4] RISC-V: Add conditional autovec convert(INT<->FP) patterns Lehua Ding
3 siblings, 1 reply; 10+ messages in thread
From: Lehua Ding @ 2023-09-01 5:45 UTC (permalink / raw)
To: gcc-patches, rdapp.gcc; +Cc: juzhe.zhong, kito.cheng, palmer, jeffreyalaw
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_<optab><v_double_trunc><mode>):
New combine pattern.
(*cond_<optab><v_quad_trunc><mode>): Ditto.
(*cond_<optab><v_oct_trunc><mode>): Ditto.
(*cond_trunc<mode><v_double_trunc>): Ditto.
* config/riscv/autovec.md (<optab><v_quad_trunc><mode>2): Adjust.
(<optab><v_oct_trunc><mode>2): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/narrow-3.c: Adjust.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c: New test.
---
gcc/config/riscv/autovec-opt.md | 77 +++++++++++++++++++
gcc/config/riscv/autovec.md | 37 ++++-----
.../riscv/rvv/autovec/binop/narrow-3.c | 2 +-
.../rvv/autovec/cond/cond_convert_int2int-1.h | 47 +++++++++++
.../rvv/autovec/cond/cond_convert_int2int-2.h | 46 +++++++++++
.../cond/cond_convert_int2int-rv32-1.c | 17 ++++
.../cond/cond_convert_int2int-rv32-2.c | 16 ++++
.../cond/cond_convert_int2int-rv64-1.c | 16 ++++
.../cond/cond_convert_int2int-rv64-2.c | 16 ++++
.../autovec/cond/cond_convert_int2int_run-1.c | 31 ++++++++
.../autovec/cond/cond_convert_int2int_run-2.c | 30 ++++++++
11 files changed, 311 insertions(+), 24 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 92590776c3e..6796239d82d 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -747,3 +747,80 @@
riscv_vector::BINARY_OP, operands);
DONE;
})
+
+;; Combine sign_extend/zero_extend(vf2) and vcond_mask
+(define_insn_and_split "*cond_<optab><v_double_trunc><mode>"
+ [(set (match_operand:VWEXTI 0 "register_operand")
+ (if_then_else:VWEXTI
+ (match_operand:<VM> 1 "register_operand")
+ (any_extend:VWEXTI (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
+ (match_operand:VWEXTI 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_vf2 (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine sign_extend/zero_extend(vf4) and vcond_mask
+(define_insn_and_split "*cond_<optab><v_quad_trunc><mode>"
+ [(set (match_operand:VQEXTI 0 "register_operand")
+ (if_then_else:VQEXTI
+ (match_operand:<VM> 1 "register_operand")
+ (any_extend:VQEXTI (match_operand:<V_QUAD_TRUNC> 2 "register_operand"))
+ (match_operand:VQEXTI 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_vf4 (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine sign_extend/zero_extend(vf8) and vcond_mask
+(define_insn_and_split "*cond_<optab><v_oct_trunc><mode>"
+ [(set (match_operand:VOEXTI 0 "register_operand")
+ (if_then_else:VOEXTI
+ (match_operand:<VM> 1 "register_operand")
+ (any_extend:VOEXTI (match_operand:<V_OCT_TRUNC> 2 "register_operand"))
+ (match_operand:VOEXTI 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_vf8 (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine trunc(vf2) + vcond_mask
+(define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
+ [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand")
+ (if_then_else:<V_DOUBLE_TRUNC>
+ (match_operand:<VM> 1 "register_operand")
+ (truncate:<V_DOUBLE_TRUNC>
+ (match_operand:VWEXTI 2 "register_operand"))
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_trunc (<MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 006e174ebd5..4859805b8f7 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -633,22 +633,28 @@
[(set_attr "type" "vext")
(set_attr "mode" "<MODE>")])
-(define_expand "<optab><v_quad_trunc><mode>2"
+(define_insn_and_split "<optab><v_quad_trunc><mode>2"
[(set (match_operand:VQEXTI 0 "register_operand")
(any_extend:VQEXTI
(match_operand:<V_QUAD_TRUNC> 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred_vf4 (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
})
-(define_expand "<optab><v_oct_trunc><mode>2"
+(define_insn_and_split "<optab><v_oct_trunc><mode>2"
[(set (match_operand:VOEXTI 0 "register_operand")
(any_extend:VOEXTI
(match_operand:<V_OCT_TRUNC> 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred_vf8 (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
@@ -687,13 +693,8 @@
"TARGET_VECTOR"
{
rtx half = gen_reg_rtx (<V_DOUBLE_TRUNC>mode);
- rtx opshalf[] = {half, operands[1]};
- insn_code icode = code_for_pred_trunc (<MODE>mode);
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, opshalf);
-
- rtx ops[] = {operands[0], half};
- icode = code_for_pred_trunc (<V_DOUBLE_TRUNC>mode);
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops);
+ emit_insn (gen_trunc<mode><v_double_trunc>2 (half, operands[1]));
+ emit_insn (gen_trunc<v_double_trunc><v_quad_trunc>2 (operands[0], half));
DONE;
})
@@ -707,19 +708,9 @@
(match_operand:VOEXTI 1 "register_operand")))]
"TARGET_VECTOR"
{
- rtx half = gen_reg_rtx (<V_DOUBLE_TRUNC>mode);
- rtx opshalf[] = {half, operands[1]};
- insn_code icode = code_for_pred_trunc (<MODE>mode);
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, opshalf);
-
rtx quarter = gen_reg_rtx (<V_QUAD_TRUNC>mode);
- rtx opsquarter[] = {quarter, half};
- icode = code_for_pred_trunc (<V_DOUBLE_TRUNC>mode);
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, opsquarter);
-
- rtx ops[] = {operands[0], quarter};
- icode = code_for_pred_trunc (<V_QUAD_TRUNC>mode);
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops);
+ emit_insn (gen_trunc<mode><v_quad_trunc>2 (quarter, operands[1]));
+ emit_insn (gen_trunc<v_quad_trunc><v_oct_trunc>2 (operands[0], quarter));
DONE;
})
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c
index 3b288466394..315d2de0a8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/narrow-3.c
@@ -27,5 +27,5 @@
TEST_ALL ()
-/* { dg-final { scan-assembler-times {\tvnsra\.wx} 4 } } */
+/* { dg-final { scan-assembler-times {\tvnsra\.wx} 8 } } */
/* { dg-final { scan-assembler-times {\tvnsrl\.wx} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h
new file mode 100644
index 00000000000..c8ef6df399d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-1.h
@@ -0,0 +1,47 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \
+ void __attribute__ ((noipa)) \
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \
+ OLD_TYPE *__restrict a, \
+ NEW_TYPE *__restrict b, \
+ OLD_TYPE *__restrict pred, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \
+ } \
+ }
+
+/* INT -> wider-INT */
+#define TEST_ALL_X2X_WIDER(T) \
+ T (uint8_t, uint16_t) \
+ T (uint8_t, uint32_t) \
+ T (uint8_t, uint64_t) \
+ T (int8_t, int16_t) \
+ T (int8_t, int32_t) \
+ T (int8_t, int64_t) \
+ T (uint16_t, uint32_t) \
+ T (uint16_t, uint64_t) \
+ T (int16_t, int32_t) \
+ T (int16_t, int64_t) \
+ T (uint32_t, uint64_t) \
+ T (int32_t, int64_t)
+
+/* INT -> narrower-INT */
+#define TEST_ALL_X2X_NARROWER(T) \
+ T (uint16_t, uint8_t) \
+ T (int16_t, int8_t) \
+ T (uint32_t, uint8_t) \
+ T (int32_t, int8_t) \
+ T (uint64_t, uint8_t) \
+ T (int64_t, int8_t) \
+ T (uint32_t, uint16_t) \
+ T (int32_t, int16_t) \
+ T (uint64_t, uint16_t) \
+ T (int64_t, int16_t) \
+ T (uint64_t, uint32_t) \
+ T (int64_t, int32_t)
+
+TEST_ALL_X2X_WIDER (DEF_LOOP)
+TEST_ALL_X2X_NARROWER (DEF_LOOP)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h
new file mode 100644
index 00000000000..f53c1b3fde9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-2.h
@@ -0,0 +1,46 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \
+ void __attribute__ ((noipa)) \
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \
+ OLD_TYPE *__restrict a, NEW_TYPE b, \
+ OLD_TYPE *__restrict pred, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \
+ } \
+ }
+
+/* INT -> wider-INT */
+#define TEST_ALL_X2X_WIDER(T) \
+ T (uint8_t, uint16_t) \
+ T (uint8_t, uint32_t) \
+ T (uint8_t, uint64_t) \
+ T (int8_t, int16_t) \
+ T (int8_t, int32_t) \
+ T (int8_t, int64_t) \
+ T (uint16_t, uint32_t) \
+ T (uint16_t, uint64_t) \
+ T (int16_t, int32_t) \
+ T (int16_t, int64_t) \
+ T (uint32_t, uint64_t) \
+ T (int32_t, int64_t)
+
+/* INT -> narrower-INT */
+#define TEST_ALL_X2X_NARROWER(T) \
+ T (uint16_t, uint8_t) \
+ T (int16_t, int8_t) \
+ T (uint32_t, uint8_t) \
+ T (int32_t, int8_t) \
+ T (uint64_t, uint8_t) \
+ T (int64_t, int8_t) \
+ T (uint32_t, uint16_t) \
+ T (int32_t, int16_t) \
+ T (uint64_t, uint16_t) \
+ T (int64_t, int16_t) \
+ T (uint64_t, uint32_t) \
+ T (int64_t, int32_t)
+
+TEST_ALL_X2X_WIDER (DEF_LOOP)
+TEST_ALL_X2X_NARROWER (DEF_LOOP)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
new file mode 100644
index 00000000000..8c07e427560
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_convert_int2int-1.h"
+
+/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
+
+/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+
+/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
new file mode 100644
index 00000000000..74490cdc055
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv32-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_convert_int2int-2.h"
+
+/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
+
+/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+
+/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
new file mode 100644
index 00000000000..00357966ba6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-1.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_convert_int2int-1.h"
+
+/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
+
+/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+
+/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
new file mode 100644
index 00000000000..3c4ad9c4f66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int-rv64-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_convert_int2int-2.h"
+
+/* { dg-final { scan-assembler-times {\tvzext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf2\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvzext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf4\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvzext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
+/* { dg-final { scan-assembler-times {\tvsext\.vf8\tv[0-9]+,v[0-9]+,v0\.t} 1 } } */
+
+/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 12 } } */
+/* { dg-final { scan-assembler-times {\tvncvt\.x\.x\.w\tv[0-9]+,v[0-9]+\n} 8 } } */
+
+/* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c
new file mode 100644
index 00000000000..04f24168a38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_convert_int2int-1.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \
+ { \
+ NEW_TYPE r[N], b[N]; \
+ OLD_TYPE a[N], pred[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ b[i] = (i % 9) * (i % 7 + 1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ } \
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \
+ for (int i = 0; i < N; ++i) \
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_X2X_WIDER (TEST_LOOP)
+ TEST_ALL_X2X_NARROWER (TEST_LOOP)
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c
new file mode 100644
index 00000000000..7a6897bf029
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2int_run-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_convert_int2int-2.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \
+ { \
+ NEW_TYPE r[N], b = 189; \
+ OLD_TYPE a[N], pred[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ } \
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \
+ for (int i = 0; i < N; ++i) \
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_X2X_WIDER (TEST_LOOP)
+ TEST_ALL_X2X_NARROWER (TEST_LOOP)
+ return 0;
+}
--
2.36.3
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 3/4] RISC-V: Add conditional autovec convert(FP<->FP) patterns
2023-09-01 5:45 [PATCH 0/4] Add conditional autovec convert patterns Lehua Ding
2023-09-01 5:45 ` [PATCH 1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api Lehua Ding
2023-09-01 5:45 ` [PATCH 2/4] RISC-V: Add conditional autovec convert(INT<->INT) patterns Lehua Ding
@ 2023-09-01 5:45 ` Lehua Ding
2023-09-01 10:15 ` Robin Dapp
2023-09-01 5:45 ` [PATCH 4/4] RISC-V: Add conditional autovec convert(INT<->FP) patterns Lehua Ding
3 siblings, 1 reply; 10+ messages in thread
From: Lehua Ding @ 2023-09-01 5:45 UTC (permalink / raw)
To: gcc-patches, rdapp.gcc; +Cc: juzhe.zhong, kito.cheng, palmer, jeffreyalaw
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_extend<v_double_trunc><mode>):
New combine pattern.
(*cond_trunc<mode><v_double_trunc>): Ditto.
* config/riscv/autovec.md: Adjust.
* config/riscv/riscv-v.cc (needs_fp_rounding): Add FP extend.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c: New test.
---
gcc/config/riscv/autovec-opt.md | 39 +++++++++++++++++++
gcc/config/riscv/autovec.md | 13 ++-----
gcc/config/riscv/riscv-v.cc | 4 +-
.../autovec/cond/cond_convert_float2float-1.h | 29 ++++++++++++++
.../autovec/cond/cond_convert_float2float-2.h | 28 +++++++++++++
.../cond/cond_convert_float2float-rv32-1.c | 9 +++++
.../cond/cond_convert_float2float-rv32-2.c | 9 +++++
.../cond/cond_convert_float2float-rv64-1.c | 9 +++++
.../cond/cond_convert_float2float-rv64-2.c | 9 +++++
.../cond/cond_convert_float2float_run-1.c | 31 +++++++++++++++
.../cond/cond_convert_float2float_run-2.c | 30 ++++++++++++++
11 files changed, 199 insertions(+), 11 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 6796239d82d..ef468bb9df7 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -824,3 +824,42 @@
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
})
+
+;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask
+(define_insn_and_split "*cond_extend<v_double_trunc><mode>"
+ [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand")
+ (if_then_else:VWEXTF_ZVFHMIN
+ (match_operand:<VM> 1 "register_operand")
+ (float_extend:VWEXTF_ZVFHMIN (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
+ (match_operand:VWEXTF_ZVFHMIN 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_extend (<MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine FP trunc(vf2) + vcond_mask
+(define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
+ [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand")
+ (if_then_else:<V_DOUBLE_TRUNC>
+ (match_operand:<VM> 1 "register_operand")
+ (float_truncate:<V_DOUBLE_TRUNC>
+ (match_operand:VWEXTF_ZVFHMIN 2 "register_operand"))
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_trunc (<MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4859805b8f7..a4ac688e373 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -742,13 +742,8 @@
"TARGET_VECTOR && (TARGET_ZVFHMIN || TARGET_ZVFH)"
{
rtx dblw = gen_reg_rtx (<V_DOUBLE_TRUNC>mode);
- insn_code icode = code_for_pred_extend (<V_DOUBLE_TRUNC>mode);
- rtx ops1[] = {dblw, operands[1]};
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops1);
-
- icode = code_for_pred_extend (<MODE>mode);
- rtx ops2[] = {operands[0], dblw};
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops2);
+ emit_insn (gen_extend<v_quad_trunc><v_double_trunc>2 (dblw, operands[1]));
+ emit_insn (gen_extend<v_double_trunc><mode>2 (operands[0], dblw));
DONE;
})
@@ -791,9 +786,7 @@
insn_code icode = code_for_pred_rod_trunc (<MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, opshalf);
- rtx ops[] = {operands[0], half};
- icode = code_for_pred_trunc (<V_DOUBLE_TRUNC>mode);
- riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, ops);
+ emit_insn (gen_trunc<v_double_trunc><v_quad_trunc>2 (operands[0], half));
DONE;
})
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 89ac4743f40..0f414663620 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2966,7 +2966,9 @@ needs_fp_rounding (unsigned icode, machine_mode mode)
return icode != maybe_code_for_pred (SMIN, mode)
&& icode != maybe_code_for_pred (SMAX, mode)
&& icode != maybe_code_for_pred (NEG, mode)
- && icode != maybe_code_for_pred (ABS, mode);
+ && icode != maybe_code_for_pred (ABS, mode)
+ /* narrower-FP -> FP */
+ && icode != maybe_code_for_pred_extend (mode);
}
/* Subroutine to expand COND_LEN_* patterns. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h
new file mode 100644
index 00000000000..4742d926af6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-1.h
@@ -0,0 +1,29 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \
+ void __attribute__ ((noipa)) \
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \
+ OLD_TYPE *__restrict a, \
+ NEW_TYPE *__restrict b, \
+ OLD_TYPE *__restrict pred, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \
+ } \
+ }
+
+/* FP -> wider-FP */
+#define TEST_ALL_F2F_WIDER(T) \
+ T (_Float16, float) \
+ T (_Float16, double) \
+ T (float, double)
+
+/* FP -> narrower-FP */
+#define TEST_ALL_F2F_NARROWER(T) \
+ T (float, _Float16) \
+ T (double, _Float16) \
+ T (double, float)
+
+TEST_ALL_F2F_WIDER (DEF_LOOP)
+TEST_ALL_F2F_NARROWER (DEF_LOOP)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h
new file mode 100644
index 00000000000..b084eaae19d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-2.h
@@ -0,0 +1,28 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \
+ void __attribute__ ((noipa)) \
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \
+ OLD_TYPE *__restrict a, NEW_TYPE b, \
+ OLD_TYPE *__restrict pred, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \
+ } \
+ }
+
+/* FP -> wider-FP */
+#define TEST_ALL_F2F_WIDER(T) \
+ T (_Float16, float) \
+ T (_Float16, double) \
+ T (float, double)
+
+/* FP -> narrower-FP */
+#define TEST_ALL_F2F_NARROWER(T) \
+ T (float, _Float16) \
+ T (double, _Float16) \
+ T (double, float)
+
+TEST_ALL_F2F_WIDER (DEF_LOOP)
+TEST_ALL_F2F_NARROWER (DEF_LOOP)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
new file mode 100644
index 00000000000..e0d9eaa4173
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-1.h"
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
new file mode 100644
index 00000000000..8d963b0397b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv32-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-2.h"
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
new file mode 100644
index 00000000000..9841fdd7f79
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-1.h"
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
new file mode 100644
index 00000000000..03ee19fa9e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float-rv64-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-2.h"
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.f\.v\tv[0-9]+,v[0-9]+\n} 1 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rod\.f\.f\.w\tv[0-9]+,v[0-9]+\n} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
new file mode 100644
index 00000000000..407bbc27c2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-1.c
@@ -0,0 +1,31 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-1.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \
+ { \
+ NEW_TYPE r[N], b[N]; \
+ OLD_TYPE a[N], pred[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ b[i] = (i % 9) * (i % 7 + 1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ } \
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \
+ for (int i = 0; i < N; ++i) \
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_F2F_WIDER (TEST_LOOP)
+ TEST_ALL_F2F_NARROWER (TEST_LOOP)
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
new file mode 100644
index 00000000000..05d217da625
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2float_run-2.c
@@ -0,0 +1,30 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2float-2.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \
+ { \
+ NEW_TYPE r[N], b = 18.02; \
+ OLD_TYPE a[N], pred[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ } \
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \
+ for (int i = 0; i < N; ++i) \
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_F2F_WIDER (TEST_LOOP)
+ TEST_ALL_F2F_NARROWER (TEST_LOOP)
+ return 0;
+}
--
2.36.3
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 4/4] RISC-V: Add conditional autovec convert(INT<->FP) patterns
2023-09-01 5:45 [PATCH 0/4] Add conditional autovec convert patterns Lehua Ding
` (2 preceding siblings ...)
2023-09-01 5:45 ` [PATCH 3/4] RISC-V: Add conditional autovec convert(FP<->FP) patterns Lehua Ding
@ 2023-09-01 5:45 ` Lehua Ding
2023-09-01 10:27 ` Robin Dapp
3 siblings, 1 reply; 10+ messages in thread
From: Lehua Ding @ 2023-09-01 5:45 UTC (permalink / raw)
To: gcc-patches, rdapp.gcc; +Cc: juzhe.zhong, kito.cheng, palmer, jeffreyalaw
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_<optab><mode><vconvert>):
New combine pattern.
(*cond_<float_cvt><vconvert><mode>): Ditto.
(*cond_<optab><vnconvert><mode>): Ditto.
(*cond_<float_cvt><vnconvert><mode>): Ditto.
(*cond_<optab><mode><vnconvert>): Ditto.
(*cond_<float_cvt><mode><vnconvert>2): Ditto.
* config/riscv/autovec.md (<optab><mode><vconvert>2): Adjust.
(<float_cvt><vconvert><mode>2): Adjust.
(<optab><vnconvert><mode>2): Adjust.
(<float_cvt><vnconvert><mode>2): Adjust.
(<optab><mode><vnconvert>2): Adjust.
(<float_cvt><mode><vnconvert>2): Adjust.
* config/riscv/riscv-v.cc (needs_fp_rounding): Add INT->FP extend.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c: New test.
---
gcc/config/riscv/autovec-opt.md | 120 ++++++++++++++++++
gcc/config/riscv/autovec.md | 42 ++++--
gcc/config/riscv/riscv-v.cc | 5 +-
.../autovec/cond/cond_convert_float2int-1.h | 51 ++++++++
.../autovec/cond/cond_convert_float2int-2.h | 50 ++++++++
.../cond/cond_convert_float2int-rv32-1.c | 15 +++
.../cond/cond_convert_float2int-rv32-2.c | 15 +++
.../cond/cond_convert_float2int-rv64-1.c | 15 +++
.../cond/cond_convert_float2int-rv64-2.c | 15 +++
.../cond/cond_convert_float2int_run-1.c | 32 +++++
.../cond/cond_convert_float2int_run-2.c | 31 +++++
.../autovec/cond/cond_convert_int2float-1.h | 45 +++++++
.../autovec/cond/cond_convert_int2float-2.h | 44 +++++++
.../cond/cond_convert_int2float-rv32-1.c | 13 ++
.../cond/cond_convert_int2float-rv32-2.c | 13 ++
.../cond/cond_convert_int2float-rv64-1.c | 13 ++
.../cond/cond_convert_int2float-rv64-2.c | 13 ++
.../cond/cond_convert_int2float_run-1.c | 32 +++++
.../cond/cond_convert_int2float_run-2.c | 31 +++++
19 files changed, 582 insertions(+), 13 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index ef468bb9df7..1ca5ce97193 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -863,3 +863,123 @@
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
})
+
+;; Combine convert(FP->INT) + vcond_mask
+(define_insn_and_split "*cond_<optab><mode><vconvert>"
+ [(set (match_operand:<VCONVERT> 0 "register_operand")
+ (if_then_else:<VCONVERT>
+ (match_operand:<VM> 1 "register_operand")
+ (any_fix:<VCONVERT>
+ (match_operand:VF 2 "register_operand"))
+ (match_operand:<VCONVERT> 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine convert(INT->FP) + vcond_mask
+(define_insn_and_split "*cond_<float_cvt><vconvert><mode>"
+ [(set (match_operand:VF 0 "register_operand")
+ (if_then_else:VF
+ (match_operand:<VM> 1 "register_operand")
+ (any_float:VF
+ (match_operand:<VCONVERT> 2 "register_operand"))
+ (match_operand:VF 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine convert(FP->2xINT) + vcond_mask
+(define_insn_and_split "*cond_<optab><vnconvert><mode>"
+ [(set (match_operand:VWCONVERTI 0 "register_operand")
+ (if_then_else:VWCONVERTI
+ (match_operand:<VM> 1 "register_operand")
+ (any_fix:VWCONVERTI
+ (match_operand:<VNCONVERT> 2 "register_operand"))
+ (match_operand:VWCONVERTI 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine convert(INT->2xFP) + vcond_mask
+(define_insn_and_split "*cond_<float_cvt><vnconvert><mode>"
+ [(set (match_operand:VF 0 "register_operand")
+ (if_then_else:VF
+ (match_operand:<VM> 1 "register_operand")
+ (any_float:VF
+ (match_operand:<VNCONVERT> 2 "register_operand"))
+ (match_operand:VF 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine convert(2xFP->INT) + vcond_mask
+(define_insn_and_split "*cond_<optab><mode><vnconvert>"
+ [(set (match_operand:<VNCONVERT> 0 "register_operand")
+ (if_then_else:<VNCONVERT>
+ (match_operand:<VM> 1 "register_operand")
+ (any_fix:<VNCONVERT>
+ (match_operand:VF 2 "register_operand"))
+ (match_operand:<VNCONVERT> 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
+
+;; Combine convert(2xINT->FP) + vcond_mask
+(define_insn_and_split "*cond_<float_cvt><mode><vnconvert>2"
+ [(set (match_operand:<VNCONVERT> 0 "register_operand")
+ (if_then_else:<VNCONVERT>
+ (match_operand:<VM> 1 "register_operand")
+ (any_float:<VNCONVERT>
+ (match_operand:VWCONVERTI 2 "register_operand"))
+ (match_operand:<VNCONVERT> 3 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3],
+ gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
+ riscv_vector::expand_cond_len_unop (icode, ops);
+ DONE;
+})
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index a4ac688e373..35e98a6f3f7 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -803,11 +803,14 @@
;; - vfcvt.rtz.x.f.v
;; -------------------------------------------------------------------------
-(define_expand "<optab><mode><vconvert>2"
+(define_insn_and_split "<optab><mode><vconvert>2"
[(set (match_operand:<VCONVERT> 0 "register_operand")
(any_fix:<VCONVERT>
(match_operand:VF 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
@@ -822,11 +825,14 @@
;; - vfcvt.f.x.v
;; -------------------------------------------------------------------------
-(define_expand "<float_cvt><vconvert><mode>2"
+(define_insn_and_split "<float_cvt><vconvert><mode>2"
[(set (match_operand:VF 0 "register_operand")
(any_float:VF
(match_operand:<VCONVERT> 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands);
@@ -844,11 +850,14 @@
;; - vfwcvt.rtz.xu.f.v
;; - vfwcvt.rtz.x.f.v
;; -------------------------------------------------------------------------
-(define_expand "<optab><vnconvert><mode>2"
+(define_insn_and_split "<optab><vnconvert><mode>2"
[(set (match_operand:VWCONVERTI 0 "register_operand")
(any_fix:VWCONVERTI
(match_operand:<VNCONVERT> 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
@@ -862,11 +871,14 @@
;; - vfwcvt.f.xu.v
;; - vfwcvt.f.x.v
;; -------------------------------------------------------------------------
-(define_expand "<float_cvt><vnconvert><mode>2"
+(define_insn_and_split "<float_cvt><vnconvert><mode>2"
[(set (match_operand:VF 0 "register_operand")
(any_float:VF
(match_operand:<VNCONVERT> 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
@@ -880,11 +892,14 @@
;; - vfncvt.rtz.xu.f.v
;; - vfncvt.rtz.x.f.v
;; -------------------------------------------------------------------------
-(define_expand "<optab><mode><vnconvert>2"
+(define_insn_and_split "<optab><mode><vnconvert>2"
[(set (match_operand:<VNCONVERT> 0 "register_operand")
(any_fix:<VNCONVERT>
(match_operand:VF 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
@@ -898,11 +913,14 @@
;; - vfncvt.f.xu.w
;; - vfncvt.f.x.w
;; -------------------------------------------------------------------------
-(define_expand "<float_cvt><mode><vnconvert>2"
+(define_insn_and_split "<float_cvt><mode><vnconvert>2"
[(set (match_operand:<VNCONVERT> 0 "register_operand")
(any_float:<VNCONVERT>
(match_operand:VWCONVERTI 1 "register_operand")))]
- "TARGET_VECTOR"
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
{
insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 0f414663620..cdb459f2a47 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2968,7 +2968,10 @@ needs_fp_rounding (unsigned icode, machine_mode mode)
&& icode != maybe_code_for_pred (NEG, mode)
&& icode != maybe_code_for_pred (ABS, mode)
/* narrower-FP -> FP */
- && icode != maybe_code_for_pred_extend (mode);
+ && icode != maybe_code_for_pred_extend (mode)
+ /* narrower-INT -> FP */
+ && icode != maybe_code_for_pred_widen (FLOAT, mode)
+ && icode != maybe_code_for_pred_widen (UNSIGNED_FLOAT, mode);
}
/* Subroutine to expand COND_LEN_* patterns. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h
new file mode 100644
index 00000000000..2df68aa2d1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-1.h
@@ -0,0 +1,51 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \
+ void __attribute__ ((noipa)) \
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \
+ OLD_TYPE *__restrict a, \
+ NEW_TYPE *__restrict b, \
+ OLD_TYPE *__restrict pred, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \
+ } \
+ }
+
+/* FP -> INT */
+#define TEST_ALL_F2X_SAME(T) \
+ T (_Float16, uint16_t) \
+ T (_Float16, int16_t) \
+ T (float, uint32_t) \
+ T (float, int32_t) \
+ T (double, uint64_t) \
+ T (double, int64_t)
+
+/* FP -> wider-INT */
+#define TEST_ALL_F2X_WIDER(T) \
+ T (_Float16, uint32_t) \
+ T (_Float16, int32_t) \
+ T (_Float16, uint64_t) \
+ T (_Float16, int64_t) \
+ T (float, uint64_t) \
+ T (float, int64_t)
+
+/* FP -> narrower-INT */
+#define TEST_ALL_F2X_NARROWER(T) \
+ T (_Float16, uint8_t) \
+ T (_Float16, int8_t) \
+ T (float, uint8_t) \
+ T (float, int8_t) \
+ T (float, uint16_t) \
+ T (float, int16_t) \
+ T (double, uint8_t) \
+ T (double, int8_t) \
+ T (double, uint16_t) \
+ T (double, int16_t) \
+ T (double, uint32_t) \
+ T (double, int32_t)
+
+TEST_ALL_F2X_SAME (DEF_LOOP)
+TEST_ALL_F2X_WIDER (DEF_LOOP)
+TEST_ALL_F2X_NARROWER (DEF_LOOP)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h
new file mode 100644
index 00000000000..9735141faa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-2.h
@@ -0,0 +1,50 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \
+ void __attribute__ ((noipa)) \
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \
+ OLD_TYPE *__restrict a, NEW_TYPE b, \
+ OLD_TYPE *__restrict pred, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \
+ } \
+ }
+
+/* FP -> INT */
+#define TEST_ALL_F2X_SAME(T) \
+ T (_Float16, uint16_t) \
+ T (_Float16, int16_t) \
+ T (float, uint32_t) \
+ T (float, int32_t) \
+ T (double, uint64_t) \
+ T (double, int64_t)
+
+/* FP -> wider-INT */
+#define TEST_ALL_F2X_WIDER(T) \
+ T (_Float16, uint32_t) \
+ T (_Float16, int32_t) \
+ T (_Float16, uint64_t) \
+ T (_Float16, int64_t) \
+ T (float, uint64_t) \
+ T (float, int64_t)
+
+/* FP -> narrower-INT */
+#define TEST_ALL_F2X_NARROWER(T) \
+ T (_Float16, uint8_t) \
+ T (_Float16, int8_t) \
+ T (float, uint8_t) \
+ T (float, int8_t) \
+ T (float, uint16_t) \
+ T (float, int16_t) \
+ T (double, uint8_t) \
+ T (double, int8_t) \
+ T (double, uint16_t) \
+ T (double, int16_t) \
+ T (double, uint32_t) \
+ T (double, int32_t)
+
+TEST_ALL_F2X_SAME (DEF_LOOP)
+TEST_ALL_F2X_WIDER (DEF_LOOP)
+TEST_ALL_F2X_NARROWER (DEF_LOOP)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
new file mode 100644
index 00000000000..0702b60c551
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2int-1.h"
+
+/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */
+
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
new file mode 100644
index 00000000000..6eeed28ee6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv32-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2int-2.h"
+
+/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */
+
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
new file mode 100644
index 00000000000..43f7150fa0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2int-1.h"
+
+/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */
+
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
new file mode 100644
index 00000000000..e4a1b175d9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int-rv64-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_float2int-2.h"
+
+/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.xu\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.rtz\.x\.f\.v\tv[0-9]+,v[0-9]+\n} 2 } } */
+
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.xu\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.rtz\.x\.f\.w\tv[0-9]+,v[0-9]+\n} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
new file mode 100644
index 00000000000..65b54bb3c83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_convert_float2int-1.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \
+ { \
+ NEW_TYPE r[N], b[N]; \
+ OLD_TYPE a[N], pred[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ b[i] = (i % 9) * (i % 7 + 1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ } \
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \
+ for (int i = 0; i < N; ++i) \
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_F2X_SAME (TEST_LOOP)
+ TEST_ALL_F2X_WIDER (TEST_LOOP)
+ TEST_ALL_F2X_NARROWER (TEST_LOOP)
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
new file mode 100644
index 00000000000..030ea2c1964
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_float2int_run-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_convert_float2int-2.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \
+ { \
+ NEW_TYPE r[N], b = 192; \
+ OLD_TYPE a[N], pred[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ } \
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \
+ for (int i = 0; i < N; ++i) \
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_F2X_SAME (TEST_LOOP)
+ TEST_ALL_F2X_WIDER (TEST_LOOP)
+ TEST_ALL_F2X_NARROWER (TEST_LOOP)
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h
new file mode 100644
index 00000000000..5b0baeece41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-1.h
@@ -0,0 +1,45 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \
+ void __attribute__ ((noipa)) \
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \
+ OLD_TYPE *__restrict a, \
+ NEW_TYPE *__restrict b, \
+ OLD_TYPE *__restrict pred, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b[i]; \
+ } \
+ }
+
+/* INT -> FP */
+#define TEST_ALL_X2F_SAME(T) \
+ T (uint16_t, _Float16) \
+ T (int16_t, _Float16) \
+ T (uint32_t, float) \
+ T (int32_t, float) \
+ T (uint64_t, double) \
+ T (int64_t, double)
+
+/* INT -> wider-FP */
+#define TEST_ALL_X2F_WIDER(T) \
+ T (uint16_t, float) \
+ T (int16_t, float) \
+ T (uint16_t, double) \
+ T (int16_t, double) \
+ T (uint32_t, double) \
+ T (int32_t, double)
+
+/* INT -> narrower-FP */
+#define TEST_ALL_X2F_NARROWER(T) \
+ T (uint32_t, _Float16) \
+ T (int32_t, _Float16) \
+ T (uint64_t, _Float16) \
+ T (int64_t, _Float16) \
+ T (uint64_t, float) \
+ T (int64_t, float)
+
+TEST_ALL_X2F_SAME (DEF_LOOP)
+TEST_ALL_X2F_WIDER (DEF_LOOP)
+TEST_ALL_X2F_NARROWER (DEF_LOOP)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h
new file mode 100644
index 00000000000..2177c946de8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-2.h
@@ -0,0 +1,44 @@
+#include <stdint.h>
+
+#define DEF_LOOP(OLD_TYPE, NEW_TYPE) \
+ void __attribute__ ((noipa)) \
+ test_##OLD_TYPE##_2_##NEW_TYPE (NEW_TYPE *__restrict r, \
+ OLD_TYPE *__restrict a, NEW_TYPE b, \
+ OLD_TYPE *__restrict pred, int n) \
+ { \
+ for (int i = 0; i < n; ++i) \
+ { \
+ r[i] = pred[i] ? (NEW_TYPE) a[i] : b; \
+ } \
+ }
+
+/* INT -> FP */
+#define TEST_ALL_X2F_SAME(T) \
+ T (uint16_t, _Float16) \
+ T (int16_t, _Float16) \
+ T (uint32_t, float) \
+ T (int32_t, float) \
+ T (uint64_t, double) \
+ T (int64_t, double)
+
+/* INT -> wider-FP */
+#define TEST_ALL_X2F_WIDER(T) \
+ T (uint16_t, float) \
+ T (int16_t, float) \
+ T (uint16_t, double) \
+ T (int16_t, double) \
+ T (uint32_t, double) \
+ T (int32_t, double)
+
+/* INT -> narrower-FP */
+#define TEST_ALL_X2F_NARROWER(T) \
+ T (uint32_t, _Float16) \
+ T (int32_t, _Float16) \
+ T (uint64_t, _Float16) \
+ T (int64_t, _Float16) \
+ T (uint64_t, float) \
+ T (int64_t, float)
+
+TEST_ALL_X2F_SAME (DEF_LOOP)
+TEST_ALL_X2F_WIDER (DEF_LOOP)
+TEST_ALL_X2F_NARROWER (DEF_LOOP)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
new file mode 100644
index 00000000000..fbb1a28791d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_int2float-2.h"
+
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
new file mode 100644
index 00000000000..fbb1a28791d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_int2float-2.h"
+
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
new file mode 100644
index 00000000000..2f85c819709
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_int2float-1.h"
+
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
new file mode 100644
index 00000000000..2f4fdd728bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+
+#include "cond_convert_int2float-2.h"
+
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 3 } } */
+
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.xu\.v\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfwcvt\.f\.x\.v\tv[0-9]+,v[0-9]+,v0\.t} 4 } } */
+
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
+/* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
new file mode 100644
index 00000000000..10bc06757c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-1.c
@@ -0,0 +1,32 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_convert_int2float-1.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \
+ { \
+ NEW_TYPE r[N], b[N]; \
+ OLD_TYPE a[N], pred[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ b[i] = (i % 9) * (i % 7 + 1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ } \
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \
+ for (int i = 0; i < N; ++i) \
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b[i])) \
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_X2F_SAME (TEST_LOOP)
+ TEST_ALL_X2F_WIDER (TEST_LOOP)
+ TEST_ALL_X2F_NARROWER (TEST_LOOP)
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
new file mode 100644
index 00000000000..08d27e6dca1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float_run-2.c
@@ -0,0 +1,31 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include "cond_convert_int2float-2.h"
+
+#define N 99
+
+#define TEST_LOOP(OLD_TYPE, NEW_TYPE) \
+ { \
+ NEW_TYPE r[N], b = 192.12; \
+ OLD_TYPE a[N], pred[N]; \
+ for (int i = 0; i < N; ++i) \
+ { \
+ a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \
+ pred[i] = (i % 7 < 4); \
+ asm volatile("" ::: "memory"); \
+ } \
+ test_##OLD_TYPE##_2_##NEW_TYPE (r, a, b, pred, N); \
+ for (int i = 0; i < N; ++i) \
+ if (r[i] != (pred[i] ? (NEW_TYPE) a[i] : b)) \
+ __builtin_abort (); \
+ }
+
+int
+main ()
+{
+ TEST_ALL_X2F_SAME (TEST_LOOP)
+ TEST_ALL_X2F_WIDER (TEST_LOOP)
+ TEST_ALL_X2F_NARROWER (TEST_LOOP)
+ return 0;
+}
--
2.36.3
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