From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id 3B2113858D35 for ; Wed, 6 Sep 2023 09:48:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3B2113858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp79t1693993681tcml00cd Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 06 Sep 2023 17:48:00 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: mRz6/7wsmIhtv7RVaemk2JCel9zmVCOHt1YHikYkA9YSgStr686ZPFDHYO8lp uNrJZbJUdyfwkkBWctc0RGdtiLI0fgM29DdFU10phzIjvTYEhK4WAgpiq3zsJi3RY8jNT7v p4bMEOBuoi9RNS2ilFx6OuWIumK01DcFRuyd/NMkCk9nQ46HzwwF10eFrAXvuK2KeixWgp1 IhPJ3f0iWZO5YKXN+9uu0ucJIo1otxIotCcu3zWCz/1MIULnK6CCpeSbBz/lI0dernO6/BU sFiiRs8WQ0502sF+YYp8ewKX9Nn/veMWCPjYWWOLVmG+12oJpkfZzDPW2wlcj8wN02qTjRP E/8PVsAU+RRJB95xzleBEt+KmEQMUvZTWejPql+ErEIJ6O7ggpG/lE6ti5W6KD87YJKri94 X-QQ-GoodBg: 2 X-BIZMAIL-ID: 11135231160392943862 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296] Date: Wed, 6 Sep 2023 17:47:59 +0800 Message-Id: <20230906094759.4040203-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch fix incorrect mode tieable between DI and V2SI which cause ICE in RA. PR target/111296 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_modes_tieable_p): Fix bug. gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/pr111296.C: New test. --- gcc/config/riscv/riscv.cc | 7 +++++++ .../g++.target/riscv/rvv/base/pr111296.C | 18 ++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 228515acc1f..2c0c4c2f3ae 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7648,6 +7648,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) static bool riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2) { + /* We don't allow different REG_CLASS modes tieable since it + will cause ICE in register allocation (RA). + E.g. V2SI and DI are not tieable. */ + if (riscv_v_ext_mode_p (mode1) && !riscv_v_ext_mode_p (mode2)) + return false; + else if (riscv_v_ext_mode_p (mode2) && !riscv_v_ext_mode_p (mode1)) + return false; return (mode1 == mode2 || !(GET_MODE_CLASS (mode1) == MODE_FLOAT && GET_MODE_CLASS (mode2) == MODE_FLOAT)); diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C new file mode 100644 index 00000000000..6eb14fd83a8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-std=c++03 -march=rv64gcv -mabi=lp64d -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable" } */ + +struct a +{ + int b; + int c; +}; +int d; +a +e () +{ + a f; + int g = d - 1, h = d / 2 - 1; + f.b = g; + f.c = h; + return f; +} -- 2.36.3