* [PATCH] RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit
@ 2023-09-06 12:18 Juzhe-Zhong
2023-09-06 13:38 ` Robin Dapp
0 siblings, 1 reply; 3+ messages in thread
From: Juzhe-Zhong @ 2023-09-06 12:18 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, kito.cheng, jeffreyalaw, rdapp.gcc, Juzhe-Zhong
Previously, I add TARGET_64BIT condtion to block VLS modes with size = 64bit in RV32 system
E.g. V8QI
Since I realized such modes may cause inferior codegen for some situations in RV32 system.
However, this is really quite ugly and it cause ICE for some cases in RV32:
FAIL: gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c (internal compiler error: in require, at machmode.h:313)
3937FAIL: gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c (test for excess errors)
For inferior codegen in RV32 system, we should try another reasonable approach to fix it.
Remove those TARGET_64BIT and fix ICE.
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (VLS_ENTRY): Remove TARGET_64BIT
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
* gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64d-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64f-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/zve64x-1.c: Ditto.
---
gcc/config/riscv/riscv-vector-switch.def | 8 ++++----
.../gcc.target/riscv/rvv/autovec/partial/slp-9.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c | 2 +-
17 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def
index c035dc3558b..174e5a181c6 100644
--- a/gcc/config/riscv/riscv-vector-switch.def
+++ b/gcc/config/riscv/riscv-vector-switch.def
@@ -309,7 +309,7 @@ VLS_ENTRY (V4096BI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096)
VLS_ENTRY (V1QI, TARGET_VECTOR_VLS)
VLS_ENTRY (V2QI, TARGET_VECTOR_VLS)
VLS_ENTRY (V4QI, TARGET_VECTOR_VLS)
-VLS_ENTRY (V8QI, TARGET_VECTOR_VLS && TARGET_64BIT)
+VLS_ENTRY (V8QI, TARGET_VECTOR_VLS)
VLS_ENTRY (V16QI, TARGET_VECTOR_VLS)
VLS_ENTRY (V32QI, TARGET_VECTOR_VLS)
VLS_ENTRY (V64QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64)
@@ -321,7 +321,7 @@ VLS_ENTRY (V2048QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048)
VLS_ENTRY (V4096QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096)
VLS_ENTRY (V1HI, TARGET_VECTOR_VLS)
VLS_ENTRY (V2HI, TARGET_VECTOR_VLS)
-VLS_ENTRY (V4HI, TARGET_VECTOR_VLS && TARGET_64BIT)
+VLS_ENTRY (V4HI, TARGET_VECTOR_VLS)
VLS_ENTRY (V8HI, TARGET_VECTOR_VLS)
VLS_ENTRY (V16HI, TARGET_VECTOR_VLS)
VLS_ENTRY (V32HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64)
@@ -332,7 +332,7 @@ VLS_ENTRY (V512HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024)
VLS_ENTRY (V1024HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048)
VLS_ENTRY (V2048HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096)
VLS_ENTRY (V1SI, TARGET_VECTOR_VLS)
-VLS_ENTRY (V2SI, TARGET_VECTOR_VLS && TARGET_64BIT)
+VLS_ENTRY (V2SI, TARGET_VECTOR_VLS)
VLS_ENTRY (V4SI, TARGET_VECTOR_VLS)
VLS_ENTRY (V8SI, TARGET_VECTOR_VLS)
VLS_ENTRY (V16SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64)
@@ -342,7 +342,7 @@ VLS_ENTRY (V128SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512)
VLS_ENTRY (V256SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024)
VLS_ENTRY (V512SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048)
VLS_ENTRY (V1024SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096)
-VLS_ENTRY (V1DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_64BIT)
+VLS_ENTRY (V1DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64)
VLS_ENTRY (V2DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64)
VLS_ENTRY (V4DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64)
VLS_ENTRY (V8DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
index 59b07e265e8..5fba27c7a35 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
+/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */
#include <stdint.h>
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c
index 54a36ae72d2..867b4e85783 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
index 345e2f963d5..1a4362beb3b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c
index 754aee23e91..d22eb15dd21 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c
index 52a2c2b42b1..54d82a88650 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c
index 7a911d154dd..6119a10c145 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c
index 8d26abbe130..fd85203c4bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c
index 15c481624ea..74825c476a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
index 1394f08f2b9..c477a96c37d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c
index 46be1f4da5b..8096c28939d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c
index 90e30843be1..9a133d11f46 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c
index 02ac73bcb05..00303499b89 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c
index 50cbfe13175..8809a400e18 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
index c5e89996fa4..94d88cc5312 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
index 6c2a002de9c..87f3b2f709c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
index 8fbfa8a8b68..64fbe454d33 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
@@ -3,4 +3,4 @@
#include "template-1.h"
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
--
2.36.3
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit
2023-09-06 12:18 [PATCH] RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit Juzhe-Zhong
@ 2023-09-06 13:38 ` Robin Dapp
2023-09-06 14:00 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: Robin Dapp @ 2023-09-06 13:38 UTC (permalink / raw)
To: Juzhe-Zhong, gcc-patches; +Cc: rdapp.gcc, kito.cheng, kito.cheng, jeffreyalaw
LGTM.
Regards
Robin
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit
2023-09-06 13:38 ` Robin Dapp
@ 2023-09-06 14:00 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-09-06 14:00 UTC (permalink / raw)
To: Robin Dapp, Juzhe-Zhong, gcc-patches; +Cc: kito.cheng, kito.cheng
Committed, thanks Robin.
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of Robin Dapp via Gcc-patches
Sent: Wednesday, September 6, 2023 9:39 PM
To: Juzhe-Zhong <juzhe.zhong@rivai.ai>; gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com; kito.cheng@gmail.com
Subject: Re: [PATCH] RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit
LGTM.
Regards
Robin
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-09-06 12:18 [PATCH] RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit Juzhe-Zhong
2023-09-06 13:38 ` Robin Dapp
2023-09-06 14:00 ` Li, Pan2
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