From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id 1050A3858409 for ; Wed, 6 Sep 2023 12:18:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1050A3858409 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp87t1694002697t2q355ks Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 06 Sep 2023 20:18:15 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: qcKkmz/zJhzQU0g89hgHzUHLhs6pyoq/5XZNxIduW+FElqFSWgLb96i0rI1lX iDWU72PJYklSLGC7Y+uUPq4x76NkNkHAQEpG8KWvFuNOKXo8dCwHBgdlpyfAJcXpwVXj+et Be4uIy0URc6o7FasD4N2Mtdwss1NFLa089P0uawZn9lVi92JKk12CIZb1QTUoAxB56Daz/O 5SloY1i1fNtTYvD9dSloy5qkoYYw0U3rm1ghzoCo0VaWaMzQbWNWNpxL1yI4dqfOX1PGEdm yzyPh3uRh+6VhSG6Irjr9JDB8ir4+eaU2M9VJJk25jgXEKijPatvgcbQrKK7WRV1DWjTbZQ N8wzTG0H9tdNnjFR3pcDyrnDDg+m7PXqHS6DQtKqHS3MsPH7wOeDq3Biz57X/7Xl3nYiJ5I qNtX1YleI2nktNdDzT+p+Q== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 10347619357413628710 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with size = 64bit Date: Wed, 6 Sep 2023 20:18:14 +0800 Message-Id: <20230906121814.1445594-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Previously, I add TARGET_64BIT condtion to block VLS modes with size = 64bit in RV32 system E.g. V8QI Since I realized such modes may cause inferior codegen for some situations in RV32 system. However, this is really quite ugly and it cause ICE for some cases in RV32: FAIL: gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c (internal compiler error: in require, at machmode.h:313) 3937FAIL: gcc.target/riscv/rvv/autovec/conversions/vfncvt-ftoi-run.c (test for excess errors) For inferior codegen in RV32 system, we should try another reasonable approach to fix it. Remove those TARGET_64BIT and fix ICE. gcc/ChangeLog: * config/riscv/riscv-vector-switch.def (VLS_ENTRY): Remove TARGET_64BIT gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test. * gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64d-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64f-1.c: Ditto. * gcc.target/riscv/rvv/autovec/zve64x-1.c: Ditto. --- gcc/config/riscv/riscv-vector-switch.def | 8 ++++---- .../gcc.target/riscv/rvv/autovec/partial/slp-9.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c | 2 +- .../gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c | 2 +- 17 files changed, 20 insertions(+), 20 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def index c035dc3558b..174e5a181c6 100644 --- a/gcc/config/riscv/riscv-vector-switch.def +++ b/gcc/config/riscv/riscv-vector-switch.def @@ -309,7 +309,7 @@ VLS_ENTRY (V4096BI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096) VLS_ENTRY (V1QI, TARGET_VECTOR_VLS) VLS_ENTRY (V2QI, TARGET_VECTOR_VLS) VLS_ENTRY (V4QI, TARGET_VECTOR_VLS) -VLS_ENTRY (V8QI, TARGET_VECTOR_VLS && TARGET_64BIT) +VLS_ENTRY (V8QI, TARGET_VECTOR_VLS) VLS_ENTRY (V16QI, TARGET_VECTOR_VLS) VLS_ENTRY (V32QI, TARGET_VECTOR_VLS) VLS_ENTRY (V64QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64) @@ -321,7 +321,7 @@ VLS_ENTRY (V2048QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048) VLS_ENTRY (V4096QI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096) VLS_ENTRY (V1HI, TARGET_VECTOR_VLS) VLS_ENTRY (V2HI, TARGET_VECTOR_VLS) -VLS_ENTRY (V4HI, TARGET_VECTOR_VLS && TARGET_64BIT) +VLS_ENTRY (V4HI, TARGET_VECTOR_VLS) VLS_ENTRY (V8HI, TARGET_VECTOR_VLS) VLS_ENTRY (V16HI, TARGET_VECTOR_VLS) VLS_ENTRY (V32HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64) @@ -332,7 +332,7 @@ VLS_ENTRY (V512HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024) VLS_ENTRY (V1024HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048) VLS_ENTRY (V2048HI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096) VLS_ENTRY (V1SI, TARGET_VECTOR_VLS) -VLS_ENTRY (V2SI, TARGET_VECTOR_VLS && TARGET_64BIT) +VLS_ENTRY (V2SI, TARGET_VECTOR_VLS) VLS_ENTRY (V4SI, TARGET_VECTOR_VLS) VLS_ENTRY (V8SI, TARGET_VECTOR_VLS) VLS_ENTRY (V16SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64) @@ -342,7 +342,7 @@ VLS_ENTRY (V128SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512) VLS_ENTRY (V256SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024) VLS_ENTRY (V512SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048) VLS_ENTRY (V1024SI, TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096) -VLS_ENTRY (V1DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_64BIT) +VLS_ENTRY (V1DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64) VLS_ENTRY (V2DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64) VLS_ENTRY (V4DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64) VLS_ENTRY (V8DI, TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c index 59b07e265e8..5fba27c7a35 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-march=rv64gcv -mabi=lp64d --param riscv-autovec-preference=scalable -fno-vect-cost-model -fdump-tree-optimized-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c index 54a36ae72d2..867b4e85783 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl1024b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c index 345e2f963d5..1a4362beb3b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c index 754aee23e91..d22eb15dd21 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl2048b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c index 52a2c2b42b1..54d82a88650 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl256b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c index 7a911d154dd..6119a10c145 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl4096b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c index 8d26abbe130..fd85203c4bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl512b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c index 15c481624ea..74825c476a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl1024b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c index 1394f08f2b9..c477a96c37d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c index 46be1f4da5b..8096c28939d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl2048b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c index 90e30843be1..9a133d11f46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl256b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c index 02ac73bcb05..00303499b89 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl4096b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c index 50cbfe13175..8809a400e18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl512b-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c index c5e89996fa4..94d88cc5312 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 6 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c index 6c2a002de9c..87f3b2f709c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 5 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c index 8fbfa8a8b68..64fbe454d33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c @@ -3,4 +3,4 @@ #include "template-1.h" -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */ -- 2.36.3