[PATCH 0/5] RISC-V: Add Types to Untyped Instructions

[Edwin Lu <ewlu@rivosinc.com>]

This series adds types to the remaining untyped instructions.

Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/

Also enables assert which checks to make sure every instruction has a type

All patches were tested with rv32/rv64 linux/newlib multilib
Additional extensions tested:
gcv
gc_zba_zbb_zbc_zbs

Edwin Lu (5):
  RISC-V: Update Types for Vector Instructions
  RISC-V: Add Types for Un-Typed zc Instructions
  RISC-V: Add Types to Un-Typed Zicond Instructions
  RISC-V: Add Types to Un-Typed Zicond Instructions
  RISC-V: Remove Assert Protecting Types

 gcc/config/riscv/autovec-opt.md |  42 ++++++++-----
 gcc/config/riscv/autovec.md     |  28 ++++++---
 gcc/config/riscv/riscv.cc       |   2 -
 gcc/config/riscv/riscv.md       |   9 ++-
 gcc/config/riscv/zc.md          | 102 ++++++++++++++++----------------
 gcc/config/riscv/zicond.md      |   8 +--
 6 files changed, 110 insertions(+), 81 deletions(-)

-- 
2.34.1