* [PATCH v3] RISC-V:Optimize the MASK opt generation
@ 2023-09-06 2:02 Feng Wang
2023-09-06 3:42 ` Kito Cheng
2023-09-07 0:48 ` Tsukasa OI
0 siblings, 2 replies; 7+ messages in thread
From: Feng Wang @ 2023-09-06 2:02 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, gaofei, xuli1, Feng Wang
This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
generation" and add the new explanation in the options.texi.
Please check the detail info on the
"https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html"
gcc/ChangeLog:
* config/riscv/riscv-opts.h (MASK_ZICSR):
(MASK_ZIFENCEI): Delete;
(MASK_ZIHINTNTL): Ditto;
(MASK_ZIHINTPAUSE): Ditto;
(TARGET_ZICSR): Ditto;
(TARGET_ZIFENCEI): Ditto;
(TARGET_ZIHINTNTL): Ditto;
(TARGET_ZIHINTPAUSE):Ditto;
(MASK_ZAWRS): Ditto;
(TARGET_ZAWRS): Ditto;
(MASK_ZBA): Ditto;
(MASK_ZBB): Ditto;
(MASK_ZBC): Ditto;
(MASK_ZBS): Ditto;
(TARGET_ZBA): Ditto;
(TARGET_ZBB): Ditto;
(TARGET_ZBC): Ditto;
(TARGET_ZBS): Ditto;
(MASK_ZFINX): Ditto;
(MASK_ZDINX): Ditto;
(MASK_ZHINX): Ditto;
(MASK_ZHINXMIN): Ditto;
(TARGET_ZFINX): Ditto;
(TARGET_ZDINX): Ditto;
(TARGET_ZHINX): Ditto;
(TARGET_ZHINXMIN): Ditto;
(MASK_ZBKB): Ditto;
(MASK_ZBKC): Ditto;
(MASK_ZBKX): Ditto;
(MASK_ZKNE): Ditto;
(MASK_ZKND): Ditto;
(MASK_ZKNH): Ditto;
(MASK_ZKR): Ditto;
(MASK_ZKSED): Ditto;
(MASK_ZKSH): Ditto;
(MASK_ZKT): Ditto;
(TARGET_ZBKB): Ditto;
(TARGET_ZBKC): Ditto;
(TARGET_ZBKX): Ditto;
(TARGET_ZKNE): Ditto;
(TARGET_ZKND): Ditto;
(TARGET_ZKNH): Ditto;
(TARGET_ZKR): Ditto;
(TARGET_ZKSED): Ditto;
(TARGET_ZKSH): Ditto;
(TARGET_ZKT): Ditto;
(MASK_ZTSO): Ditto;
(TARGET_ZTSO): Ditto;
(MASK_VECTOR_ELEN_32): Ditto;
(MASK_VECTOR_ELEN_64): Ditto;
(MASK_VECTOR_ELEN_FP_32):Ditto;
(MASK_VECTOR_ELEN_FP_64):Ditto;
(MASK_VECTOR_ELEN_FP_16):Ditto;
(TARGET_VECTOR_ELEN_32): Ditto;
(TARGET_VECTOR_ELEN_64): Ditto;
(TARGET_VECTOR_ELEN_FP_32):Ditto;
(TARGET_VECTOR_ELEN_FP_64):Ditto;
(TARGET_VECTOR_ELEN_FP_16):Ditto;
(MASK_ZVBB): Ditto;
(MASK_ZVBC): Ditto;
(TARGET_ZVBB): Ditto;
(TARGET_ZVBC): Ditto;
(MASK_ZVKG): Ditto;
(MASK_ZVKNED): Ditto;
(MASK_ZVKNHA): Ditto;
(MASK_ZVKNHB): Ditto;
(MASK_ZVKSED): Ditto;
(MASK_ZVKSH): Ditto;
(MASK_ZVKN): Ditto;
(MASK_ZVKNC): Ditto;
(MASK_ZVKNG): Ditto;
(MASK_ZVKS): Ditto;
(MASK_ZVKSC): Ditto;
(MASK_ZVKSG): Ditto;
(MASK_ZVKT): Ditto;
(TARGET_ZVKG): Ditto;
(TARGET_ZVKNED): Ditto;
(TARGET_ZVKNHA): Ditto;
(TARGET_ZVKNHB): Ditto;
(TARGET_ZVKSED): Ditto;
(TARGET_ZVKSH): Ditto;
(TARGET_ZVKN): Ditto;
(TARGET_ZVKNC): Ditto;
(TARGET_ZVKNG): Ditto;
(TARGET_ZVKS): Ditto;
(TARGET_ZVKSC): Ditto;
(TARGET_ZVKSG): Ditto;
(TARGET_ZVKT): Ditto;
(MASK_ZVL32B): Ditto;
(MASK_ZVL64B): Ditto;
(MASK_ZVL128B): Ditto;
(MASK_ZVL256B): Ditto;
(MASK_ZVL512B): Ditto;
(MASK_ZVL1024B): Ditto;
(MASK_ZVL2048B): Ditto;
(MASK_ZVL4096B): Ditto;
(MASK_ZVL8192B): Ditto;
(MASK_ZVL16384B): Ditto;
(MASK_ZVL32768B): Ditto;
(MASK_ZVL65536B): Ditto;
(TARGET_ZVL32B): Ditto;
(TARGET_ZVL64B): Ditto;
(TARGET_ZVL128B): Ditto;
(TARGET_ZVL256B): Ditto;
(TARGET_ZVL512B): Ditto;
(TARGET_ZVL1024B): Ditto;
(TARGET_ZVL2048B): Ditto;
(TARGET_ZVL4096B): Ditto;
(TARGET_ZVL8192B): Ditto;
(TARGET_ZVL16384B): Ditto;
(TARGET_ZVL32768B): Ditto;
(TARGET_ZVL65536B): Ditto;
(MASK_ZICBOZ): Ditto;
(MASK_ZICBOM): Ditto;
(MASK_ZICBOP): Ditto;
(TARGET_ZICBOZ): Ditto;
(TARGET_ZICBOM): Ditto;
(TARGET_ZICBOP): Ditto;
(MASK_ZICOND): Ditto;
(TARGET_ZICOND): Ditto;
(MASK_ZFA): Ditto;
(TARGET_ZFA): Ditto;
(MASK_ZFHMIN): Ditto;
(MASK_ZFH): Ditto;
(MASK_ZVFHMIN): Ditto;
(MASK_ZVFH): Ditto;
(TARGET_ZFHMIN): Ditto;
(TARGET_ZFH): Ditto;
(TARGET_ZVFHMIN): Ditto;
(TARGET_ZVFH): Ditto;
(MASK_ZMMUL): Ditto;
(TARGET_ZMMUL): Ditto;
(MASK_ZCA): Ditto;
(MASK_ZCB): Ditto;
(MASK_ZCE): Ditto;
(MASK_ZCF): Ditto;
(MASK_ZCD): Ditto;
(MASK_ZCMP): Ditto;
(MASK_ZCMT): Ditto;
(TARGET_ZCA): Ditto;
(TARGET_ZCB): Ditto;
(TARGET_ZCE): Ditto;
(TARGET_ZCF): Ditto;
(TARGET_ZCD): Ditto;
(TARGET_ZCMP): Ditto;
(TARGET_ZCMT): Ditto;
(MASK_SVINVAL): Ditto;
(MASK_SVNAPOT): Ditto;
(TARGET_SVINVAL): Ditto;
(TARGET_SVNAPOT): Ditto;
(MASK_XTHEADBA): Ditto;
(MASK_XTHEADBB): Ditto;
(MASK_XTHEADBS): Ditto;
(MASK_XTHEADCMO): Ditto;
(MASK_XTHEADCONDMOV): Ditto;
(MASK_XTHEADFMEMIDX): Ditto;
(MASK_XTHEADFMV): Ditto;
(MASK_XTHEADINT): Ditto;
(MASK_XTHEADMAC): Ditto;
(MASK_XTHEADMEMIDX): Ditto;
(MASK_XTHEADMEMPAIR): Ditto;
(MASK_XTHEADSYNC): Ditto;
(TARGET_XTHEADBA): Ditto;
(TARGET_XTHEADBB): Ditto;
(TARGET_XTHEADBS): Ditto;
(TARGET_XTHEADCMO): Ditto;
(TARGET_XTHEADCONDMOV):Ditto;
(TARGET_XTHEADFMEMIDX):Ditto;
(TARGET_XTHEADFMV): Ditto;
(TARGET_XTHEADINT): Ditto;
(TARGET_XTHEADMAC): Ditto;
(TARGET_XTHEADMEMIDX): Ditto;
(TARGET_XTHEADMEMPAIR):Ditto;
(TARGET_XTHEADSYNC): Ditto;
* config/riscv/riscv.opt: Add new Mask defination.
* doc/options.texi: Add new explanation for the usage.
* opt-functions.awk: Add new function to find the index
of target variable from extra_target_vars.
* opt-read.awk: Add new function to store the Mask flags.
* opth-gen.awk: Add new function to output the defination of
Mask Macro and Target Macro.
---
gcc/config/riscv/riscv-opts.h | 212 ----------------------------------
gcc/config/riscv/riscv.opt | 174 ++++++++++++++++++++++++++++
gcc/doc/options.texi | 6 +
gcc/opt-functions.awk | 11 ++
gcc/opt-read.awk | 16 ++-
gcc/opth-gen.awk | 22 ++++
6 files changed, 228 insertions(+), 213 deletions(-)
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 5ed69abd214..07aa3cc83db 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -99,192 +99,6 @@ enum riscv_entity
MAX_RISCV_ENTITIES
};
-#define MASK_ZICSR (1 << 0)
-#define MASK_ZIFENCEI (1 << 1)
-#define MASK_ZIHINTNTL (1 << 2)
-#define MASK_ZIHINTPAUSE (1 << 3)
-
-#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
-#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
-#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
-#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0)
-
-#define MASK_ZAWRS (1 << 0)
-#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
-
-#define MASK_ZBA (1 << 0)
-#define MASK_ZBB (1 << 1)
-#define MASK_ZBC (1 << 2)
-#define MASK_ZBS (1 << 3)
-
-#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
-#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
-#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
-#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
-
-#define MASK_ZFINX (1 << 0)
-#define MASK_ZDINX (1 << 1)
-#define MASK_ZHINX (1 << 2)
-#define MASK_ZHINXMIN (1 << 3)
-
-#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
-#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
-#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
-#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
-
-#define MASK_ZBKB (1 << 0)
-#define MASK_ZBKC (1 << 1)
-#define MASK_ZBKX (1 << 2)
-#define MASK_ZKNE (1 << 3)
-#define MASK_ZKND (1 << 4)
-#define MASK_ZKNH (1 << 5)
-#define MASK_ZKR (1 << 6)
-#define MASK_ZKSED (1 << 7)
-#define MASK_ZKSH (1 << 8)
-#define MASK_ZKT (1 << 9)
-
-#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
-#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
-#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
-#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
-#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
-#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
-#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
-#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
-#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
-#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
-
-#define MASK_ZTSO (1 << 0)
-
-#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0)
-
-#define MASK_VECTOR_ELEN_32 (1 << 0)
-#define MASK_VECTOR_ELEN_64 (1 << 1)
-#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
-#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
-/* Align the bit index to riscv-vector-builtins.h. */
-#define MASK_VECTOR_ELEN_FP_16 (1 << 6)
-
-#define TARGET_VECTOR_ELEN_32 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
-#define TARGET_VECTOR_ELEN_64 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
-#define TARGET_VECTOR_ELEN_FP_32 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
-#define TARGET_VECTOR_ELEN_FP_64 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
-#define TARGET_VECTOR_ELEN_FP_16 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_16) != 0)
-
-#define MASK_ZVBB (1 << 0)
-#define MASK_ZVBC (1 << 1)
-
-#define TARGET_ZVBB ((riscv_zvb_subext & MASK_ZVBB) != 0)
-#define TARGET_ZVBC ((riscv_zvb_subext & MASK_ZVBC) != 0)
-
-#define MASK_ZVKG (1 << 0)
-#define MASK_ZVKNED (1 << 1)
-#define MASK_ZVKNHA (1 << 2)
-#define MASK_ZVKNHB (1 << 3)
-#define MASK_ZVKSED (1 << 4)
-#define MASK_ZVKSH (1 << 5)
-#define MASK_ZVKN (1 << 6)
-#define MASK_ZVKNC (1 << 7)
-#define MASK_ZVKNG (1 << 8)
-#define MASK_ZVKS (1 << 9)
-#define MASK_ZVKSC (1 << 10)
-#define MASK_ZVKSG (1 << 11)
-#define MASK_ZVKT (1 << 12)
-
-#define TARGET_ZVKG ((riscv_zvk_subext & MASK_ZVKG) != 0)
-#define TARGET_ZVKNED ((riscv_zvk_subext & MASK_ZVKNED) != 0)
-#define TARGET_ZVKNHA ((riscv_zvk_subext & MASK_ZVKNHA) != 0)
-#define TARGET_ZVKNHB ((riscv_zvk_subext & MASK_ZVKNHB) != 0)
-#define TARGET_ZVKSED ((riscv_zvk_subext & MASK_ZVKSED) != 0)
-#define TARGET_ZVKSH ((riscv_zvk_subext & MASK_ZVKSH) != 0)
-#define TARGET_ZVKN ((riscv_zvk_subext & MASK_ZVKN) != 0)
-#define TARGET_ZVKNC ((riscv_zvk_subext & MASK_ZVKNC) != 0)
-#define TARGET_ZVKNG ((riscv_zvk_subext & MASK_ZVKNG) != 0)
-#define TARGET_ZVKS ((riscv_zvk_subext & MASK_ZVKS) != 0)
-#define TARGET_ZVKSC ((riscv_zvk_subext & MASK_ZVKSC) != 0)
-#define TARGET_ZVKSG ((riscv_zvk_subext & MASK_ZVKSG) != 0)
-#define TARGET_ZVKT ((riscv_zvk_subext & MASK_ZVKT) != 0)
-
-#define MASK_ZVL32B (1 << 0)
-#define MASK_ZVL64B (1 << 1)
-#define MASK_ZVL128B (1 << 2)
-#define MASK_ZVL256B (1 << 3)
-#define MASK_ZVL512B (1 << 4)
-#define MASK_ZVL1024B (1 << 5)
-#define MASK_ZVL2048B (1 << 6)
-#define MASK_ZVL4096B (1 << 7)
-#define MASK_ZVL8192B (1 << 8)
-#define MASK_ZVL16384B (1 << 9)
-#define MASK_ZVL32768B (1 << 10)
-#define MASK_ZVL65536B (1 << 11)
-
-#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
-#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
-#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
-#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
-#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
-#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
-#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
-#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
-#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
-#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
-#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
-#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
-
-#define MASK_ZICBOZ (1 << 0)
-#define MASK_ZICBOM (1 << 1)
-#define MASK_ZICBOP (1 << 2)
-
-#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
-#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
-#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
-
-#define MASK_ZICOND (1 << 2)
-#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0)
-
-#define MASK_ZFA (1 << 0)
-#define TARGET_ZFA ((riscv_zfa_subext & MASK_ZFA) != 0)
-
-#define MASK_ZFHMIN (1 << 0)
-#define MASK_ZFH (1 << 1)
-#define MASK_ZVFHMIN (1 << 2)
-#define MASK_ZVFH (1 << 3)
-
-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
-#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
-#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
-#define TARGET_ZVFH ((riscv_zf_subext & MASK_ZVFH) != 0)
-
-#define MASK_ZMMUL (1 << 0)
-#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
-
-#define MASK_ZCA (1 << 0)
-#define MASK_ZCB (1 << 1)
-#define MASK_ZCE (1 << 2)
-#define MASK_ZCF (1 << 3)
-#define MASK_ZCD (1 << 4)
-#define MASK_ZCMP (1 << 5)
-#define MASK_ZCMT (1 << 6)
-
-#define TARGET_ZCA ((riscv_zc_subext & MASK_ZCA) != 0)
-#define TARGET_ZCB ((riscv_zc_subext & MASK_ZCB) != 0)
-#define TARGET_ZCE ((riscv_zc_subext & MASK_ZCE) != 0)
-#define TARGET_ZCF ((riscv_zc_subext & MASK_ZCF) != 0)
-#define TARGET_ZCD ((riscv_zc_subext & MASK_ZCD) != 0)
-#define TARGET_ZCMP ((riscv_zc_subext & MASK_ZCMP) != 0)
-#define TARGET_ZCMT ((riscv_zc_subext & MASK_ZCMT) != 0)
-
-#define MASK_SVINVAL (1 << 0)
-#define MASK_SVNAPOT (1 << 1)
-
-#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
-#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
-
/* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
popcount to caclulate the minimal VLEN. */
@@ -293,32 +107,6 @@ enum riscv_entity
? 0 \
: 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
-#define MASK_XTHEADBA (1 << 0)
-#define MASK_XTHEADBB (1 << 1)
-#define MASK_XTHEADBS (1 << 2)
-#define MASK_XTHEADCMO (1 << 3)
-#define MASK_XTHEADCONDMOV (1 << 4)
-#define MASK_XTHEADFMEMIDX (1 << 5)
-#define MASK_XTHEADFMV (1 << 6)
-#define MASK_XTHEADINT (1 << 7)
-#define MASK_XTHEADMAC (1 << 8)
-#define MASK_XTHEADMEMIDX (1 << 9)
-#define MASK_XTHEADMEMPAIR (1 << 10)
-#define MASK_XTHEADSYNC (1 << 11)
-
-#define TARGET_XTHEADBA ((riscv_xthead_subext & MASK_XTHEADBA) != 0)
-#define TARGET_XTHEADBB ((riscv_xthead_subext & MASK_XTHEADBB) != 0)
-#define TARGET_XTHEADBS ((riscv_xthead_subext & MASK_XTHEADBS) != 0)
-#define TARGET_XTHEADCMO ((riscv_xthead_subext & MASK_XTHEADCMO) != 0)
-#define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
-#define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
-#define TARGET_XTHEADFMV ((riscv_xthead_subext & MASK_XTHEADFMV) != 0)
-#define TARGET_XTHEADINT ((riscv_xthead_subext & MASK_XTHEADINT) != 0)
-#define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
-#define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
-#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
-#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
-
/* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
is the highest priority choice and should not conflict with VLS modes. */
#define TARGET_VECTOR_VLS \
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index d2407c3c502..4570c4b76c2 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -209,54 +209,228 @@ long riscv_stack_protector_guard_offset = 0
TargetVariable
int riscv_zi_subext
+Mask(ZICSR) in TargetVariable(riscv_zi_subext)
+
+Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)
+
+Mask(ZIHINTNTL) in TargetVariable(riscv_zi_subext)
+
+Mask(ZIHINTPAUSE) in TargetVariable(riscv_zi_subext)
+
+Mask(ZICOND) in TargetVariable(riscv_zi_subext)
+
TargetVariable
int riscv_za_subext
+Mask(ZAWRS) in TargetVariable(riscv_za_subext)
+
TargetVariable
int riscv_zb_subext
+Mask(ZBA) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBB) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBC) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBS) in TargetVariable(riscv_zb_subext)
+
TargetVariable
int riscv_zinx_subext
+Mask(ZFINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZDINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZHINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZHINXMIN) in TargetVariable(riscv_zinx_subext)
+
TargetVariable
int riscv_zk_subext
+Mask(ZBKB) in TargetVariable(riscv_zk_subext)
+
+Mask(ZBKC) in TargetVariable(riscv_zk_subext)
+
+Mask(ZBKX) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKNE) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKND) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKNH) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKR) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKSED) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKSH) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKT) in TargetVariable(riscv_zk_subext)
+
TargetVariable
int riscv_vector_elen_flags
+Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_64) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_32) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_64) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_16) in TargetVariable(riscv_vector_elen_flags)
+
TargetVariable
int riscv_zvl_flags
+Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL128B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL256B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL512B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL1024B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL2048B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL4096B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL8192B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL16384B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL32768B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL65536B) in TargetVariable(riscv_zvl_flags)
+
TargetVariable
int riscv_zvb_subext
+Mask(ZVBB) in TargetVariable(riscv_zvb_subext)
+
+Mask(ZVBC) in TargetVariable(riscv_zvb_subext)
+
TargetVariable
int riscv_zvk_subext
+Mask(ZVKG) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKNED) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKNHA) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKNHB) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKSED) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKSH) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKN) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKNC) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKNG) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKS) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKSC) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKSG) in TargetVariable(riscv_zvk_subext)
+
+Mask(ZVKT) in TargetVariable(riscv_zvk_subext)
+
TargetVariable
int riscv_zicmo_subext
+Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
+
TargetVariable
int riscv_zf_subext
+Mask(ZFHMIN) in TargetVariable(riscv_zf_subext)
+
+Mask(ZFH) in TargetVariable(riscv_zf_subext)
+
+Mask(ZVFHMIN) in TargetVariable(riscv_zf_subext)
+
+Mask(ZVFH) in TargetVariable(riscv_zf_subext)
+
TargetVariable
int riscv_zfa_subext
+Mask(ZFA) in TargetVariable(riscv_zfa_subext)
+
TargetVariable
int riscv_zm_subext
+Mask(ZMMUL) in TargetVariable(riscv_zm_subext)
+
TargetVariable
int riscv_zc_subext
+Mask(ZCA) in TargetVariable(riscv_zc_subext)
+
+Mask(ZCB) in TargetVariable(riscv_zc_subext)
+
+Mask(ZCE) in TargetVariable(riscv_zc_subext)
+
+Mask(ZCF) in TargetVariable(riscv_zc_subext)
+
+Mask(ZCD) in TargetVariable(riscv_zc_subext)
+
+Mask(ZCMP) in TargetVariable(riscv_zc_subext)
+
+Mask(ZCMT) in TargetVariable(riscv_zc_subext)
+
TargetVariable
int riscv_sv_subext
+Mask(SVINVAL) in TargetVariable(riscv_sv_subext)
+
+Mask(SVNAPOT) in TargetVariable(riscv_sv_subext)
+
TargetVariable
int riscv_ztso_subext
+Mask(ZTSO) in TargetVariable(riscv_ztso_subext)
+
TargetVariable
int riscv_xthead_subext
+Mask(XTHEADBA) in TargetVariable(riscv_xthead_subext)
+
+Mask(XTHEADBB) in TargetVariable(riscv_xthead_subext)
+
+Mask(XTHEADBS) in TargetVariable(riscv_xthead_subext)
+
+Mask(XTHEADCMO) in TargetVariable(riscv_xthead_subext)
+
+Mask(XTHEADCONDMOV) in TargetVariable(riscv_xthead_subext)
+
+Mask(XTHEADFMEMIDX) in TargetVariable(riscv_xthead_subext)
+
+Mask(XTHEADFMV) in TargetVariable(riscv_xthead_subext)
+
+Mask(XTHEADINT) in TargetVariable(riscv_xthead_subext)
+
+Mask(XTHEADMAC) in TargetVariable(riscv_xthead_subext)
+
+Mask(XTHEADMEMIDX) in TargetVariable(riscv_xthead_subext)
+
+Mask(XTHEADMEMPAIR) in TargetVariable(riscv_xthead_subext)
+
+Mask(XTHEADSYNC) in TargetVariable(riscv_xthead_subext)
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
index f50063c9787..24663d8233e 100644
--- a/gcc/doc/options.texi
+++ b/gcc/doc/options.texi
@@ -409,6 +409,12 @@ the value 1 when the option is active and 0 otherwise. If you use @code{Var}
to attach the option to a different variable, the bitmask macro with be
called @code{OPTION_MASK_@var{name}}.
+@item Mask(@var{name}) in TargetVariable(@var{other_target_flags})
+This method can be used to associate the option with a bit in @samp{other_target_flags}
+which has been defined,when the option number exceeds the bits of @code{target_flags}.
+The macro @code{MASK_@var{name}} and The @code{TARGET_@var{name}}
+will aslo be generated automatically as described above .
+
@item InverseMask(@var{othername})
@itemx InverseMask(@var{othername}, @var{thisname})
The option is the inverse of another option that has the
diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
index 36de4639318..cbfcf7dabcf 100644
--- a/gcc/opt-functions.awk
+++ b/gcc/opt-functions.awk
@@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option, uinteger_used)
else
return "-1, -1"
}
+
+# Find the index of target variable from extra_target_vars
+function find_index(var, var_arry, n_var_arry)
+{
+ for (var_index = 0; var_index < n_var_arry; var_index++)
+ {
+ if (var_arry[var_index] == var)
+ break
+ }
+ return var_index
+}
diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
index fc4e3d77910..0ff2e806373 100644
--- a/gcc/opt-read.awk
+++ b/gcc/opt-read.awk
@@ -22,6 +22,7 @@ BEGIN {
n_opts = 0
n_langs = 0
n_target_save = 0
+ n_target_vars = 0
n_extra_vars = 0
n_extra_target_vars = 0
n_extra_masks = 0
@@ -121,7 +122,20 @@ BEGIN {
n_opts++;
}
else {
- extra_masks[n_extra_masks++] = name
+ if($0 ~ "in")
+ {
+ target_var = opt_args("TargetVariable", $1)
+ var_index = find_index(target_var, target_vars, n_target_vars)
+ if (var_index == n_target_vars)
+ {
+ target_vars[n_target_vars++] = target_var
+ }
+ other_masks[var_index][n_other_mask[var_index]++] = name
+ }
+ else
+ {
+ extra_masks[n_extra_masks++] = name
+ }
}
}
}
diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
index 71404f9eff6..70ca3d37719 100644
--- a/gcc/opth-gen.awk
+++ b/gcc/opth-gen.awk
@@ -406,6 +406,18 @@ for (i = 0; i < n_extra_masks; i++) {
print "#define MASK_" extra_masks[i] " (1U << " masknum[""]++ ")"
}
+for (i = 0; i < n_target_vars; i++)
+{
+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
+ continue
+ for (j = 0; j < n_other_mask[i]; j++)
+ {
+ print "#define MASK_" other_masks[i][j] " (1U << " other_masknum[i][""]++ ")"
+ }
+ if (other_masknum[i][""] > 32)
+ print "#error too many target masks for" extra_target_vars[i]
+}
+
for (var in masknum) {
if (var != "" && host_wide_int[var] == "yes") {
print "#if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] " > HOST_BITS_PER_WIDE_INT"
@@ -419,6 +431,16 @@ for (var in masknum) {
print "#error too many masks for " var
}
}
+for (i = 0; i < n_target_vars; i++)
+{
+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
+ continue
+ for (j = 0; j < n_other_mask[i]; j++)
+ {
+ print "#define TARGET_" other_masks[i][j] \
+ " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 0)"
+ }
+}
print ""
for (i = 0; i < n_opts; i++) {
--
2.17.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] RISC-V:Optimize the MASK opt generation
2023-09-06 2:02 [PATCH v3] RISC-V:Optimize the MASK opt generation Feng Wang
@ 2023-09-06 3:42 ` Kito Cheng
2023-09-06 6:38 ` Feng Wang
2023-09-07 0:48 ` Tsukasa OI
1 sibling, 1 reply; 7+ messages in thread
From: Kito Cheng @ 2023-09-06 3:42 UTC (permalink / raw)
To: Feng Wang; +Cc: gcc-patches
Reading the manual again, it seems I missed something in the manual
before, the MASK syntax already says we can specify Var to select the
variable other than target_flags, but I tried that not work when we
only declare Mask with Var (e.g. "Mask(VECTOR_ELEN_32)
Var(riscv_vector_elen_flags)" still using target_flags)
So maybe we should just fix that instead of extending the syntax?
e.g.
Mask(VECTOR_ELEN_32) Var(riscv_vector_elen_flags)
rather than
Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
On Wed, Sep 6, 2023 at 10:03 AM Feng Wang <wangfeng@eswincomputing.com> wrote:
>
> This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
> generation" and add the new explanation in the options.texi.
> Please check the detail info on the
> "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html"
> gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h (MASK_ZICSR):
> (MASK_ZIFENCEI): Delete;
> (MASK_ZIHINTNTL): Ditto;
> (MASK_ZIHINTPAUSE): Ditto;
> (TARGET_ZICSR): Ditto;
> (TARGET_ZIFENCEI): Ditto;
> (TARGET_ZIHINTNTL): Ditto;
> (TARGET_ZIHINTPAUSE):Ditto;
> (MASK_ZAWRS): Ditto;
> (TARGET_ZAWRS): Ditto;
> (MASK_ZBA): Ditto;
> (MASK_ZBB): Ditto;
> (MASK_ZBC): Ditto;
> (MASK_ZBS): Ditto;
> (TARGET_ZBA): Ditto;
> (TARGET_ZBB): Ditto;
> (TARGET_ZBC): Ditto;
> (TARGET_ZBS): Ditto;
> (MASK_ZFINX): Ditto;
> (MASK_ZDINX): Ditto;
> (MASK_ZHINX): Ditto;
> (MASK_ZHINXMIN): Ditto;
> (TARGET_ZFINX): Ditto;
> (TARGET_ZDINX): Ditto;
> (TARGET_ZHINX): Ditto;
> (TARGET_ZHINXMIN): Ditto;
> (MASK_ZBKB): Ditto;
> (MASK_ZBKC): Ditto;
> (MASK_ZBKX): Ditto;
> (MASK_ZKNE): Ditto;
> (MASK_ZKND): Ditto;
> (MASK_ZKNH): Ditto;
> (MASK_ZKR): Ditto;
> (MASK_ZKSED): Ditto;
> (MASK_ZKSH): Ditto;
> (MASK_ZKT): Ditto;
> (TARGET_ZBKB): Ditto;
> (TARGET_ZBKC): Ditto;
> (TARGET_ZBKX): Ditto;
> (TARGET_ZKNE): Ditto;
> (TARGET_ZKND): Ditto;
> (TARGET_ZKNH): Ditto;
> (TARGET_ZKR): Ditto;
> (TARGET_ZKSED): Ditto;
> (TARGET_ZKSH): Ditto;
> (TARGET_ZKT): Ditto;
> (MASK_ZTSO): Ditto;
> (TARGET_ZTSO): Ditto;
> (MASK_VECTOR_ELEN_32): Ditto;
> (MASK_VECTOR_ELEN_64): Ditto;
> (MASK_VECTOR_ELEN_FP_32):Ditto;
> (MASK_VECTOR_ELEN_FP_64):Ditto;
> (MASK_VECTOR_ELEN_FP_16):Ditto;
> (TARGET_VECTOR_ELEN_32): Ditto;
> (TARGET_VECTOR_ELEN_64): Ditto;
> (TARGET_VECTOR_ELEN_FP_32):Ditto;
> (TARGET_VECTOR_ELEN_FP_64):Ditto;
> (TARGET_VECTOR_ELEN_FP_16):Ditto;
> (MASK_ZVBB): Ditto;
> (MASK_ZVBC): Ditto;
> (TARGET_ZVBB): Ditto;
> (TARGET_ZVBC): Ditto;
> (MASK_ZVKG): Ditto;
> (MASK_ZVKNED): Ditto;
> (MASK_ZVKNHA): Ditto;
> (MASK_ZVKNHB): Ditto;
> (MASK_ZVKSED): Ditto;
> (MASK_ZVKSH): Ditto;
> (MASK_ZVKN): Ditto;
> (MASK_ZVKNC): Ditto;
> (MASK_ZVKNG): Ditto;
> (MASK_ZVKS): Ditto;
> (MASK_ZVKSC): Ditto;
> (MASK_ZVKSG): Ditto;
> (MASK_ZVKT): Ditto;
> (TARGET_ZVKG): Ditto;
> (TARGET_ZVKNED): Ditto;
> (TARGET_ZVKNHA): Ditto;
> (TARGET_ZVKNHB): Ditto;
> (TARGET_ZVKSED): Ditto;
> (TARGET_ZVKSH): Ditto;
> (TARGET_ZVKN): Ditto;
> (TARGET_ZVKNC): Ditto;
> (TARGET_ZVKNG): Ditto;
> (TARGET_ZVKS): Ditto;
> (TARGET_ZVKSC): Ditto;
> (TARGET_ZVKSG): Ditto;
> (TARGET_ZVKT): Ditto;
> (MASK_ZVL32B): Ditto;
> (MASK_ZVL64B): Ditto;
> (MASK_ZVL128B): Ditto;
> (MASK_ZVL256B): Ditto;
> (MASK_ZVL512B): Ditto;
> (MASK_ZVL1024B): Ditto;
> (MASK_ZVL2048B): Ditto;
> (MASK_ZVL4096B): Ditto;
> (MASK_ZVL8192B): Ditto;
> (MASK_ZVL16384B): Ditto;
> (MASK_ZVL32768B): Ditto;
> (MASK_ZVL65536B): Ditto;
> (TARGET_ZVL32B): Ditto;
> (TARGET_ZVL64B): Ditto;
> (TARGET_ZVL128B): Ditto;
> (TARGET_ZVL256B): Ditto;
> (TARGET_ZVL512B): Ditto;
> (TARGET_ZVL1024B): Ditto;
> (TARGET_ZVL2048B): Ditto;
> (TARGET_ZVL4096B): Ditto;
> (TARGET_ZVL8192B): Ditto;
> (TARGET_ZVL16384B): Ditto;
> (TARGET_ZVL32768B): Ditto;
> (TARGET_ZVL65536B): Ditto;
> (MASK_ZICBOZ): Ditto;
> (MASK_ZICBOM): Ditto;
> (MASK_ZICBOP): Ditto;
> (TARGET_ZICBOZ): Ditto;
> (TARGET_ZICBOM): Ditto;
> (TARGET_ZICBOP): Ditto;
> (MASK_ZICOND): Ditto;
> (TARGET_ZICOND): Ditto;
> (MASK_ZFA): Ditto;
> (TARGET_ZFA): Ditto;
> (MASK_ZFHMIN): Ditto;
> (MASK_ZFH): Ditto;
> (MASK_ZVFHMIN): Ditto;
> (MASK_ZVFH): Ditto;
> (TARGET_ZFHMIN): Ditto;
> (TARGET_ZFH): Ditto;
> (TARGET_ZVFHMIN): Ditto;
> (TARGET_ZVFH): Ditto;
> (MASK_ZMMUL): Ditto;
> (TARGET_ZMMUL): Ditto;
> (MASK_ZCA): Ditto;
> (MASK_ZCB): Ditto;
> (MASK_ZCE): Ditto;
> (MASK_ZCF): Ditto;
> (MASK_ZCD): Ditto;
> (MASK_ZCMP): Ditto;
> (MASK_ZCMT): Ditto;
> (TARGET_ZCA): Ditto;
> (TARGET_ZCB): Ditto;
> (TARGET_ZCE): Ditto;
> (TARGET_ZCF): Ditto;
> (TARGET_ZCD): Ditto;
> (TARGET_ZCMP): Ditto;
> (TARGET_ZCMT): Ditto;
> (MASK_SVINVAL): Ditto;
> (MASK_SVNAPOT): Ditto;
> (TARGET_SVINVAL): Ditto;
> (TARGET_SVNAPOT): Ditto;
> (MASK_XTHEADBA): Ditto;
> (MASK_XTHEADBB): Ditto;
> (MASK_XTHEADBS): Ditto;
> (MASK_XTHEADCMO): Ditto;
> (MASK_XTHEADCONDMOV): Ditto;
> (MASK_XTHEADFMEMIDX): Ditto;
> (MASK_XTHEADFMV): Ditto;
> (MASK_XTHEADINT): Ditto;
> (MASK_XTHEADMAC): Ditto;
> (MASK_XTHEADMEMIDX): Ditto;
> (MASK_XTHEADMEMPAIR): Ditto;
> (MASK_XTHEADSYNC): Ditto;
> (TARGET_XTHEADBA): Ditto;
> (TARGET_XTHEADBB): Ditto;
> (TARGET_XTHEADBS): Ditto;
> (TARGET_XTHEADCMO): Ditto;
> (TARGET_XTHEADCONDMOV):Ditto;
> (TARGET_XTHEADFMEMIDX):Ditto;
> (TARGET_XTHEADFMV): Ditto;
> (TARGET_XTHEADINT): Ditto;
> (TARGET_XTHEADMAC): Ditto;
> (TARGET_XTHEADMEMIDX): Ditto;
> (TARGET_XTHEADMEMPAIR):Ditto;
> (TARGET_XTHEADSYNC): Ditto;
> * config/riscv/riscv.opt: Add new Mask defination.
> * doc/options.texi: Add new explanation for the usage.
> * opt-functions.awk: Add new function to find the index
> of target variable from extra_target_vars.
> * opt-read.awk: Add new function to store the Mask flags.
> * opth-gen.awk: Add new function to output the defination of
> Mask Macro and Target Macro.
> ---
> gcc/config/riscv/riscv-opts.h | 212 ----------------------------------
> gcc/config/riscv/riscv.opt | 174 ++++++++++++++++++++++++++++
> gcc/doc/options.texi | 6 +
> gcc/opt-functions.awk | 11 ++
> gcc/opt-read.awk | 16 ++-
> gcc/opth-gen.awk | 22 ++++
> 6 files changed, 228 insertions(+), 213 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 5ed69abd214..07aa3cc83db 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -99,192 +99,6 @@ enum riscv_entity
> MAX_RISCV_ENTITIES
> };
>
> -#define MASK_ZICSR (1 << 0)
> -#define MASK_ZIFENCEI (1 << 1)
> -#define MASK_ZIHINTNTL (1 << 2)
> -#define MASK_ZIHINTPAUSE (1 << 3)
> -
> -#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
> -#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
> -#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
> -#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0)
> -
> -#define MASK_ZAWRS (1 << 0)
> -#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
> -
> -#define MASK_ZBA (1 << 0)
> -#define MASK_ZBB (1 << 1)
> -#define MASK_ZBC (1 << 2)
> -#define MASK_ZBS (1 << 3)
> -
> -#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
> -#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
> -#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
> -#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
> -
> -#define MASK_ZFINX (1 << 0)
> -#define MASK_ZDINX (1 << 1)
> -#define MASK_ZHINX (1 << 2)
> -#define MASK_ZHINXMIN (1 << 3)
> -
> -#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
> -#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
> -#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
> -#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
> -
> -#define MASK_ZBKB (1 << 0)
> -#define MASK_ZBKC (1 << 1)
> -#define MASK_ZBKX (1 << 2)
> -#define MASK_ZKNE (1 << 3)
> -#define MASK_ZKND (1 << 4)
> -#define MASK_ZKNH (1 << 5)
> -#define MASK_ZKR (1 << 6)
> -#define MASK_ZKSED (1 << 7)
> -#define MASK_ZKSH (1 << 8)
> -#define MASK_ZKT (1 << 9)
> -
> -#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
> -#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
> -#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
> -#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
> -#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
> -#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
> -#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
> -#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
> -#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
> -#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
> -
> -#define MASK_ZTSO (1 << 0)
> -
> -#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0)
> -
> -#define MASK_VECTOR_ELEN_32 (1 << 0)
> -#define MASK_VECTOR_ELEN_64 (1 << 1)
> -#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
> -#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
> -/* Align the bit index to riscv-vector-builtins.h. */
> -#define MASK_VECTOR_ELEN_FP_16 (1 << 6)
> -
> -#define TARGET_VECTOR_ELEN_32 \
> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
> -#define TARGET_VECTOR_ELEN_64 \
> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
> -#define TARGET_VECTOR_ELEN_FP_32 \
> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
> -#define TARGET_VECTOR_ELEN_FP_64 \
> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
> -#define TARGET_VECTOR_ELEN_FP_16 \
> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_16) != 0)
> -
> -#define MASK_ZVBB (1 << 0)
> -#define MASK_ZVBC (1 << 1)
> -
> -#define TARGET_ZVBB ((riscv_zvb_subext & MASK_ZVBB) != 0)
> -#define TARGET_ZVBC ((riscv_zvb_subext & MASK_ZVBC) != 0)
> -
> -#define MASK_ZVKG (1 << 0)
> -#define MASK_ZVKNED (1 << 1)
> -#define MASK_ZVKNHA (1 << 2)
> -#define MASK_ZVKNHB (1 << 3)
> -#define MASK_ZVKSED (1 << 4)
> -#define MASK_ZVKSH (1 << 5)
> -#define MASK_ZVKN (1 << 6)
> -#define MASK_ZVKNC (1 << 7)
> -#define MASK_ZVKNG (1 << 8)
> -#define MASK_ZVKS (1 << 9)
> -#define MASK_ZVKSC (1 << 10)
> -#define MASK_ZVKSG (1 << 11)
> -#define MASK_ZVKT (1 << 12)
> -
> -#define TARGET_ZVKG ((riscv_zvk_subext & MASK_ZVKG) != 0)
> -#define TARGET_ZVKNED ((riscv_zvk_subext & MASK_ZVKNED) != 0)
> -#define TARGET_ZVKNHA ((riscv_zvk_subext & MASK_ZVKNHA) != 0)
> -#define TARGET_ZVKNHB ((riscv_zvk_subext & MASK_ZVKNHB) != 0)
> -#define TARGET_ZVKSED ((riscv_zvk_subext & MASK_ZVKSED) != 0)
> -#define TARGET_ZVKSH ((riscv_zvk_subext & MASK_ZVKSH) != 0)
> -#define TARGET_ZVKN ((riscv_zvk_subext & MASK_ZVKN) != 0)
> -#define TARGET_ZVKNC ((riscv_zvk_subext & MASK_ZVKNC) != 0)
> -#define TARGET_ZVKNG ((riscv_zvk_subext & MASK_ZVKNG) != 0)
> -#define TARGET_ZVKS ((riscv_zvk_subext & MASK_ZVKS) != 0)
> -#define TARGET_ZVKSC ((riscv_zvk_subext & MASK_ZVKSC) != 0)
> -#define TARGET_ZVKSG ((riscv_zvk_subext & MASK_ZVKSG) != 0)
> -#define TARGET_ZVKT ((riscv_zvk_subext & MASK_ZVKT) != 0)
> -
> -#define MASK_ZVL32B (1 << 0)
> -#define MASK_ZVL64B (1 << 1)
> -#define MASK_ZVL128B (1 << 2)
> -#define MASK_ZVL256B (1 << 3)
> -#define MASK_ZVL512B (1 << 4)
> -#define MASK_ZVL1024B (1 << 5)
> -#define MASK_ZVL2048B (1 << 6)
> -#define MASK_ZVL4096B (1 << 7)
> -#define MASK_ZVL8192B (1 << 8)
> -#define MASK_ZVL16384B (1 << 9)
> -#define MASK_ZVL32768B (1 << 10)
> -#define MASK_ZVL65536B (1 << 11)
> -
> -#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
> -#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
> -#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
> -#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
> -#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
> -#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
> -#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
> -#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
> -#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
> -#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
> -#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
> -#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
> -
> -#define MASK_ZICBOZ (1 << 0)
> -#define MASK_ZICBOM (1 << 1)
> -#define MASK_ZICBOP (1 << 2)
> -
> -#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
> -#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
> -#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
> -
> -#define MASK_ZICOND (1 << 2)
> -#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0)
> -
> -#define MASK_ZFA (1 << 0)
> -#define TARGET_ZFA ((riscv_zfa_subext & MASK_ZFA) != 0)
> -
> -#define MASK_ZFHMIN (1 << 0)
> -#define MASK_ZFH (1 << 1)
> -#define MASK_ZVFHMIN (1 << 2)
> -#define MASK_ZVFH (1 << 3)
> -
> -#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> -#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
> -#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
> -#define TARGET_ZVFH ((riscv_zf_subext & MASK_ZVFH) != 0)
> -
> -#define MASK_ZMMUL (1 << 0)
> -#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
> -
> -#define MASK_ZCA (1 << 0)
> -#define MASK_ZCB (1 << 1)
> -#define MASK_ZCE (1 << 2)
> -#define MASK_ZCF (1 << 3)
> -#define MASK_ZCD (1 << 4)
> -#define MASK_ZCMP (1 << 5)
> -#define MASK_ZCMT (1 << 6)
> -
> -#define TARGET_ZCA ((riscv_zc_subext & MASK_ZCA) != 0)
> -#define TARGET_ZCB ((riscv_zc_subext & MASK_ZCB) != 0)
> -#define TARGET_ZCE ((riscv_zc_subext & MASK_ZCE) != 0)
> -#define TARGET_ZCF ((riscv_zc_subext & MASK_ZCF) != 0)
> -#define TARGET_ZCD ((riscv_zc_subext & MASK_ZCD) != 0)
> -#define TARGET_ZCMP ((riscv_zc_subext & MASK_ZCMP) != 0)
> -#define TARGET_ZCMT ((riscv_zc_subext & MASK_ZCMT) != 0)
> -
> -#define MASK_SVINVAL (1 << 0)
> -#define MASK_SVNAPOT (1 << 1)
> -
> -#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
> -#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
> -
> /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
> popcount to caclulate the minimal VLEN. */
> @@ -293,32 +107,6 @@ enum riscv_entity
> ? 0 \
> : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
>
> -#define MASK_XTHEADBA (1 << 0)
> -#define MASK_XTHEADBB (1 << 1)
> -#define MASK_XTHEADBS (1 << 2)
> -#define MASK_XTHEADCMO (1 << 3)
> -#define MASK_XTHEADCONDMOV (1 << 4)
> -#define MASK_XTHEADFMEMIDX (1 << 5)
> -#define MASK_XTHEADFMV (1 << 6)
> -#define MASK_XTHEADINT (1 << 7)
> -#define MASK_XTHEADMAC (1 << 8)
> -#define MASK_XTHEADMEMIDX (1 << 9)
> -#define MASK_XTHEADMEMPAIR (1 << 10)
> -#define MASK_XTHEADSYNC (1 << 11)
> -
> -#define TARGET_XTHEADBA ((riscv_xthead_subext & MASK_XTHEADBA) != 0)
> -#define TARGET_XTHEADBB ((riscv_xthead_subext & MASK_XTHEADBB) != 0)
> -#define TARGET_XTHEADBS ((riscv_xthead_subext & MASK_XTHEADBS) != 0)
> -#define TARGET_XTHEADCMO ((riscv_xthead_subext & MASK_XTHEADCMO) != 0)
> -#define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
> -#define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
> -#define TARGET_XTHEADFMV ((riscv_xthead_subext & MASK_XTHEADFMV) != 0)
> -#define TARGET_XTHEADINT ((riscv_xthead_subext & MASK_XTHEADINT) != 0)
> -#define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
> -#define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
> -#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
> -#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
> -
> /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
> is the highest priority choice and should not conflict with VLS modes. */
> #define TARGET_VECTOR_VLS \
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index d2407c3c502..4570c4b76c2 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -209,54 +209,228 @@ long riscv_stack_protector_guard_offset = 0
> TargetVariable
> int riscv_zi_subext
>
> +Mask(ZICSR) in TargetVariable(riscv_zi_subext)
> +
> +Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)
> +
> +Mask(ZIHINTNTL) in TargetVariable(riscv_zi_subext)
> +
> +Mask(ZIHINTPAUSE) in TargetVariable(riscv_zi_subext)
> +
> +Mask(ZICOND) in TargetVariable(riscv_zi_subext)
> +
> TargetVariable
> int riscv_za_subext
>
> +Mask(ZAWRS) in TargetVariable(riscv_za_subext)
> +
> TargetVariable
> int riscv_zb_subext
>
> +Mask(ZBA) in TargetVariable(riscv_zb_subext)
> +
> +Mask(ZBB) in TargetVariable(riscv_zb_subext)
> +
> +Mask(ZBC) in TargetVariable(riscv_zb_subext)
> +
> +Mask(ZBS) in TargetVariable(riscv_zb_subext)
> +
> TargetVariable
> int riscv_zinx_subext
>
> +Mask(ZFINX) in TargetVariable(riscv_zinx_subext)
> +
> +Mask(ZDINX) in TargetVariable(riscv_zinx_subext)
> +
> +Mask(ZHINX) in TargetVariable(riscv_zinx_subext)
> +
> +Mask(ZHINXMIN) in TargetVariable(riscv_zinx_subext)
> +
> TargetVariable
> int riscv_zk_subext
>
> +Mask(ZBKB) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZBKC) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZBKX) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKNE) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKND) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKNH) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKR) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKSED) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKSH) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKT) in TargetVariable(riscv_zk_subext)
> +
> TargetVariable
> int riscv_vector_elen_flags
>
> +Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
> +
> +Mask(VECTOR_ELEN_64) in TargetVariable(riscv_vector_elen_flags)
> +
> +Mask(VECTOR_ELEN_FP_32) in TargetVariable(riscv_vector_elen_flags)
> +
> +Mask(VECTOR_ELEN_FP_64) in TargetVariable(riscv_vector_elen_flags)
> +
> +Mask(VECTOR_ELEN_FP_16) in TargetVariable(riscv_vector_elen_flags)
> +
> TargetVariable
> int riscv_zvl_flags
>
> +Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL128B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL256B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL512B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL1024B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL2048B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL4096B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL8192B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL16384B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL32768B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL65536B) in TargetVariable(riscv_zvl_flags)
> +
> TargetVariable
> int riscv_zvb_subext
>
> +Mask(ZVBB) in TargetVariable(riscv_zvb_subext)
> +
> +Mask(ZVBC) in TargetVariable(riscv_zvb_subext)
> +
> TargetVariable
> int riscv_zvk_subext
>
> +Mask(ZVKG) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKNED) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKNHA) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKNHB) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKSED) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKSH) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKN) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKNC) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKNG) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKS) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKSC) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKSG) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKT) in TargetVariable(riscv_zvk_subext)
> +
> TargetVariable
> int riscv_zicmo_subext
>
> +Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
> +
> +Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
> +
> +Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
> +
> TargetVariable
> int riscv_zf_subext
>
> +Mask(ZFHMIN) in TargetVariable(riscv_zf_subext)
> +
> +Mask(ZFH) in TargetVariable(riscv_zf_subext)
> +
> +Mask(ZVFHMIN) in TargetVariable(riscv_zf_subext)
> +
> +Mask(ZVFH) in TargetVariable(riscv_zf_subext)
> +
> TargetVariable
> int riscv_zfa_subext
>
> +Mask(ZFA) in TargetVariable(riscv_zfa_subext)
> +
> TargetVariable
> int riscv_zm_subext
>
> +Mask(ZMMUL) in TargetVariable(riscv_zm_subext)
> +
> TargetVariable
> int riscv_zc_subext
>
> +Mask(ZCA) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCB) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCE) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCF) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCD) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCMP) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCMT) in TargetVariable(riscv_zc_subext)
> +
> TargetVariable
> int riscv_sv_subext
>
> +Mask(SVINVAL) in TargetVariable(riscv_sv_subext)
> +
> +Mask(SVNAPOT) in TargetVariable(riscv_sv_subext)
> +
> TargetVariable
> int riscv_ztso_subext
>
> +Mask(ZTSO) in TargetVariable(riscv_ztso_subext)
> +
> TargetVariable
> int riscv_xthead_subext
>
> +Mask(XTHEADBA) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADBB) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADBS) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADCMO) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADCONDMOV) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADFMEMIDX) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADFMV) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADINT) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADMAC) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADMEMIDX) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADMEMPAIR) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADSYNC) in TargetVariable(riscv_xthead_subext)
> +
> Enum
> Name(isa_spec_class) Type(enum riscv_isa_spec_class)
> Supported ISA specs (for use with the -misa-spec= option):
> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
> index f50063c9787..24663d8233e 100644
> --- a/gcc/doc/options.texi
> +++ b/gcc/doc/options.texi
> @@ -409,6 +409,12 @@ the value 1 when the option is active and 0 otherwise. If you use @code{Var}
> to attach the option to a different variable, the bitmask macro with be
> called @code{OPTION_MASK_@var{name}}.
>
> +@item Mask(@var{name}) in TargetVariable(@var{other_target_flags})
> +This method can be used to associate the option with a bit in @samp{other_target_flags}
> +which has been defined,when the option number exceeds the bits of @code{target_flags}.
> +The macro @code{MASK_@var{name}} and The @code{TARGET_@var{name}}
> +will aslo be generated automatically as described above .
> +
> @item InverseMask(@var{othername})
> @itemx InverseMask(@var{othername}, @var{thisname})
> The option is the inverse of another option that has the
> diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
> index 36de4639318..cbfcf7dabcf 100644
> --- a/gcc/opt-functions.awk
> +++ b/gcc/opt-functions.awk
> @@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option, uinteger_used)
> else
> return "-1, -1"
> }
> +
> +# Find the index of target variable from extra_target_vars
> +function find_index(var, var_arry, n_var_arry)
> +{
> + for (var_index = 0; var_index < n_var_arry; var_index++)
> + {
> + if (var_arry[var_index] == var)
> + break
> + }
> + return var_index
> +}
> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
> index fc4e3d77910..0ff2e806373 100644
> --- a/gcc/opt-read.awk
> +++ b/gcc/opt-read.awk
> @@ -22,6 +22,7 @@ BEGIN {
> n_opts = 0
> n_langs = 0
> n_target_save = 0
> + n_target_vars = 0
> n_extra_vars = 0
> n_extra_target_vars = 0
> n_extra_masks = 0
> @@ -121,7 +122,20 @@ BEGIN {
> n_opts++;
> }
> else {
> - extra_masks[n_extra_masks++] = name
> + if($0 ~ "in")
> + {
> + target_var = opt_args("TargetVariable", $1)
> + var_index = find_index(target_var, target_vars, n_target_vars)
> + if (var_index == n_target_vars)
> + {
> + target_vars[n_target_vars++] = target_var
> + }
> + other_masks[var_index][n_other_mask[var_index]++] = name
> + }
> + else
> + {
> + extra_masks[n_extra_masks++] = name
> + }
> }
> }
> }
> diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
> index 71404f9eff6..70ca3d37719 100644
> --- a/gcc/opth-gen.awk
> +++ b/gcc/opth-gen.awk
> @@ -406,6 +406,18 @@ for (i = 0; i < n_extra_masks; i++) {
> print "#define MASK_" extra_masks[i] " (1U << " masknum[""]++ ")"
> }
>
> +for (i = 0; i < n_target_vars; i++)
> +{
> + if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
> + continue
> + for (j = 0; j < n_other_mask[i]; j++)
> + {
> + print "#define MASK_" other_masks[i][j] " (1U << " other_masknum[i][""]++ ")"
> + }
> + if (other_masknum[i][""] > 32)
> + print "#error too many target masks for" extra_target_vars[i]
> +}
> +
> for (var in masknum) {
> if (var != "" && host_wide_int[var] == "yes") {
> print "#if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] " > HOST_BITS_PER_WIDE_INT"
> @@ -419,6 +431,16 @@ for (var in masknum) {
> print "#error too many masks for " var
> }
> }
> +for (i = 0; i < n_target_vars; i++)
> +{
> + if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
> + continue
> + for (j = 0; j < n_other_mask[i]; j++)
> + {
> + print "#define TARGET_" other_masks[i][j] \
> + " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 0)"
> + }
> +}
> print ""
>
> for (i = 0; i < n_opts; i++) {
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PATCH v3] RISC-V:Optimize the MASK opt generation
2023-09-06 3:42 ` Kito Cheng
@ 2023-09-06 6:38 ` Feng Wang
2023-09-06 7:19 ` Kito Cheng
0 siblings, 1 reply; 7+ messages in thread
From: Feng Wang @ 2023-09-06 6:38 UTC (permalink / raw)
To: kito.cheng; +Cc: gcc-patches
According to the doc, take“Mask(VECTOR_ELEN_32) Var(riscv_vector_elen_flags)”as example,
it just generates the OPTION_MASK_VECTOR_ELEN_32, will not generate MASK_VECTOR_ELEN_32
and TARGET_VECTOR_ELEN_32.
Do you want to use "MASK(name) Var(other_flags)" to generate the MASK and TARGET Macro?
I think it will change a lot of code and the original meaning is changed.
--------------
Feng Wang
>Reading the manual again, it seems I missed something in the manual
>before, the MASK syntax already says we can specify Var to select the
>variable other than target_flags, but I tried that not work when we
>only declare Mask with Var (e.g. "Mask(VECTOR_ELEN_32)
>Var(riscv_vector_elen_flags)" still using target_flags)
>
>So maybe we should just fix that instead of extending the syntax?
>e.g.
>Mask(VECTOR_ELEN_32) Var(riscv_vector_elen_flags)
>rather than
>Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
>
>
>On Wed, Sep 6, 2023 at 10:03 AM Feng Wang <wangfeng@eswincomputing.com> wrote:
>>
>> This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
>> generation" and add the new explanation in the options.texi.
>> Please check the detail info on the
>> "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html"
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv-opts.h (MASK_ZICSR):
>> (MASK_ZIFENCEI): Delete;
>> (MASK_ZIHINTNTL): Ditto;
>> (MASK_ZIHINTPAUSE): Ditto;
>> (TARGET_ZICSR): Ditto;
>> (TARGET_ZIFENCEI): Ditto;
>> (TARGET_ZIHINTNTL): Ditto;
>> (TARGET_ZIHINTPAUSE):Ditto;
>> (MASK_ZAWRS): Ditto;
>> (TARGET_ZAWRS): Ditto;
>> (MASK_ZBA): Ditto;
>> (MASK_ZBB): Ditto;
>> (MASK_ZBC): Ditto;
>> (MASK_ZBS): Ditto;
>> (TARGET_ZBA): Ditto;
>> (TARGET_ZBB): Ditto;
>> (TARGET_ZBC): Ditto;
>> (TARGET_ZBS): Ditto;
>> (MASK_ZFINX): Ditto;
>> (MASK_ZDINX): Ditto;
>> (MASK_ZHINX): Ditto;
>> (MASK_ZHINXMIN): Ditto;
>> (TARGET_ZFINX): Ditto;
>> (TARGET_ZDINX): Ditto;
>> (TARGET_ZHINX): Ditto;
>> (TARGET_ZHINXMIN): Ditto;
>> (MASK_ZBKB): Ditto;
>> (MASK_ZBKC): Ditto;
>> (MASK_ZBKX): Ditto;
>> (MASK_ZKNE): Ditto;
>> (MASK_ZKND): Ditto;
>> (MASK_ZKNH): Ditto;
>> (MASK_ZKR): Ditto;
>> (MASK_ZKSED): Ditto;
>> (MASK_ZKSH): Ditto;
>> (MASK_ZKT): Ditto;
>> (TARGET_ZBKB): Ditto;
>> (TARGET_ZBKC): Ditto;
>> (TARGET_ZBKX): Ditto;
>> (TARGET_ZKNE): Ditto;
>> (TARGET_ZKND): Ditto;
>> (TARGET_ZKNH): Ditto;
>> (TARGET_ZKR): Ditto;
>> (TARGET_ZKSED): Ditto;
>> (TARGET_ZKSH): Ditto;
>> (TARGET_ZKT): Ditto;
>> (MASK_ZTSO): Ditto;
>> (TARGET_ZTSO): Ditto;
>> (MASK_VECTOR_ELEN_32): Ditto;
>> (MASK_VECTOR_ELEN_64): Ditto;
>> (MASK_VECTOR_ELEN_FP_32):Ditto;
>> (MASK_VECTOR_ELEN_FP_64):Ditto;
>> (MASK_VECTOR_ELEN_FP_16):Ditto;
>> (TARGET_VECTOR_ELEN_32): Ditto;
>> (TARGET_VECTOR_ELEN_64): Ditto;
>> (TARGET_VECTOR_ELEN_FP_32):Ditto;
>> (TARGET_VECTOR_ELEN_FP_64):Ditto;
>> (TARGET_VECTOR_ELEN_FP_16):Ditto;
>> (MASK_ZVBB): Ditto;
>> (MASK_ZVBC): Ditto;
>> (TARGET_ZVBB): Ditto;
>> (TARGET_ZVBC): Ditto;
>> (MASK_ZVKG): Ditto;
>> (MASK_ZVKNED): Ditto;
>> (MASK_ZVKNHA): Ditto;
>> (MASK_ZVKNHB): Ditto;
>> (MASK_ZVKSED): Ditto;
>> (MASK_ZVKSH): Ditto;
>> (MASK_ZVKN): Ditto;
>> (MASK_ZVKNC): Ditto;
>> (MASK_ZVKNG): Ditto;
>> (MASK_ZVKS): Ditto;
>> (MASK_ZVKSC): Ditto;
>> (MASK_ZVKSG): Ditto;
>> (MASK_ZVKT): Ditto;
>> (TARGET_ZVKG): Ditto;
>> (TARGET_ZVKNED): Ditto;
>> (TARGET_ZVKNHA): Ditto;
>> (TARGET_ZVKNHB): Ditto;
>> (TARGET_ZVKSED): Ditto;
>> (TARGET_ZVKSH): Ditto;
>> (TARGET_ZVKN): Ditto;
>> (TARGET_ZVKNC): Ditto;
>> (TARGET_ZVKNG): Ditto;
>> (TARGET_ZVKS): Ditto;
>> (TARGET_ZVKSC): Ditto;
>> (TARGET_ZVKSG): Ditto;
>> (TARGET_ZVKT): Ditto;
>> (MASK_ZVL32B): Ditto;
>> (MASK_ZVL64B): Ditto;
>> (MASK_ZVL128B): Ditto;
>> (MASK_ZVL256B): Ditto;
>> (MASK_ZVL512B): Ditto;
>> (MASK_ZVL1024B): Ditto;
>> (MASK_ZVL2048B): Ditto;
>> (MASK_ZVL4096B): Ditto;
>> (MASK_ZVL8192B): Ditto;
>> (MASK_ZVL16384B): Ditto;
>> (MASK_ZVL32768B): Ditto;
>> (MASK_ZVL65536B): Ditto;
>> (TARGET_ZVL32B): Ditto;
>> (TARGET_ZVL64B): Ditto;
>> (TARGET_ZVL128B): Ditto;
>> (TARGET_ZVL256B): Ditto;
>> (TARGET_ZVL512B): Ditto;
>> (TARGET_ZVL1024B): Ditto;
>> (TARGET_ZVL2048B): Ditto;
>> (TARGET_ZVL4096B): Ditto;
>> (TARGET_ZVL8192B): Ditto;
>> (TARGET_ZVL16384B): Ditto;
>> (TARGET_ZVL32768B): Ditto;
>> (TARGET_ZVL65536B): Ditto;
>> (MASK_ZICBOZ): Ditto;
>> (MASK_ZICBOM): Ditto;
>> (MASK_ZICBOP): Ditto;
>> (TARGET_ZICBOZ): Ditto;
>> (TARGET_ZICBOM): Ditto;
>> (TARGET_ZICBOP): Ditto;
>> (MASK_ZICOND): Ditto;
>> (TARGET_ZICOND): Ditto;
>> (MASK_ZFA): Ditto;
>> (TARGET_ZFA): Ditto;
>> (MASK_ZFHMIN): Ditto;
>> (MASK_ZFH): Ditto;
>> (MASK_ZVFHMIN): Ditto;
>> (MASK_ZVFH): Ditto;
>> (TARGET_ZFHMIN): Ditto;
>> (TARGET_ZFH): Ditto;
>> (TARGET_ZVFHMIN): Ditto;
>> (TARGET_ZVFH): Ditto;
>> (MASK_ZMMUL): Ditto;
>> (TARGET_ZMMUL): Ditto;
>> (MASK_ZCA): Ditto;
>> (MASK_ZCB): Ditto;
>> (MASK_ZCE): Ditto;
>> (MASK_ZCF): Ditto;
>> (MASK_ZCD): Ditto;
>> (MASK_ZCMP): Ditto;
>> (MASK_ZCMT): Ditto;
>> (TARGET_ZCA): Ditto;
>> (TARGET_ZCB): Ditto;
>> (TARGET_ZCE): Ditto;
>> (TARGET_ZCF): Ditto;
>> (TARGET_ZCD): Ditto;
>> (TARGET_ZCMP): Ditto;
>> (TARGET_ZCMT): Ditto;
>> (MASK_SVINVAL): Ditto;
>> (MASK_SVNAPOT): Ditto;
>> (TARGET_SVINVAL): Ditto;
>> (TARGET_SVNAPOT): Ditto;
>> (MASK_XTHEADBA): Ditto;
>> (MASK_XTHEADBB): Ditto;
>> (MASK_XTHEADBS): Ditto;
>> (MASK_XTHEADCMO): Ditto;
>> (MASK_XTHEADCONDMOV): Ditto;
>> (MASK_XTHEADFMEMIDX): Ditto;
>> (MASK_XTHEADFMV): Ditto;
>> (MASK_XTHEADINT): Ditto;
>> (MASK_XTHEADMAC): Ditto;
>> (MASK_XTHEADMEMIDX): Ditto;
>> (MASK_XTHEADMEMPAIR): Ditto;
>> (MASK_XTHEADSYNC): Ditto;
>> (TARGET_XTHEADBA): Ditto;
>> (TARGET_XTHEADBB): Ditto;
>> (TARGET_XTHEADBS): Ditto;
>> (TARGET_XTHEADCMO): Ditto;
>> (TARGET_XTHEADCONDMOV):Ditto;
>> (TARGET_XTHEADFMEMIDX):Ditto;
>> (TARGET_XTHEADFMV): Ditto;
>> (TARGET_XTHEADINT): Ditto;
>> (TARGET_XTHEADMAC): Ditto;
>> (TARGET_XTHEADMEMIDX): Ditto;
>> (TARGET_XTHEADMEMPAIR):Ditto;
>> (TARGET_XTHEADSYNC): Ditto;
>> * config/riscv/riscv.opt: Add new Mask defination.
>> * doc/options.texi: Add new explanation for the usage.
>> * opt-functions.awk: Add new function to find the index
>> of target variable from extra_target_vars.
>> * opt-read.awk: Add new function to store the Mask flags.
>> * opth-gen.awk: Add new function to output the defination of
>> Mask Macro and Target Macro.
>> ---
>> gcc/config/riscv/riscv-opts.h | 212 ----------------------------------
>> gcc/config/riscv/riscv.opt | 174 ++++++++++++++++++++++++++++
>> gcc/doc/options.texi | 6 +
>> gcc/opt-functions.awk | 11 ++
>> gcc/opt-read.awk | 16 ++-
>> gcc/opth-gen.awk | 22 ++++
>> 6 files changed, 228 insertions(+), 213 deletions(-)
>>
>> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
>> index 5ed69abd214..07aa3cc83db 100644
>> --- a/gcc/config/riscv/riscv-opts.h
>> +++ b/gcc/config/riscv/riscv-opts.h
>> @@ -99,192 +99,6 @@ enum riscv_entity
>> MAX_RISCV_ENTITIES
>> };
>>
>> -#define MASK_ZICSR (1 << 0)
>> -#define MASK_ZIFENCEI (1 << 1)
>> -#define MASK_ZIHINTNTL (1 << 2)
>> -#define MASK_ZIHINTPAUSE (1 << 3)
>> -
>> -#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
>> -#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
>> -#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
>> -#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0)
>> -
>> -#define MASK_ZAWRS (1 << 0)
>> -#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
>> -
>> -#define MASK_ZBA (1 << 0)
>> -#define MASK_ZBB (1 << 1)
>> -#define MASK_ZBC (1 << 2)
>> -#define MASK_ZBS (1 << 3)
>> -
>> -#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
>> -#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
>> -#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
>> -#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
>> -
>> -#define MASK_ZFINX (1 << 0)
>> -#define MASK_ZDINX (1 << 1)
>> -#define MASK_ZHINX (1 << 2)
>> -#define MASK_ZHINXMIN (1 << 3)
>> -
>> -#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
>> -#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
>> -#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
>> -#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
>> -
>> -#define MASK_ZBKB (1 << 0)
>> -#define MASK_ZBKC (1 << 1)
>> -#define MASK_ZBKX (1 << 2)
>> -#define MASK_ZKNE (1 << 3)
>> -#define MASK_ZKND (1 << 4)
>> -#define MASK_ZKNH (1 << 5)
>> -#define MASK_ZKR (1 << 6)
>> -#define MASK_ZKSED (1 << 7)
>> -#define MASK_ZKSH (1 << 8)
>> -#define MASK_ZKT (1 << 9)
>> -
>> -#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
>> -#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
>> -#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
>> -#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
>> -#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
>> -#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
>> -#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
>> -#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
>> -#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
>> -#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
>> -
>> -#define MASK_ZTSO (1 << 0)
>> -
>> -#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0)
>> -
>> -#define MASK_VECTOR_ELEN_32 (1 << 0)
>> -#define MASK_VECTOR_ELEN_64 (1 << 1)
>> -#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
>> -#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
>> -/* Align the bit index to riscv-vector-builtins.h. */
>> -#define MASK_VECTOR_ELEN_FP_16 (1 << 6)
>> -
>> -#define TARGET_VECTOR_ELEN_32 \
>> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
>> -#define TARGET_VECTOR_ELEN_64 \
>> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
>> -#define TARGET_VECTOR_ELEN_FP_32 \
>> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
>> -#define TARGET_VECTOR_ELEN_FP_64 \
>> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
>> -#define TARGET_VECTOR_ELEN_FP_16 \
>> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_16) != 0)
>> -
>> -#define MASK_ZVBB (1 << 0)
>> -#define MASK_ZVBC (1 << 1)
>> -
>> -#define TARGET_ZVBB ((riscv_zvb_subext & MASK_ZVBB) != 0)
>> -#define TARGET_ZVBC ((riscv_zvb_subext & MASK_ZVBC) != 0)
>> -
>> -#define MASK_ZVKG (1 << 0)
>> -#define MASK_ZVKNED (1 << 1)
>> -#define MASK_ZVKNHA (1 << 2)
>> -#define MASK_ZVKNHB (1 << 3)
>> -#define MASK_ZVKSED (1 << 4)
>> -#define MASK_ZVKSH (1 << 5)
>> -#define MASK_ZVKN (1 << 6)
>> -#define MASK_ZVKNC (1 << 7)
>> -#define MASK_ZVKNG (1 << 8)
>> -#define MASK_ZVKS (1 << 9)
>> -#define MASK_ZVKSC (1 << 10)
>> -#define MASK_ZVKSG (1 << 11)
>> -#define MASK_ZVKT (1 << 12)
>> -
>> -#define TARGET_ZVKG ((riscv_zvk_subext & MASK_ZVKG) != 0)
>> -#define TARGET_ZVKNED ((riscv_zvk_subext & MASK_ZVKNED) != 0)
>> -#define TARGET_ZVKNHA ((riscv_zvk_subext & MASK_ZVKNHA) != 0)
>> -#define TARGET_ZVKNHB ((riscv_zvk_subext & MASK_ZVKNHB) != 0)
>> -#define TARGET_ZVKSED ((riscv_zvk_subext & MASK_ZVKSED) != 0)
>> -#define TARGET_ZVKSH ((riscv_zvk_subext & MASK_ZVKSH) != 0)
>> -#define TARGET_ZVKN ((riscv_zvk_subext & MASK_ZVKN) != 0)
>> -#define TARGET_ZVKNC ((riscv_zvk_subext & MASK_ZVKNC) != 0)
>> -#define TARGET_ZVKNG ((riscv_zvk_subext & MASK_ZVKNG) != 0)
>> -#define TARGET_ZVKS ((riscv_zvk_subext & MASK_ZVKS) != 0)
>> -#define TARGET_ZVKSC ((riscv_zvk_subext & MASK_ZVKSC) != 0)
>> -#define TARGET_ZVKSG ((riscv_zvk_subext & MASK_ZVKSG) != 0)
>> -#define TARGET_ZVKT ((riscv_zvk_subext & MASK_ZVKT) != 0)
>> -
>> -#define MASK_ZVL32B (1 << 0)
>> -#define MASK_ZVL64B (1 << 1)
>> -#define MASK_ZVL128B (1 << 2)
>> -#define MASK_ZVL256B (1 << 3)
>> -#define MASK_ZVL512B (1 << 4)
>> -#define MASK_ZVL1024B (1 << 5)
>> -#define MASK_ZVL2048B (1 << 6)
>> -#define MASK_ZVL4096B (1 << 7)
>> -#define MASK_ZVL8192B (1 << 8)
>> -#define MASK_ZVL16384B (1 << 9)
>> -#define MASK_ZVL32768B (1 << 10)
>> -#define MASK_ZVL65536B (1 << 11)
>> -
>> -#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
>> -#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
>> -#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
>> -#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
>> -#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
>> -#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
>> -#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
>> -#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
>> -#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
>> -#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
>> -#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
>> -#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
>> -
>> -#define MASK_ZICBOZ (1 << 0)
>> -#define MASK_ZICBOM (1 << 1)
>> -#define MASK_ZICBOP (1 << 2)
>> -
>> -#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
>> -#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
>> -#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
>> -
>> -#define MASK_ZICOND (1 << 2)
>> -#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0)
>> -
>> -#define MASK_ZFA (1 << 0)
>> -#define TARGET_ZFA ((riscv_zfa_subext & MASK_ZFA) != 0)
>> -
>> -#define MASK_ZFHMIN (1 << 0)
>> -#define MASK_ZFH (1 << 1)
>> -#define MASK_ZVFHMIN (1 << 2)
>> -#define MASK_ZVFH (1 << 3)
>> -
>> -#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
>> -#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
>> -#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
>> -#define TARGET_ZVFH ((riscv_zf_subext & MASK_ZVFH) != 0)
>> -
>> -#define MASK_ZMMUL (1 << 0)
>> -#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
>> -
>> -#define MASK_ZCA (1 << 0)
>> -#define MASK_ZCB (1 << 1)
>> -#define MASK_ZCE (1 << 2)
>> -#define MASK_ZCF (1 << 3)
>> -#define MASK_ZCD (1 << 4)
>> -#define MASK_ZCMP (1 << 5)
>> -#define MASK_ZCMT (1 << 6)
>> -
>> -#define TARGET_ZCA ((riscv_zc_subext & MASK_ZCA) != 0)
>> -#define TARGET_ZCB ((riscv_zc_subext & MASK_ZCB) != 0)
>> -#define TARGET_ZCE ((riscv_zc_subext & MASK_ZCE) != 0)
>> -#define TARGET_ZCF ((riscv_zc_subext & MASK_ZCF) != 0)
>> -#define TARGET_ZCD ((riscv_zc_subext & MASK_ZCD) != 0)
>> -#define TARGET_ZCMP ((riscv_zc_subext & MASK_ZCMP) != 0)
>> -#define TARGET_ZCMT ((riscv_zc_subext & MASK_ZCMT) != 0)
>> -
>> -#define MASK_SVINVAL (1 << 0)
>> -#define MASK_SVNAPOT (1 << 1)
>> -
>> -#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
>> -#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
>> -
>> /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
>> set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
>> popcount to caclulate the minimal VLEN. */
>> @@ -293,32 +107,6 @@ enum riscv_entity
>> ? 0 \
>> : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
>>
>> -#define MASK_XTHEADBA (1 << 0)
>> -#define MASK_XTHEADBB (1 << 1)
>> -#define MASK_XTHEADBS (1 << 2)
>> -#define MASK_XTHEADCMO (1 << 3)
>> -#define MASK_XTHEADCONDMOV (1 << 4)
>> -#define MASK_XTHEADFMEMIDX (1 << 5)
>> -#define MASK_XTHEADFMV (1 << 6)
>> -#define MASK_XTHEADINT (1 << 7)
>> -#define MASK_XTHEADMAC (1 << 8)
>> -#define MASK_XTHEADMEMIDX (1 << 9)
>> -#define MASK_XTHEADMEMPAIR (1 << 10)
>> -#define MASK_XTHEADSYNC (1 << 11)
>> -
>> -#define TARGET_XTHEADBA ((riscv_xthead_subext & MASK_XTHEADBA) != 0)
>> -#define TARGET_XTHEADBB ((riscv_xthead_subext & MASK_XTHEADBB) != 0)
>> -#define TARGET_XTHEADBS ((riscv_xthead_subext & MASK_XTHEADBS) != 0)
>> -#define TARGET_XTHEADCMO ((riscv_xthead_subext & MASK_XTHEADCMO) != 0)
>> -#define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
>> -#define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
>> -#define TARGET_XTHEADFMV ((riscv_xthead_subext & MASK_XTHEADFMV) != 0)
>> -#define TARGET_XTHEADINT ((riscv_xthead_subext & MASK_XTHEADINT) != 0)
>> -#define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
>> -#define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
>> -#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
>> -#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
>> -
>> /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
>> is the highest priority choice and should not conflict with VLS modes. */
>> #define TARGET_VECTOR_VLS \
>> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
>> index d2407c3c502..4570c4b76c2 100644
>> --- a/gcc/config/riscv/riscv.opt
>> +++ b/gcc/config/riscv/riscv.opt
>> @@ -209,54 +209,228 @@ long riscv_stack_protector_guard_offset = 0
>> TargetVariable
>> int riscv_zi_subext
>>
>> +Mask(ZICSR) in TargetVariable(riscv_zi_subext)
>> +
>> +Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)
>> +
>> +Mask(ZIHINTNTL) in TargetVariable(riscv_zi_subext)
>> +
>> +Mask(ZIHINTPAUSE) in TargetVariable(riscv_zi_subext)
>> +
>> +Mask(ZICOND) in TargetVariable(riscv_zi_subext)
>> +
>> TargetVariable
>> int riscv_za_subext
>>
>> +Mask(ZAWRS) in TargetVariable(riscv_za_subext)
>> +
>> TargetVariable
>> int riscv_zb_subext
>>
>> +Mask(ZBA) in TargetVariable(riscv_zb_subext)
>> +
>> +Mask(ZBB) in TargetVariable(riscv_zb_subext)
>> +
>> +Mask(ZBC) in TargetVariable(riscv_zb_subext)
>> +
>> +Mask(ZBS) in TargetVariable(riscv_zb_subext)
>> +
>> TargetVariable
>> int riscv_zinx_subext
>>
>> +Mask(ZFINX) in TargetVariable(riscv_zinx_subext)
>> +
>> +Mask(ZDINX) in TargetVariable(riscv_zinx_subext)
>> +
>> +Mask(ZHINX) in TargetVariable(riscv_zinx_subext)
>> +
>> +Mask(ZHINXMIN) in TargetVariable(riscv_zinx_subext)
>> +
>> TargetVariable
>> int riscv_zk_subext
>>
>> +Mask(ZBKB) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZBKC) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZBKX) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKNE) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKND) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKNH) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKR) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKSED) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKSH) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKT) in TargetVariable(riscv_zk_subext)
>> +
>> TargetVariable
>> int riscv_vector_elen_flags
>>
>> +Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
>> +
>> +Mask(VECTOR_ELEN_64) in TargetVariable(riscv_vector_elen_flags)
>> +
>> +Mask(VECTOR_ELEN_FP_32) in TargetVariable(riscv_vector_elen_flags)
>> +
>> +Mask(VECTOR_ELEN_FP_64) in TargetVariable(riscv_vector_elen_flags)
>> +
>> +Mask(VECTOR_ELEN_FP_16) in TargetVariable(riscv_vector_elen_flags)
>> +
>> TargetVariable
>> int riscv_zvl_flags
>>
>> +Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL128B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL256B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL512B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL1024B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL2048B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL4096B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL8192B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL16384B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL32768B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL65536B) in TargetVariable(riscv_zvl_flags)
>> +
>> TargetVariable
>> int riscv_zvb_subext
>>
>> +Mask(ZVBB) in TargetVariable(riscv_zvb_subext)
>> +
>> +Mask(ZVBC) in TargetVariable(riscv_zvb_subext)
>> +
>> TargetVariable
>> int riscv_zvk_subext
>>
>> +Mask(ZVKG) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKNED) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKNHA) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKNHB) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKSED) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKSH) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKN) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKNC) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKNG) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKS) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKSC) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKSG) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKT) in TargetVariable(riscv_zvk_subext)
>> +
>> TargetVariable
>> int riscv_zicmo_subext
>>
>> +Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
>> +
>> +Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
>> +
>> +Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
>> +
>> TargetVariable
>> int riscv_zf_subext
>>
>> +Mask(ZFHMIN) in TargetVariable(riscv_zf_subext)
>> +
>> +Mask(ZFH) in TargetVariable(riscv_zf_subext)
>> +
>> +Mask(ZVFHMIN) in TargetVariable(riscv_zf_subext)
>> +
>> +Mask(ZVFH) in TargetVariable(riscv_zf_subext)
>> +
>> TargetVariable
>> int riscv_zfa_subext
>>
>> +Mask(ZFA) in TargetVariable(riscv_zfa_subext)
>> +
>> TargetVariable
>> int riscv_zm_subext
>>
>> +Mask(ZMMUL) in TargetVariable(riscv_zm_subext)
>> +
>> TargetVariable
>> int riscv_zc_subext
>>
>> +Mask(ZCA) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCB) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCE) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCF) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCD) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCMP) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCMT) in TargetVariable(riscv_zc_subext)
>> +
>> TargetVariable
>> int riscv_sv_subext
>>
>> +Mask(SVINVAL) in TargetVariable(riscv_sv_subext)
>> +
>> +Mask(SVNAPOT) in TargetVariable(riscv_sv_subext)
>> +
>> TargetVariable
>> int riscv_ztso_subext
>>
>> +Mask(ZTSO) in TargetVariable(riscv_ztso_subext)
>> +
>> TargetVariable
>> int riscv_xthead_subext
>>
>> +Mask(XTHEADBA) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADBB) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADBS) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADCMO) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADCONDMOV) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADFMEMIDX) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADFMV) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADINT) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADMAC) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADMEMIDX) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADMEMPAIR) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADSYNC) in TargetVariable(riscv_xthead_subext)
>> +
>> Enum
>> Name(isa_spec_class) Type(enum riscv_isa_spec_class)
>> Supported ISA specs (for use with the -misa-spec= option):
>> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
>> index f50063c9787..24663d8233e 100644
>> --- a/gcc/doc/options.texi
>> +++ b/gcc/doc/options.texi
>> @@ -409,6 +409,12 @@ the value 1 when the option is active and 0 otherwise. If you use @code{Var}
>> to attach the option to a different variable, the bitmask macro with be
>> called @code{OPTION_MASK_@var{name}}.
>>
>> +@item Mask(@var{name}) in TargetVariable(@var{other_target_flags})
>> +This method can be used to associate the option with a bit in @samp{other_target_flags}
>> +which has been defined,when the option number exceeds the bits of @code{target_flags}.
>> +The macro @code{MASK_@var{name}} and The @code{TARGET_@var{name}}
>> +will aslo be generated automatically as described above .
>> +
>> @item InverseMask(@var{othername})
>> @itemx InverseMask(@var{othername}, @var{thisname})
>> The option is the inverse of another option that has the
>> diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
>> index 36de4639318..cbfcf7dabcf 100644
>> --- a/gcc/opt-functions.awk
>> +++ b/gcc/opt-functions.awk
>> @@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option, uinteger_used)
>> else
>> return "-1, -1"
>> }
>> +
>> +# Find the index of target variable from extra_target_vars
>> +function find_index(var, var_arry, n_var_arry)
>> +{
>> + for (var_index = 0; var_index < n_var_arry; var_index++)
>> + {
>> + if (var_arry[var_index] == var)
>> + break
>> + }
>> + return var_index
>> +}
>> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
>> index fc4e3d77910..0ff2e806373 100644
>> --- a/gcc/opt-read.awk
>> +++ b/gcc/opt-read.awk
>> @@ -22,6 +22,7 @@ BEGIN {
>> n_opts = 0
>> n_langs = 0
>> n_target_save = 0
>> + n_target_vars = 0
>> n_extra_vars = 0
>> n_extra_target_vars = 0
>> n_extra_masks = 0
>> @@ -121,7 +122,20 @@ BEGIN {
>> n_opts++;
>> }
>> else {
>> - extra_masks[n_extra_masks++] = name
>> + if($0 ~ "in")
>> + {
>> + target_var = opt_args("TargetVariable", $1)
>> + var_index = find_index(target_var, target_vars, n_target_vars)
>> + if (var_index == n_target_vars)
>> + {
>> + target_vars[n_target_vars++] = target_var
>> + }
>> + other_masks[var_index][n_other_mask[var_index]++] = name
>> + }
>> + else
>> + {
>> + extra_masks[n_extra_masks++] = name
>> + }
>> }
>> }
>> }
>> diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
>> index 71404f9eff6..70ca3d37719 100644
>> --- a/gcc/opth-gen.awk
>> +++ b/gcc/opth-gen.awk
>> @@ -406,6 +406,18 @@ for (i = 0; i < n_extra_masks; i++) {
>> print "#define MASK_" extra_masks[i] " (1U << " masknum[""]++ ")"
>> }
>>
>> +for (i = 0; i < n_target_vars; i++)
>> +{
>> + if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
>> + continue
>> + for (j = 0; j < n_other_mask[i]; j++)
>> + {
>> + print "#define MASK_" other_masks[i][j] " (1U << " other_masknum[i][""]++ ")"
>> + }
>> + if (other_masknum[i][""] > 32)
>> + print "#error too many target masks for" extra_target_vars[i]
>> +}
>> +
>> for (var in masknum) {
>> if (var != "" && host_wide_int[var] == "yes") {
>> print "#if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] " > HOST_BITS_PER_WIDE_INT"
>> @@ -419,6 +431,16 @@ for (var in masknum) {
>> print "#error too many masks for " var
>> }
>> }
>> +for (i = 0; i < n_target_vars; i++)
>> +{
>> + if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
>> + continue
>> + for (j = 0; j < n_other_mask[i]; j++)
>> + {
>> + print "#define TARGET_" other_masks[i][j] \
>> + " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 0)"
>> + }
>> +}
>> print ""
>>
>> for (i = 0; i < n_opts; i++) {
>> --
>> 2.17.1
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PATCH v3] RISC-V:Optimize the MASK opt generation
2023-09-06 6:38 ` Feng Wang
@ 2023-09-06 7:19 ` Kito Cheng
0 siblings, 0 replies; 7+ messages in thread
From: Kito Cheng @ 2023-09-06 7:19 UTC (permalink / raw)
To: Feng Wang; +Cc: gcc-patches
I saw RVC has MASK_RVC and TARGET_RVC in options.h?
On Wed, Sep 6, 2023 at 2:39 PM Feng Wang <wangfeng@eswincomputing.com> wrote:
>
> According to the doc, take“Mask(VECTOR_ELEN_32) Var(riscv_vector_elen_flags)”as example,
> it just generates the OPTION_MASK_VECTOR_ELEN_32, will not generate MASK_VECTOR_ELEN_32
> and TARGET_VECTOR_ELEN_32.
> Do you want to use "MASK(name) Var(other_flags)" to generate the MASK and TARGET Macro?
> I think it will change a lot of code and the original meaning is changed.
> --------------
> Feng Wang
> >Reading the manual again, it seems I missed something in the manual
> >before, the MASK syntax already says we can specify Var to select the
> >variable other than target_flags, but I tried that not work when we
> >only declare Mask with Var (e.g. "Mask(VECTOR_ELEN_32)
> >Var(riscv_vector_elen_flags)" still using target_flags)
> >
> >So maybe we should just fix that instead of extending the syntax?
> >e.g.
> >Mask(VECTOR_ELEN_32) Var(riscv_vector_elen_flags)
> >rather than
> >Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
> >
> >
> >On Wed, Sep 6, 2023 at 10:03 AM Feng Wang <wangfeng@eswincomputing.com> wrote:
> >>
> >> This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
> >> generation" and add the new explanation in the options.texi.
> >> Please check the detail info on the
> >> "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html"
> >> gcc/ChangeLog:
> >>
> >> * config/riscv/riscv-opts.h (MASK_ZICSR):
> >> (MASK_ZIFENCEI): Delete;
> >> (MASK_ZIHINTNTL): Ditto;
> >> (MASK_ZIHINTPAUSE): Ditto;
> >> (TARGET_ZICSR): Ditto;
> >> (TARGET_ZIFENCEI): Ditto;
> >> (TARGET_ZIHINTNTL): Ditto;
> >> (TARGET_ZIHINTPAUSE):Ditto;
> >> (MASK_ZAWRS): Ditto;
> >> (TARGET_ZAWRS): Ditto;
> >> (MASK_ZBA): Ditto;
> >> (MASK_ZBB): Ditto;
> >> (MASK_ZBC): Ditto;
> >> (MASK_ZBS): Ditto;
> >> (TARGET_ZBA): Ditto;
> >> (TARGET_ZBB): Ditto;
> >> (TARGET_ZBC): Ditto;
> >> (TARGET_ZBS): Ditto;
> >> (MASK_ZFINX): Ditto;
> >> (MASK_ZDINX): Ditto;
> >> (MASK_ZHINX): Ditto;
> >> (MASK_ZHINXMIN): Ditto;
> >> (TARGET_ZFINX): Ditto;
> >> (TARGET_ZDINX): Ditto;
> >> (TARGET_ZHINX): Ditto;
> >> (TARGET_ZHINXMIN): Ditto;
> >> (MASK_ZBKB): Ditto;
> >> (MASK_ZBKC): Ditto;
> >> (MASK_ZBKX): Ditto;
> >> (MASK_ZKNE): Ditto;
> >> (MASK_ZKND): Ditto;
> >> (MASK_ZKNH): Ditto;
> >> (MASK_ZKR): Ditto;
> >> (MASK_ZKSED): Ditto;
> >> (MASK_ZKSH): Ditto;
> >> (MASK_ZKT): Ditto;
> >> (TARGET_ZBKB): Ditto;
> >> (TARGET_ZBKC): Ditto;
> >> (TARGET_ZBKX): Ditto;
> >> (TARGET_ZKNE): Ditto;
> >> (TARGET_ZKND): Ditto;
> >> (TARGET_ZKNH): Ditto;
> >> (TARGET_ZKR): Ditto;
> >> (TARGET_ZKSED): Ditto;
> >> (TARGET_ZKSH): Ditto;
> >> (TARGET_ZKT): Ditto;
> >> (MASK_ZTSO): Ditto;
> >> (TARGET_ZTSO): Ditto;
> >> (MASK_VECTOR_ELEN_32): Ditto;
> >> (MASK_VECTOR_ELEN_64): Ditto;
> >> (MASK_VECTOR_ELEN_FP_32):Ditto;
> >> (MASK_VECTOR_ELEN_FP_64):Ditto;
> >> (MASK_VECTOR_ELEN_FP_16):Ditto;
> >> (TARGET_VECTOR_ELEN_32): Ditto;
> >> (TARGET_VECTOR_ELEN_64): Ditto;
> >> (TARGET_VECTOR_ELEN_FP_32):Ditto;
> >> (TARGET_VECTOR_ELEN_FP_64):Ditto;
> >> (TARGET_VECTOR_ELEN_FP_16):Ditto;
> >> (MASK_ZVBB): Ditto;
> >> (MASK_ZVBC): Ditto;
> >> (TARGET_ZVBB): Ditto;
> >> (TARGET_ZVBC): Ditto;
> >> (MASK_ZVKG): Ditto;
> >> (MASK_ZVKNED): Ditto;
> >> (MASK_ZVKNHA): Ditto;
> >> (MASK_ZVKNHB): Ditto;
> >> (MASK_ZVKSED): Ditto;
> >> (MASK_ZVKSH): Ditto;
> >> (MASK_ZVKN): Ditto;
> >> (MASK_ZVKNC): Ditto;
> >> (MASK_ZVKNG): Ditto;
> >> (MASK_ZVKS): Ditto;
> >> (MASK_ZVKSC): Ditto;
> >> (MASK_ZVKSG): Ditto;
> >> (MASK_ZVKT): Ditto;
> >> (TARGET_ZVKG): Ditto;
> >> (TARGET_ZVKNED): Ditto;
> >> (TARGET_ZVKNHA): Ditto;
> >> (TARGET_ZVKNHB): Ditto;
> >> (TARGET_ZVKSED): Ditto;
> >> (TARGET_ZVKSH): Ditto;
> >> (TARGET_ZVKN): Ditto;
> >> (TARGET_ZVKNC): Ditto;
> >> (TARGET_ZVKNG): Ditto;
> >> (TARGET_ZVKS): Ditto;
> >> (TARGET_ZVKSC): Ditto;
> >> (TARGET_ZVKSG): Ditto;
> >> (TARGET_ZVKT): Ditto;
> >> (MASK_ZVL32B): Ditto;
> >> (MASK_ZVL64B): Ditto;
> >> (MASK_ZVL128B): Ditto;
> >> (MASK_ZVL256B): Ditto;
> >> (MASK_ZVL512B): Ditto;
> >> (MASK_ZVL1024B): Ditto;
> >> (MASK_ZVL2048B): Ditto;
> >> (MASK_ZVL4096B): Ditto;
> >> (MASK_ZVL8192B): Ditto;
> >> (MASK_ZVL16384B): Ditto;
> >> (MASK_ZVL32768B): Ditto;
> >> (MASK_ZVL65536B): Ditto;
> >> (TARGET_ZVL32B): Ditto;
> >> (TARGET_ZVL64B): Ditto;
> >> (TARGET_ZVL128B): Ditto;
> >> (TARGET_ZVL256B): Ditto;
> >> (TARGET_ZVL512B): Ditto;
> >> (TARGET_ZVL1024B): Ditto;
> >> (TARGET_ZVL2048B): Ditto;
> >> (TARGET_ZVL4096B): Ditto;
> >> (TARGET_ZVL8192B): Ditto;
> >> (TARGET_ZVL16384B): Ditto;
> >> (TARGET_ZVL32768B): Ditto;
> >> (TARGET_ZVL65536B): Ditto;
> >> (MASK_ZICBOZ): Ditto;
> >> (MASK_ZICBOM): Ditto;
> >> (MASK_ZICBOP): Ditto;
> >> (TARGET_ZICBOZ): Ditto;
> >> (TARGET_ZICBOM): Ditto;
> >> (TARGET_ZICBOP): Ditto;
> >> (MASK_ZICOND): Ditto;
> >> (TARGET_ZICOND): Ditto;
> >> (MASK_ZFA): Ditto;
> >> (TARGET_ZFA): Ditto;
> >> (MASK_ZFHMIN): Ditto;
> >> (MASK_ZFH): Ditto;
> >> (MASK_ZVFHMIN): Ditto;
> >> (MASK_ZVFH): Ditto;
> >> (TARGET_ZFHMIN): Ditto;
> >> (TARGET_ZFH): Ditto;
> >> (TARGET_ZVFHMIN): Ditto;
> >> (TARGET_ZVFH): Ditto;
> >> (MASK_ZMMUL): Ditto;
> >> (TARGET_ZMMUL): Ditto;
> >> (MASK_ZCA): Ditto;
> >> (MASK_ZCB): Ditto;
> >> (MASK_ZCE): Ditto;
> >> (MASK_ZCF): Ditto;
> >> (MASK_ZCD): Ditto;
> >> (MASK_ZCMP): Ditto;
> >> (MASK_ZCMT): Ditto;
> >> (TARGET_ZCA): Ditto;
> >> (TARGET_ZCB): Ditto;
> >> (TARGET_ZCE): Ditto;
> >> (TARGET_ZCF): Ditto;
> >> (TARGET_ZCD): Ditto;
> >> (TARGET_ZCMP): Ditto;
> >> (TARGET_ZCMT): Ditto;
> >> (MASK_SVINVAL): Ditto;
> >> (MASK_SVNAPOT): Ditto;
> >> (TARGET_SVINVAL): Ditto;
> >> (TARGET_SVNAPOT): Ditto;
> >> (MASK_XTHEADBA): Ditto;
> >> (MASK_XTHEADBB): Ditto;
> >> (MASK_XTHEADBS): Ditto;
> >> (MASK_XTHEADCMO): Ditto;
> >> (MASK_XTHEADCONDMOV): Ditto;
> >> (MASK_XTHEADFMEMIDX): Ditto;
> >> (MASK_XTHEADFMV): Ditto;
> >> (MASK_XTHEADINT): Ditto;
> >> (MASK_XTHEADMAC): Ditto;
> >> (MASK_XTHEADMEMIDX): Ditto;
> >> (MASK_XTHEADMEMPAIR): Ditto;
> >> (MASK_XTHEADSYNC): Ditto;
> >> (TARGET_XTHEADBA): Ditto;
> >> (TARGET_XTHEADBB): Ditto;
> >> (TARGET_XTHEADBS): Ditto;
> >> (TARGET_XTHEADCMO): Ditto;
> >> (TARGET_XTHEADCONDMOV):Ditto;
> >> (TARGET_XTHEADFMEMIDX):Ditto;
> >> (TARGET_XTHEADFMV): Ditto;
> >> (TARGET_XTHEADINT): Ditto;
> >> (TARGET_XTHEADMAC): Ditto;
> >> (TARGET_XTHEADMEMIDX): Ditto;
> >> (TARGET_XTHEADMEMPAIR):Ditto;
> >> (TARGET_XTHEADSYNC): Ditto;
> >> * config/riscv/riscv.opt: Add new Mask defination.
> >> * doc/options.texi: Add new explanation for the usage.
> >> * opt-functions.awk: Add new function to find the index
> >> of target variable from extra_target_vars.
> >> * opt-read.awk: Add new function to store the Mask flags.
> >> * opth-gen.awk: Add new function to output the defination of
> >> Mask Macro and Target Macro.
> >> ---
> >> gcc/config/riscv/riscv-opts.h | 212 ----------------------------------
> >> gcc/config/riscv/riscv.opt | 174 ++++++++++++++++++++++++++++
> >> gcc/doc/options.texi | 6 +
> >> gcc/opt-functions.awk | 11 ++
> >> gcc/opt-read.awk | 16 ++-
> >> gcc/opth-gen.awk | 22 ++++
> >> 6 files changed, 228 insertions(+), 213 deletions(-)
> >>
> >> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> >> index 5ed69abd214..07aa3cc83db 100644
> >> --- a/gcc/config/riscv/riscv-opts.h
> >> +++ b/gcc/config/riscv/riscv-opts.h
> >> @@ -99,192 +99,6 @@ enum riscv_entity
> >> MAX_RISCV_ENTITIES
> >> };
> >>
> >> -#define MASK_ZICSR (1 << 0)
> >> -#define MASK_ZIFENCEI (1 << 1)
> >> -#define MASK_ZIHINTNTL (1 << 2)
> >> -#define MASK_ZIHINTPAUSE (1 << 3)
> >> -
> >> -#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
> >> -#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
> >> -#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
> >> -#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0)
> >> -
> >> -#define MASK_ZAWRS (1 << 0)
> >> -#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
> >> -
> >> -#define MASK_ZBA (1 << 0)
> >> -#define MASK_ZBB (1 << 1)
> >> -#define MASK_ZBC (1 << 2)
> >> -#define MASK_ZBS (1 << 3)
> >> -
> >> -#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
> >> -#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
> >> -#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
> >> -#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
> >> -
> >> -#define MASK_ZFINX (1 << 0)
> >> -#define MASK_ZDINX (1 << 1)
> >> -#define MASK_ZHINX (1 << 2)
> >> -#define MASK_ZHINXMIN (1 << 3)
> >> -
> >> -#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
> >> -#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
> >> -#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
> >> -#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
> >> -
> >> -#define MASK_ZBKB (1 << 0)
> >> -#define MASK_ZBKC (1 << 1)
> >> -#define MASK_ZBKX (1 << 2)
> >> -#define MASK_ZKNE (1 << 3)
> >> -#define MASK_ZKND (1 << 4)
> >> -#define MASK_ZKNH (1 << 5)
> >> -#define MASK_ZKR (1 << 6)
> >> -#define MASK_ZKSED (1 << 7)
> >> -#define MASK_ZKSH (1 << 8)
> >> -#define MASK_ZKT (1 << 9)
> >> -
> >> -#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
> >> -#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
> >> -#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
> >> -#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
> >> -#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
> >> -#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
> >> -#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
> >> -#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
> >> -#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
> >> -#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
> >> -
> >> -#define MASK_ZTSO (1 << 0)
> >> -
> >> -#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0)
> >> -
> >> -#define MASK_VECTOR_ELEN_32 (1 << 0)
> >> -#define MASK_VECTOR_ELEN_64 (1 << 1)
> >> -#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
> >> -#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
> >> -/* Align the bit index to riscv-vector-builtins.h. */
> >> -#define MASK_VECTOR_ELEN_FP_16 (1 << 6)
> >> -
> >> -#define TARGET_VECTOR_ELEN_32 \
> >> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
> >> -#define TARGET_VECTOR_ELEN_64 \
> >> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
> >> -#define TARGET_VECTOR_ELEN_FP_32 \
> >> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
> >> -#define TARGET_VECTOR_ELEN_FP_64 \
> >> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
> >> -#define TARGET_VECTOR_ELEN_FP_16 \
> >> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_16) != 0)
> >> -
> >> -#define MASK_ZVBB (1 << 0)
> >> -#define MASK_ZVBC (1 << 1)
> >> -
> >> -#define TARGET_ZVBB ((riscv_zvb_subext & MASK_ZVBB) != 0)
> >> -#define TARGET_ZVBC ((riscv_zvb_subext & MASK_ZVBC) != 0)
> >> -
> >> -#define MASK_ZVKG (1 << 0)
> >> -#define MASK_ZVKNED (1 << 1)
> >> -#define MASK_ZVKNHA (1 << 2)
> >> -#define MASK_ZVKNHB (1 << 3)
> >> -#define MASK_ZVKSED (1 << 4)
> >> -#define MASK_ZVKSH (1 << 5)
> >> -#define MASK_ZVKN (1 << 6)
> >> -#define MASK_ZVKNC (1 << 7)
> >> -#define MASK_ZVKNG (1 << 8)
> >> -#define MASK_ZVKS (1 << 9)
> >> -#define MASK_ZVKSC (1 << 10)
> >> -#define MASK_ZVKSG (1 << 11)
> >> -#define MASK_ZVKT (1 << 12)
> >> -
> >> -#define TARGET_ZVKG ((riscv_zvk_subext & MASK_ZVKG) != 0)
> >> -#define TARGET_ZVKNED ((riscv_zvk_subext & MASK_ZVKNED) != 0)
> >> -#define TARGET_ZVKNHA ((riscv_zvk_subext & MASK_ZVKNHA) != 0)
> >> -#define TARGET_ZVKNHB ((riscv_zvk_subext & MASK_ZVKNHB) != 0)
> >> -#define TARGET_ZVKSED ((riscv_zvk_subext & MASK_ZVKSED) != 0)
> >> -#define TARGET_ZVKSH ((riscv_zvk_subext & MASK_ZVKSH) != 0)
> >> -#define TARGET_ZVKN ((riscv_zvk_subext & MASK_ZVKN) != 0)
> >> -#define TARGET_ZVKNC ((riscv_zvk_subext & MASK_ZVKNC) != 0)
> >> -#define TARGET_ZVKNG ((riscv_zvk_subext & MASK_ZVKNG) != 0)
> >> -#define TARGET_ZVKS ((riscv_zvk_subext & MASK_ZVKS) != 0)
> >> -#define TARGET_ZVKSC ((riscv_zvk_subext & MASK_ZVKSC) != 0)
> >> -#define TARGET_ZVKSG ((riscv_zvk_subext & MASK_ZVKSG) != 0)
> >> -#define TARGET_ZVKT ((riscv_zvk_subext & MASK_ZVKT) != 0)
> >> -
> >> -#define MASK_ZVL32B (1 << 0)
> >> -#define MASK_ZVL64B (1 << 1)
> >> -#define MASK_ZVL128B (1 << 2)
> >> -#define MASK_ZVL256B (1 << 3)
> >> -#define MASK_ZVL512B (1 << 4)
> >> -#define MASK_ZVL1024B (1 << 5)
> >> -#define MASK_ZVL2048B (1 << 6)
> >> -#define MASK_ZVL4096B (1 << 7)
> >> -#define MASK_ZVL8192B (1 << 8)
> >> -#define MASK_ZVL16384B (1 << 9)
> >> -#define MASK_ZVL32768B (1 << 10)
> >> -#define MASK_ZVL65536B (1 << 11)
> >> -
> >> -#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
> >> -#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
> >> -#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
> >> -#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
> >> -#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
> >> -#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
> >> -#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
> >> -#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
> >> -#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
> >> -#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
> >> -#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
> >> -#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
> >> -
> >> -#define MASK_ZICBOZ (1 << 0)
> >> -#define MASK_ZICBOM (1 << 1)
> >> -#define MASK_ZICBOP (1 << 2)
> >> -
> >> -#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
> >> -#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
> >> -#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
> >> -
> >> -#define MASK_ZICOND (1 << 2)
> >> -#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0)
> >> -
> >> -#define MASK_ZFA (1 << 0)
> >> -#define TARGET_ZFA ((riscv_zfa_subext & MASK_ZFA) != 0)
> >> -
> >> -#define MASK_ZFHMIN (1 << 0)
> >> -#define MASK_ZFH (1 << 1)
> >> -#define MASK_ZVFHMIN (1 << 2)
> >> -#define MASK_ZVFH (1 << 3)
> >> -
> >> -#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> >> -#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
> >> -#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
> >> -#define TARGET_ZVFH ((riscv_zf_subext & MASK_ZVFH) != 0)
> >> -
> >> -#define MASK_ZMMUL (1 << 0)
> >> -#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
> >> -
> >> -#define MASK_ZCA (1 << 0)
> >> -#define MASK_ZCB (1 << 1)
> >> -#define MASK_ZCE (1 << 2)
> >> -#define MASK_ZCF (1 << 3)
> >> -#define MASK_ZCD (1 << 4)
> >> -#define MASK_ZCMP (1 << 5)
> >> -#define MASK_ZCMT (1 << 6)
> >> -
> >> -#define TARGET_ZCA ((riscv_zc_subext & MASK_ZCA) != 0)
> >> -#define TARGET_ZCB ((riscv_zc_subext & MASK_ZCB) != 0)
> >> -#define TARGET_ZCE ((riscv_zc_subext & MASK_ZCE) != 0)
> >> -#define TARGET_ZCF ((riscv_zc_subext & MASK_ZCF) != 0)
> >> -#define TARGET_ZCD ((riscv_zc_subext & MASK_ZCD) != 0)
> >> -#define TARGET_ZCMP ((riscv_zc_subext & MASK_ZCMP) != 0)
> >> -#define TARGET_ZCMT ((riscv_zc_subext & MASK_ZCMT) != 0)
> >> -
> >> -#define MASK_SVINVAL (1 << 0)
> >> -#define MASK_SVNAPOT (1 << 1)
> >> -
> >> -#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
> >> -#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
> >> -
> >> /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> >> set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
> >> popcount to caclulate the minimal VLEN. */
> >> @@ -293,32 +107,6 @@ enum riscv_entity
> >> ? 0 \
> >> : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
> >>
> >> -#define MASK_XTHEADBA (1 << 0)
> >> -#define MASK_XTHEADBB (1 << 1)
> >> -#define MASK_XTHEADBS (1 << 2)
> >> -#define MASK_XTHEADCMO (1 << 3)
> >> -#define MASK_XTHEADCONDMOV (1 << 4)
> >> -#define MASK_XTHEADFMEMIDX (1 << 5)
> >> -#define MASK_XTHEADFMV (1 << 6)
> >> -#define MASK_XTHEADINT (1 << 7)
> >> -#define MASK_XTHEADMAC (1 << 8)
> >> -#define MASK_XTHEADMEMIDX (1 << 9)
> >> -#define MASK_XTHEADMEMPAIR (1 << 10)
> >> -#define MASK_XTHEADSYNC (1 << 11)
> >> -
> >> -#define TARGET_XTHEADBA ((riscv_xthead_subext & MASK_XTHEADBA) != 0)
> >> -#define TARGET_XTHEADBB ((riscv_xthead_subext & MASK_XTHEADBB) != 0)
> >> -#define TARGET_XTHEADBS ((riscv_xthead_subext & MASK_XTHEADBS) != 0)
> >> -#define TARGET_XTHEADCMO ((riscv_xthead_subext & MASK_XTHEADCMO) != 0)
> >> -#define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
> >> -#define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
> >> -#define TARGET_XTHEADFMV ((riscv_xthead_subext & MASK_XTHEADFMV) != 0)
> >> -#define TARGET_XTHEADINT ((riscv_xthead_subext & MASK_XTHEADINT) != 0)
> >> -#define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
> >> -#define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
> >> -#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
> >> -#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
> >> -
> >> /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
> >> is the highest priority choice and should not conflict with VLS modes. */
> >> #define TARGET_VECTOR_VLS \
> >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> >> index d2407c3c502..4570c4b76c2 100644
> >> --- a/gcc/config/riscv/riscv.opt
> >> +++ b/gcc/config/riscv/riscv.opt
> >> @@ -209,54 +209,228 @@ long riscv_stack_protector_guard_offset = 0
> >> TargetVariable
> >> int riscv_zi_subext
> >>
> >> +Mask(ZICSR) in TargetVariable(riscv_zi_subext)
> >> +
> >> +Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)
> >> +
> >> +Mask(ZIHINTNTL) in TargetVariable(riscv_zi_subext)
> >> +
> >> +Mask(ZIHINTPAUSE) in TargetVariable(riscv_zi_subext)
> >> +
> >> +Mask(ZICOND) in TargetVariable(riscv_zi_subext)
> >> +
> >> TargetVariable
> >> int riscv_za_subext
> >>
> >> +Mask(ZAWRS) in TargetVariable(riscv_za_subext)
> >> +
> >> TargetVariable
> >> int riscv_zb_subext
> >>
> >> +Mask(ZBA) in TargetVariable(riscv_zb_subext)
> >> +
> >> +Mask(ZBB) in TargetVariable(riscv_zb_subext)
> >> +
> >> +Mask(ZBC) in TargetVariable(riscv_zb_subext)
> >> +
> >> +Mask(ZBS) in TargetVariable(riscv_zb_subext)
> >> +
> >> TargetVariable
> >> int riscv_zinx_subext
> >>
> >> +Mask(ZFINX) in TargetVariable(riscv_zinx_subext)
> >> +
> >> +Mask(ZDINX) in TargetVariable(riscv_zinx_subext)
> >> +
> >> +Mask(ZHINX) in TargetVariable(riscv_zinx_subext)
> >> +
> >> +Mask(ZHINXMIN) in TargetVariable(riscv_zinx_subext)
> >> +
> >> TargetVariable
> >> int riscv_zk_subext
> >>
> >> +Mask(ZBKB) in TargetVariable(riscv_zk_subext)
> >> +
> >> +Mask(ZBKC) in TargetVariable(riscv_zk_subext)
> >> +
> >> +Mask(ZBKX) in TargetVariable(riscv_zk_subext)
> >> +
> >> +Mask(ZKNE) in TargetVariable(riscv_zk_subext)
> >> +
> >> +Mask(ZKND) in TargetVariable(riscv_zk_subext)
> >> +
> >> +Mask(ZKNH) in TargetVariable(riscv_zk_subext)
> >> +
> >> +Mask(ZKR) in TargetVariable(riscv_zk_subext)
> >> +
> >> +Mask(ZKSED) in TargetVariable(riscv_zk_subext)
> >> +
> >> +Mask(ZKSH) in TargetVariable(riscv_zk_subext)
> >> +
> >> +Mask(ZKT) in TargetVariable(riscv_zk_subext)
> >> +
> >> TargetVariable
> >> int riscv_vector_elen_flags
> >>
> >> +Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
> >> +
> >> +Mask(VECTOR_ELEN_64) in TargetVariable(riscv_vector_elen_flags)
> >> +
> >> +Mask(VECTOR_ELEN_FP_32) in TargetVariable(riscv_vector_elen_flags)
> >> +
> >> +Mask(VECTOR_ELEN_FP_64) in TargetVariable(riscv_vector_elen_flags)
> >> +
> >> +Mask(VECTOR_ELEN_FP_16) in TargetVariable(riscv_vector_elen_flags)
> >> +
> >> TargetVariable
> >> int riscv_zvl_flags
> >>
> >> +Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> +Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> +Mask(ZVL128B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> +Mask(ZVL256B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> +Mask(ZVL512B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> +Mask(ZVL1024B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> +Mask(ZVL2048B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> +Mask(ZVL4096B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> +Mask(ZVL8192B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> +Mask(ZVL16384B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> +Mask(ZVL32768B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> +Mask(ZVL65536B) in TargetVariable(riscv_zvl_flags)
> >> +
> >> TargetVariable
> >> int riscv_zvb_subext
> >>
> >> +Mask(ZVBB) in TargetVariable(riscv_zvb_subext)
> >> +
> >> +Mask(ZVBC) in TargetVariable(riscv_zvb_subext)
> >> +
> >> TargetVariable
> >> int riscv_zvk_subext
> >>
> >> +Mask(ZVKG) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKNED) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKNHA) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKNHB) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKSED) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKSH) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKN) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKNC) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKNG) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKS) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKSC) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKSG) in TargetVariable(riscv_zvk_subext)
> >> +
> >> +Mask(ZVKT) in TargetVariable(riscv_zvk_subext)
> >> +
> >> TargetVariable
> >> int riscv_zicmo_subext
> >>
> >> +Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
> >> +
> >> +Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
> >> +
> >> +Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
> >> +
> >> TargetVariable
> >> int riscv_zf_subext
> >>
> >> +Mask(ZFHMIN) in TargetVariable(riscv_zf_subext)
> >> +
> >> +Mask(ZFH) in TargetVariable(riscv_zf_subext)
> >> +
> >> +Mask(ZVFHMIN) in TargetVariable(riscv_zf_subext)
> >> +
> >> +Mask(ZVFH) in TargetVariable(riscv_zf_subext)
> >> +
> >> TargetVariable
> >> int riscv_zfa_subext
> >>
> >> +Mask(ZFA) in TargetVariable(riscv_zfa_subext)
> >> +
> >> TargetVariable
> >> int riscv_zm_subext
> >>
> >> +Mask(ZMMUL) in TargetVariable(riscv_zm_subext)
> >> +
> >> TargetVariable
> >> int riscv_zc_subext
> >>
> >> +Mask(ZCA) in TargetVariable(riscv_zc_subext)
> >> +
> >> +Mask(ZCB) in TargetVariable(riscv_zc_subext)
> >> +
> >> +Mask(ZCE) in TargetVariable(riscv_zc_subext)
> >> +
> >> +Mask(ZCF) in TargetVariable(riscv_zc_subext)
> >> +
> >> +Mask(ZCD) in TargetVariable(riscv_zc_subext)
> >> +
> >> +Mask(ZCMP) in TargetVariable(riscv_zc_subext)
> >> +
> >> +Mask(ZCMT) in TargetVariable(riscv_zc_subext)
> >> +
> >> TargetVariable
> >> int riscv_sv_subext
> >>
> >> +Mask(SVINVAL) in TargetVariable(riscv_sv_subext)
> >> +
> >> +Mask(SVNAPOT) in TargetVariable(riscv_sv_subext)
> >> +
> >> TargetVariable
> >> int riscv_ztso_subext
> >>
> >> +Mask(ZTSO) in TargetVariable(riscv_ztso_subext)
> >> +
> >> TargetVariable
> >> int riscv_xthead_subext
> >>
> >> +Mask(XTHEADBA) in TargetVariable(riscv_xthead_subext)
> >> +
> >> +Mask(XTHEADBB) in TargetVariable(riscv_xthead_subext)
> >> +
> >> +Mask(XTHEADBS) in TargetVariable(riscv_xthead_subext)
> >> +
> >> +Mask(XTHEADCMO) in TargetVariable(riscv_xthead_subext)
> >> +
> >> +Mask(XTHEADCONDMOV) in TargetVariable(riscv_xthead_subext)
> >> +
> >> +Mask(XTHEADFMEMIDX) in TargetVariable(riscv_xthead_subext)
> >> +
> >> +Mask(XTHEADFMV) in TargetVariable(riscv_xthead_subext)
> >> +
> >> +Mask(XTHEADINT) in TargetVariable(riscv_xthead_subext)
> >> +
> >> +Mask(XTHEADMAC) in TargetVariable(riscv_xthead_subext)
> >> +
> >> +Mask(XTHEADMEMIDX) in TargetVariable(riscv_xthead_subext)
> >> +
> >> +Mask(XTHEADMEMPAIR) in TargetVariable(riscv_xthead_subext)
> >> +
> >> +Mask(XTHEADSYNC) in TargetVariable(riscv_xthead_subext)
> >> +
> >> Enum
> >> Name(isa_spec_class) Type(enum riscv_isa_spec_class)
> >> Supported ISA specs (for use with the -misa-spec= option):
> >> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
> >> index f50063c9787..24663d8233e 100644
> >> --- a/gcc/doc/options.texi
> >> +++ b/gcc/doc/options.texi
> >> @@ -409,6 +409,12 @@ the value 1 when the option is active and 0 otherwise. If you use @code{Var}
> >> to attach the option to a different variable, the bitmask macro with be
> >> called @code{OPTION_MASK_@var{name}}.
> >>
> >> +@item Mask(@var{name}) in TargetVariable(@var{other_target_flags})
> >> +This method can be used to associate the option with a bit in @samp{other_target_flags}
> >> +which has been defined,when the option number exceeds the bits of @code{target_flags}.
> >> +The macro @code{MASK_@var{name}} and The @code{TARGET_@var{name}}
> >> +will aslo be generated automatically as described above .
> >> +
> >> @item InverseMask(@var{othername})
> >> @itemx InverseMask(@var{othername}, @var{thisname})
> >> The option is the inverse of another option that has the
> >> diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
> >> index 36de4639318..cbfcf7dabcf 100644
> >> --- a/gcc/opt-functions.awk
> >> +++ b/gcc/opt-functions.awk
> >> @@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option, uinteger_used)
> >> else
> >> return "-1, -1"
> >> }
> >> +
> >> +# Find the index of target variable from extra_target_vars
> >> +function find_index(var, var_arry, n_var_arry)
> >> +{
> >> + for (var_index = 0; var_index < n_var_arry; var_index++)
> >> + {
> >> + if (var_arry[var_index] == var)
> >> + break
> >> + }
> >> + return var_index
> >> +}
> >> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
> >> index fc4e3d77910..0ff2e806373 100644
> >> --- a/gcc/opt-read.awk
> >> +++ b/gcc/opt-read.awk
> >> @@ -22,6 +22,7 @@ BEGIN {
> >> n_opts = 0
> >> n_langs = 0
> >> n_target_save = 0
> >> + n_target_vars = 0
> >> n_extra_vars = 0
> >> n_extra_target_vars = 0
> >> n_extra_masks = 0
> >> @@ -121,7 +122,20 @@ BEGIN {
> >> n_opts++;
> >> }
> >> else {
> >> - extra_masks[n_extra_masks++] = name
> >> + if($0 ~ "in")
> >> + {
> >> + target_var = opt_args("TargetVariable", $1)
> >> + var_index = find_index(target_var, target_vars, n_target_vars)
> >> + if (var_index == n_target_vars)
> >> + {
> >> + target_vars[n_target_vars++] = target_var
> >> + }
> >> + other_masks[var_index][n_other_mask[var_index]++] = name
> >> + }
> >> + else
> >> + {
> >> + extra_masks[n_extra_masks++] = name
> >> + }
> >> }
> >> }
> >> }
> >> diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
> >> index 71404f9eff6..70ca3d37719 100644
> >> --- a/gcc/opth-gen.awk
> >> +++ b/gcc/opth-gen.awk
> >> @@ -406,6 +406,18 @@ for (i = 0; i < n_extra_masks; i++) {
> >> print "#define MASK_" extra_masks[i] " (1U << " masknum[""]++ ")"
> >> }
> >>
> >> +for (i = 0; i < n_target_vars; i++)
> >> +{
> >> + if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
> >> + continue
> >> + for (j = 0; j < n_other_mask[i]; j++)
> >> + {
> >> + print "#define MASK_" other_masks[i][j] " (1U << " other_masknum[i][""]++ ")"
> >> + }
> >> + if (other_masknum[i][""] > 32)
> >> + print "#error too many target masks for" extra_target_vars[i]
> >> +}
> >> +
> >> for (var in masknum) {
> >> if (var != "" && host_wide_int[var] == "yes") {
> >> print "#if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] " > HOST_BITS_PER_WIDE_INT"
> >> @@ -419,6 +431,16 @@ for (var in masknum) {
> >> print "#error too many masks for " var
> >> }
> >> }
> >> +for (i = 0; i < n_target_vars; i++)
> >> +{
> >> + if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
> >> + continue
> >> + for (j = 0; j < n_other_mask[i]; j++)
> >> + {
> >> + print "#define TARGET_" other_masks[i][j] \
> >> + " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 0)"
> >> + }
> >> +}
> >> print ""
> >>
> >> for (i = 0; i < n_opts; i++) {
> >> --
> >> 2.17.1
> >>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] RISC-V:Optimize the MASK opt generation
2023-09-06 2:02 [PATCH v3] RISC-V:Optimize the MASK opt generation Feng Wang
2023-09-06 3:42 ` Kito Cheng
@ 2023-09-07 0:48 ` Tsukasa OI
2023-09-07 1:17 ` Feng Wang
1 sibling, 1 reply; 7+ messages in thread
From: Tsukasa OI @ 2023-09-07 0:48 UTC (permalink / raw)
To: Feng Wang; +Cc: GCC Patches
Hi,
I will need to notify you that x_riscv_xventana_subext,
MASK_XVENTANACONDOPS and TARGET_XVENTANACONDOPS are added (I think you
want to rewrite those definitions like the rest). Also, be careful not
to remove TARGET_ZICOND_LIKE.
Thanks,
Tsukasa
On 2023/09/06 11:02, Feng Wang wrote:
> This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
> generation" and add the new explanation in the options.texi.
> Please check the detail info on the
> "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html"
> gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h (MASK_ZICSR):
> (MASK_ZIFENCEI): Delete;
> (MASK_ZIHINTNTL): Ditto;
> (MASK_ZIHINTPAUSE): Ditto;
> (TARGET_ZICSR): Ditto;
> (TARGET_ZIFENCEI): Ditto;
> (TARGET_ZIHINTNTL): Ditto;
> (TARGET_ZIHINTPAUSE):Ditto;
> (MASK_ZAWRS): Ditto;
> (TARGET_ZAWRS): Ditto;
> (MASK_ZBA): Ditto;
> (MASK_ZBB): Ditto;
> (MASK_ZBC): Ditto;
> (MASK_ZBS): Ditto;
> (TARGET_ZBA): Ditto;
> (TARGET_ZBB): Ditto;
> (TARGET_ZBC): Ditto;
> (TARGET_ZBS): Ditto;
> (MASK_ZFINX): Ditto;
> (MASK_ZDINX): Ditto;
> (MASK_ZHINX): Ditto;
> (MASK_ZHINXMIN): Ditto;
> (TARGET_ZFINX): Ditto;
> (TARGET_ZDINX): Ditto;
> (TARGET_ZHINX): Ditto;
> (TARGET_ZHINXMIN): Ditto;
> (MASK_ZBKB): Ditto;
> (MASK_ZBKC): Ditto;
> (MASK_ZBKX): Ditto;
> (MASK_ZKNE): Ditto;
> (MASK_ZKND): Ditto;
> (MASK_ZKNH): Ditto;
> (MASK_ZKR): Ditto;
> (MASK_ZKSED): Ditto;
> (MASK_ZKSH): Ditto;
> (MASK_ZKT): Ditto;
> (TARGET_ZBKB): Ditto;
> (TARGET_ZBKC): Ditto;
> (TARGET_ZBKX): Ditto;
> (TARGET_ZKNE): Ditto;
> (TARGET_ZKND): Ditto;
> (TARGET_ZKNH): Ditto;
> (TARGET_ZKR): Ditto;
> (TARGET_ZKSED): Ditto;
> (TARGET_ZKSH): Ditto;
> (TARGET_ZKT): Ditto;
> (MASK_ZTSO): Ditto;
> (TARGET_ZTSO): Ditto;
> (MASK_VECTOR_ELEN_32): Ditto;
> (MASK_VECTOR_ELEN_64): Ditto;
> (MASK_VECTOR_ELEN_FP_32):Ditto;
> (MASK_VECTOR_ELEN_FP_64):Ditto;
> (MASK_VECTOR_ELEN_FP_16):Ditto;
> (TARGET_VECTOR_ELEN_32): Ditto;
> (TARGET_VECTOR_ELEN_64): Ditto;
> (TARGET_VECTOR_ELEN_FP_32):Ditto;
> (TARGET_VECTOR_ELEN_FP_64):Ditto;
> (TARGET_VECTOR_ELEN_FP_16):Ditto;
> (MASK_ZVBB): Ditto;
> (MASK_ZVBC): Ditto;
> (TARGET_ZVBB): Ditto;
> (TARGET_ZVBC): Ditto;
> (MASK_ZVKG): Ditto;
> (MASK_ZVKNED): Ditto;
> (MASK_ZVKNHA): Ditto;
> (MASK_ZVKNHB): Ditto;
> (MASK_ZVKSED): Ditto;
> (MASK_ZVKSH): Ditto;
> (MASK_ZVKN): Ditto;
> (MASK_ZVKNC): Ditto;
> (MASK_ZVKNG): Ditto;
> (MASK_ZVKS): Ditto;
> (MASK_ZVKSC): Ditto;
> (MASK_ZVKSG): Ditto;
> (MASK_ZVKT): Ditto;
> (TARGET_ZVKG): Ditto;
> (TARGET_ZVKNED): Ditto;
> (TARGET_ZVKNHA): Ditto;
> (TARGET_ZVKNHB): Ditto;
> (TARGET_ZVKSED): Ditto;
> (TARGET_ZVKSH): Ditto;
> (TARGET_ZVKN): Ditto;
> (TARGET_ZVKNC): Ditto;
> (TARGET_ZVKNG): Ditto;
> (TARGET_ZVKS): Ditto;
> (TARGET_ZVKSC): Ditto;
> (TARGET_ZVKSG): Ditto;
> (TARGET_ZVKT): Ditto;
> (MASK_ZVL32B): Ditto;
> (MASK_ZVL64B): Ditto;
> (MASK_ZVL128B): Ditto;
> (MASK_ZVL256B): Ditto;
> (MASK_ZVL512B): Ditto;
> (MASK_ZVL1024B): Ditto;
> (MASK_ZVL2048B): Ditto;
> (MASK_ZVL4096B): Ditto;
> (MASK_ZVL8192B): Ditto;
> (MASK_ZVL16384B): Ditto;
> (MASK_ZVL32768B): Ditto;
> (MASK_ZVL65536B): Ditto;
> (TARGET_ZVL32B): Ditto;
> (TARGET_ZVL64B): Ditto;
> (TARGET_ZVL128B): Ditto;
> (TARGET_ZVL256B): Ditto;
> (TARGET_ZVL512B): Ditto;
> (TARGET_ZVL1024B): Ditto;
> (TARGET_ZVL2048B): Ditto;
> (TARGET_ZVL4096B): Ditto;
> (TARGET_ZVL8192B): Ditto;
> (TARGET_ZVL16384B): Ditto;
> (TARGET_ZVL32768B): Ditto;
> (TARGET_ZVL65536B): Ditto;
> (MASK_ZICBOZ): Ditto;
> (MASK_ZICBOM): Ditto;
> (MASK_ZICBOP): Ditto;
> (TARGET_ZICBOZ): Ditto;
> (TARGET_ZICBOM): Ditto;
> (TARGET_ZICBOP): Ditto;
> (MASK_ZICOND): Ditto;
> (TARGET_ZICOND): Ditto;
> (MASK_ZFA): Ditto;
> (TARGET_ZFA): Ditto;
> (MASK_ZFHMIN): Ditto;
> (MASK_ZFH): Ditto;
> (MASK_ZVFHMIN): Ditto;
> (MASK_ZVFH): Ditto;
> (TARGET_ZFHMIN): Ditto;
> (TARGET_ZFH): Ditto;
> (TARGET_ZVFHMIN): Ditto;
> (TARGET_ZVFH): Ditto;
> (MASK_ZMMUL): Ditto;
> (TARGET_ZMMUL): Ditto;
> (MASK_ZCA): Ditto;
> (MASK_ZCB): Ditto;
> (MASK_ZCE): Ditto;
> (MASK_ZCF): Ditto;
> (MASK_ZCD): Ditto;
> (MASK_ZCMP): Ditto;
> (MASK_ZCMT): Ditto;
> (TARGET_ZCA): Ditto;
> (TARGET_ZCB): Ditto;
> (TARGET_ZCE): Ditto;
> (TARGET_ZCF): Ditto;
> (TARGET_ZCD): Ditto;
> (TARGET_ZCMP): Ditto;
> (TARGET_ZCMT): Ditto;
> (MASK_SVINVAL): Ditto;
> (MASK_SVNAPOT): Ditto;
> (TARGET_SVINVAL): Ditto;
> (TARGET_SVNAPOT): Ditto;
> (MASK_XTHEADBA): Ditto;
> (MASK_XTHEADBB): Ditto;
> (MASK_XTHEADBS): Ditto;
> (MASK_XTHEADCMO): Ditto;
> (MASK_XTHEADCONDMOV): Ditto;
> (MASK_XTHEADFMEMIDX): Ditto;
> (MASK_XTHEADFMV): Ditto;
> (MASK_XTHEADINT): Ditto;
> (MASK_XTHEADMAC): Ditto;
> (MASK_XTHEADMEMIDX): Ditto;
> (MASK_XTHEADMEMPAIR): Ditto;
> (MASK_XTHEADSYNC): Ditto;
> (TARGET_XTHEADBA): Ditto;
> (TARGET_XTHEADBB): Ditto;
> (TARGET_XTHEADBS): Ditto;
> (TARGET_XTHEADCMO): Ditto;
> (TARGET_XTHEADCONDMOV):Ditto;
> (TARGET_XTHEADFMEMIDX):Ditto;
> (TARGET_XTHEADFMV): Ditto;
> (TARGET_XTHEADINT): Ditto;
> (TARGET_XTHEADMAC): Ditto;
> (TARGET_XTHEADMEMIDX): Ditto;
> (TARGET_XTHEADMEMPAIR):Ditto;
> (TARGET_XTHEADSYNC): Ditto;
> * config/riscv/riscv.opt: Add new Mask defination.
> * doc/options.texi: Add new explanation for the usage.
> * opt-functions.awk: Add new function to find the index
> of target variable from extra_target_vars.
> * opt-read.awk: Add new function to store the Mask flags.
> * opth-gen.awk: Add new function to output the defination of
> Mask Macro and Target Macro.
> ---
> gcc/config/riscv/riscv-opts.h | 212 ----------------------------------
> gcc/config/riscv/riscv.opt | 174 ++++++++++++++++++++++++++++
> gcc/doc/options.texi | 6 +
> gcc/opt-functions.awk | 11 ++
> gcc/opt-read.awk | 16 ++-
> gcc/opth-gen.awk | 22 ++++
> 6 files changed, 228 insertions(+), 213 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 5ed69abd214..07aa3cc83db 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -99,192 +99,6 @@ enum riscv_entity
> MAX_RISCV_ENTITIES
> };
>
> -#define MASK_ZICSR (1 << 0)
> -#define MASK_ZIFENCEI (1 << 1)
> -#define MASK_ZIHINTNTL (1 << 2)
> -#define MASK_ZIHINTPAUSE (1 << 3)
> -
> -#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
> -#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
> -#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
> -#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0)
> -
> -#define MASK_ZAWRS (1 << 0)
> -#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
> -
> -#define MASK_ZBA (1 << 0)
> -#define MASK_ZBB (1 << 1)
> -#define MASK_ZBC (1 << 2)
> -#define MASK_ZBS (1 << 3)
> -
> -#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
> -#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
> -#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
> -#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
> -
> -#define MASK_ZFINX (1 << 0)
> -#define MASK_ZDINX (1 << 1)
> -#define MASK_ZHINX (1 << 2)
> -#define MASK_ZHINXMIN (1 << 3)
> -
> -#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
> -#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
> -#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
> -#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
> -
> -#define MASK_ZBKB (1 << 0)
> -#define MASK_ZBKC (1 << 1)
> -#define MASK_ZBKX (1 << 2)
> -#define MASK_ZKNE (1 << 3)
> -#define MASK_ZKND (1 << 4)
> -#define MASK_ZKNH (1 << 5)
> -#define MASK_ZKR (1 << 6)
> -#define MASK_ZKSED (1 << 7)
> -#define MASK_ZKSH (1 << 8)
> -#define MASK_ZKT (1 << 9)
> -
> -#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
> -#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
> -#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
> -#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
> -#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
> -#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
> -#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
> -#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
> -#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
> -#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
> -
> -#define MASK_ZTSO (1 << 0)
> -
> -#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0)
> -
> -#define MASK_VECTOR_ELEN_32 (1 << 0)
> -#define MASK_VECTOR_ELEN_64 (1 << 1)
> -#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
> -#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
> -/* Align the bit index to riscv-vector-builtins.h. */
> -#define MASK_VECTOR_ELEN_FP_16 (1 << 6)
> -
> -#define TARGET_VECTOR_ELEN_32 \
> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
> -#define TARGET_VECTOR_ELEN_64 \
> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
> -#define TARGET_VECTOR_ELEN_FP_32 \
> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
> -#define TARGET_VECTOR_ELEN_FP_64 \
> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
> -#define TARGET_VECTOR_ELEN_FP_16 \
> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_16) != 0)
> -
> -#define MASK_ZVBB (1 << 0)
> -#define MASK_ZVBC (1 << 1)
> -
> -#define TARGET_ZVBB ((riscv_zvb_subext & MASK_ZVBB) != 0)
> -#define TARGET_ZVBC ((riscv_zvb_subext & MASK_ZVBC) != 0)
> -
> -#define MASK_ZVKG (1 << 0)
> -#define MASK_ZVKNED (1 << 1)
> -#define MASK_ZVKNHA (1 << 2)
> -#define MASK_ZVKNHB (1 << 3)
> -#define MASK_ZVKSED (1 << 4)
> -#define MASK_ZVKSH (1 << 5)
> -#define MASK_ZVKN (1 << 6)
> -#define MASK_ZVKNC (1 << 7)
> -#define MASK_ZVKNG (1 << 8)
> -#define MASK_ZVKS (1 << 9)
> -#define MASK_ZVKSC (1 << 10)
> -#define MASK_ZVKSG (1 << 11)
> -#define MASK_ZVKT (1 << 12)
> -
> -#define TARGET_ZVKG ((riscv_zvk_subext & MASK_ZVKG) != 0)
> -#define TARGET_ZVKNED ((riscv_zvk_subext & MASK_ZVKNED) != 0)
> -#define TARGET_ZVKNHA ((riscv_zvk_subext & MASK_ZVKNHA) != 0)
> -#define TARGET_ZVKNHB ((riscv_zvk_subext & MASK_ZVKNHB) != 0)
> -#define TARGET_ZVKSED ((riscv_zvk_subext & MASK_ZVKSED) != 0)
> -#define TARGET_ZVKSH ((riscv_zvk_subext & MASK_ZVKSH) != 0)
> -#define TARGET_ZVKN ((riscv_zvk_subext & MASK_ZVKN) != 0)
> -#define TARGET_ZVKNC ((riscv_zvk_subext & MASK_ZVKNC) != 0)
> -#define TARGET_ZVKNG ((riscv_zvk_subext & MASK_ZVKNG) != 0)
> -#define TARGET_ZVKS ((riscv_zvk_subext & MASK_ZVKS) != 0)
> -#define TARGET_ZVKSC ((riscv_zvk_subext & MASK_ZVKSC) != 0)
> -#define TARGET_ZVKSG ((riscv_zvk_subext & MASK_ZVKSG) != 0)
> -#define TARGET_ZVKT ((riscv_zvk_subext & MASK_ZVKT) != 0)
> -
> -#define MASK_ZVL32B (1 << 0)
> -#define MASK_ZVL64B (1 << 1)
> -#define MASK_ZVL128B (1 << 2)
> -#define MASK_ZVL256B (1 << 3)
> -#define MASK_ZVL512B (1 << 4)
> -#define MASK_ZVL1024B (1 << 5)
> -#define MASK_ZVL2048B (1 << 6)
> -#define MASK_ZVL4096B (1 << 7)
> -#define MASK_ZVL8192B (1 << 8)
> -#define MASK_ZVL16384B (1 << 9)
> -#define MASK_ZVL32768B (1 << 10)
> -#define MASK_ZVL65536B (1 << 11)
> -
> -#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
> -#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
> -#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
> -#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
> -#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
> -#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
> -#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
> -#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
> -#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
> -#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
> -#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
> -#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
> -
> -#define MASK_ZICBOZ (1 << 0)
> -#define MASK_ZICBOM (1 << 1)
> -#define MASK_ZICBOP (1 << 2)
> -
> -#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
> -#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
> -#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
> -
> -#define MASK_ZICOND (1 << 2)
> -#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0)
> -
> -#define MASK_ZFA (1 << 0)
> -#define TARGET_ZFA ((riscv_zfa_subext & MASK_ZFA) != 0)
> -
> -#define MASK_ZFHMIN (1 << 0)
> -#define MASK_ZFH (1 << 1)
> -#define MASK_ZVFHMIN (1 << 2)
> -#define MASK_ZVFH (1 << 3)
> -
> -#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
> -#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
> -#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
> -#define TARGET_ZVFH ((riscv_zf_subext & MASK_ZVFH) != 0)
> -
> -#define MASK_ZMMUL (1 << 0)
> -#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
> -
> -#define MASK_ZCA (1 << 0)
> -#define MASK_ZCB (1 << 1)
> -#define MASK_ZCE (1 << 2)
> -#define MASK_ZCF (1 << 3)
> -#define MASK_ZCD (1 << 4)
> -#define MASK_ZCMP (1 << 5)
> -#define MASK_ZCMT (1 << 6)
> -
> -#define TARGET_ZCA ((riscv_zc_subext & MASK_ZCA) != 0)
> -#define TARGET_ZCB ((riscv_zc_subext & MASK_ZCB) != 0)
> -#define TARGET_ZCE ((riscv_zc_subext & MASK_ZCE) != 0)
> -#define TARGET_ZCF ((riscv_zc_subext & MASK_ZCF) != 0)
> -#define TARGET_ZCD ((riscv_zc_subext & MASK_ZCD) != 0)
> -#define TARGET_ZCMP ((riscv_zc_subext & MASK_ZCMP) != 0)
> -#define TARGET_ZCMT ((riscv_zc_subext & MASK_ZCMT) != 0)
> -
> -#define MASK_SVINVAL (1 << 0)
> -#define MASK_SVNAPOT (1 << 1)
> -
> -#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
> -#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
> -
> /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
> popcount to caclulate the minimal VLEN. */
> @@ -293,32 +107,6 @@ enum riscv_entity
> ? 0 \
> : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
>
> -#define MASK_XTHEADBA (1 << 0)
> -#define MASK_XTHEADBB (1 << 1)
> -#define MASK_XTHEADBS (1 << 2)
> -#define MASK_XTHEADCMO (1 << 3)
> -#define MASK_XTHEADCONDMOV (1 << 4)
> -#define MASK_XTHEADFMEMIDX (1 << 5)
> -#define MASK_XTHEADFMV (1 << 6)
> -#define MASK_XTHEADINT (1 << 7)
> -#define MASK_XTHEADMAC (1 << 8)
> -#define MASK_XTHEADMEMIDX (1 << 9)
> -#define MASK_XTHEADMEMPAIR (1 << 10)
> -#define MASK_XTHEADSYNC (1 << 11)
> -
> -#define TARGET_XTHEADBA ((riscv_xthead_subext & MASK_XTHEADBA) != 0)
> -#define TARGET_XTHEADBB ((riscv_xthead_subext & MASK_XTHEADBB) != 0)
> -#define TARGET_XTHEADBS ((riscv_xthead_subext & MASK_XTHEADBS) != 0)
> -#define TARGET_XTHEADCMO ((riscv_xthead_subext & MASK_XTHEADCMO) != 0)
> -#define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
> -#define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
> -#define TARGET_XTHEADFMV ((riscv_xthead_subext & MASK_XTHEADFMV) != 0)
> -#define TARGET_XTHEADINT ((riscv_xthead_subext & MASK_XTHEADINT) != 0)
> -#define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
> -#define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
> -#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
> -#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
> -
> /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
> is the highest priority choice and should not conflict with VLS modes. */
> #define TARGET_VECTOR_VLS \
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index d2407c3c502..4570c4b76c2 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -209,54 +209,228 @@ long riscv_stack_protector_guard_offset = 0
> TargetVariable
> int riscv_zi_subext
>
> +Mask(ZICSR) in TargetVariable(riscv_zi_subext)
> +
> +Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)
> +
> +Mask(ZIHINTNTL) in TargetVariable(riscv_zi_subext)
> +
> +Mask(ZIHINTPAUSE) in TargetVariable(riscv_zi_subext)
> +
> +Mask(ZICOND) in TargetVariable(riscv_zi_subext)
> +
> TargetVariable
> int riscv_za_subext
>
> +Mask(ZAWRS) in TargetVariable(riscv_za_subext)
> +
> TargetVariable
> int riscv_zb_subext
>
> +Mask(ZBA) in TargetVariable(riscv_zb_subext)
> +
> +Mask(ZBB) in TargetVariable(riscv_zb_subext)
> +
> +Mask(ZBC) in TargetVariable(riscv_zb_subext)
> +
> +Mask(ZBS) in TargetVariable(riscv_zb_subext)
> +
> TargetVariable
> int riscv_zinx_subext
>
> +Mask(ZFINX) in TargetVariable(riscv_zinx_subext)
> +
> +Mask(ZDINX) in TargetVariable(riscv_zinx_subext)
> +
> +Mask(ZHINX) in TargetVariable(riscv_zinx_subext)
> +
> +Mask(ZHINXMIN) in TargetVariable(riscv_zinx_subext)
> +
> TargetVariable
> int riscv_zk_subext
>
> +Mask(ZBKB) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZBKC) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZBKX) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKNE) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKND) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKNH) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKR) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKSED) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKSH) in TargetVariable(riscv_zk_subext)
> +
> +Mask(ZKT) in TargetVariable(riscv_zk_subext)
> +
> TargetVariable
> int riscv_vector_elen_flags
>
> +Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
> +
> +Mask(VECTOR_ELEN_64) in TargetVariable(riscv_vector_elen_flags)
> +
> +Mask(VECTOR_ELEN_FP_32) in TargetVariable(riscv_vector_elen_flags)
> +
> +Mask(VECTOR_ELEN_FP_64) in TargetVariable(riscv_vector_elen_flags)
> +
> +Mask(VECTOR_ELEN_FP_16) in TargetVariable(riscv_vector_elen_flags)
> +
> TargetVariable
> int riscv_zvl_flags
>
> +Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL128B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL256B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL512B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL1024B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL2048B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL4096B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL8192B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL16384B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL32768B) in TargetVariable(riscv_zvl_flags)
> +
> +Mask(ZVL65536B) in TargetVariable(riscv_zvl_flags)
> +
> TargetVariable
> int riscv_zvb_subext
>
> +Mask(ZVBB) in TargetVariable(riscv_zvb_subext)
> +
> +Mask(ZVBC) in TargetVariable(riscv_zvb_subext)
> +
> TargetVariable
> int riscv_zvk_subext
>
> +Mask(ZVKG) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKNED) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKNHA) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKNHB) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKSED) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKSH) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKN) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKNC) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKNG) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKS) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKSC) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKSG) in TargetVariable(riscv_zvk_subext)
> +
> +Mask(ZVKT) in TargetVariable(riscv_zvk_subext)
> +
> TargetVariable
> int riscv_zicmo_subext
>
> +Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
> +
> +Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
> +
> +Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
> +
> TargetVariable
> int riscv_zf_subext
>
> +Mask(ZFHMIN) in TargetVariable(riscv_zf_subext)
> +
> +Mask(ZFH) in TargetVariable(riscv_zf_subext)
> +
> +Mask(ZVFHMIN) in TargetVariable(riscv_zf_subext)
> +
> +Mask(ZVFH) in TargetVariable(riscv_zf_subext)
> +
> TargetVariable
> int riscv_zfa_subext
>
> +Mask(ZFA) in TargetVariable(riscv_zfa_subext)
> +
> TargetVariable
> int riscv_zm_subext
>
> +Mask(ZMMUL) in TargetVariable(riscv_zm_subext)
> +
> TargetVariable
> int riscv_zc_subext
>
> +Mask(ZCA) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCB) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCE) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCF) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCD) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCMP) in TargetVariable(riscv_zc_subext)
> +
> +Mask(ZCMT) in TargetVariable(riscv_zc_subext)
> +
> TargetVariable
> int riscv_sv_subext
>
> +Mask(SVINVAL) in TargetVariable(riscv_sv_subext)
> +
> +Mask(SVNAPOT) in TargetVariable(riscv_sv_subext)
> +
> TargetVariable
> int riscv_ztso_subext
>
> +Mask(ZTSO) in TargetVariable(riscv_ztso_subext)
> +
> TargetVariable
> int riscv_xthead_subext
>
> +Mask(XTHEADBA) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADBB) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADBS) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADCMO) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADCONDMOV) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADFMEMIDX) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADFMV) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADINT) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADMAC) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADMEMIDX) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADMEMPAIR) in TargetVariable(riscv_xthead_subext)
> +
> +Mask(XTHEADSYNC) in TargetVariable(riscv_xthead_subext)
> +
> Enum
> Name(isa_spec_class) Type(enum riscv_isa_spec_class)
> Supported ISA specs (for use with the -misa-spec= option):
> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
> index f50063c9787..24663d8233e 100644
> --- a/gcc/doc/options.texi
> +++ b/gcc/doc/options.texi
> @@ -409,6 +409,12 @@ the value 1 when the option is active and 0 otherwise. If you use @code{Var}
> to attach the option to a different variable, the bitmask macro with be
> called @code{OPTION_MASK_@var{name}}.
>
> +@item Mask(@var{name}) in TargetVariable(@var{other_target_flags})
> +This method can be used to associate the option with a bit in @samp{other_target_flags}
> +which has been defined,when the option number exceeds the bits of @code{target_flags}.
> +The macro @code{MASK_@var{name}} and The @code{TARGET_@var{name}}
> +will aslo be generated automatically as described above .
> +
> @item InverseMask(@var{othername})
> @itemx InverseMask(@var{othername}, @var{thisname})
> The option is the inverse of another option that has the
> diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
> index 36de4639318..cbfcf7dabcf 100644
> --- a/gcc/opt-functions.awk
> +++ b/gcc/opt-functions.awk
> @@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option, uinteger_used)
> else
> return "-1, -1"
> }
> +
> +# Find the index of target variable from extra_target_vars
> +function find_index(var, var_arry, n_var_arry)
> +{
> + for (var_index = 0; var_index < n_var_arry; var_index++)
> + {
> + if (var_arry[var_index] == var)
> + break
> + }
> + return var_index
> +}
> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
> index fc4e3d77910..0ff2e806373 100644
> --- a/gcc/opt-read.awk
> +++ b/gcc/opt-read.awk
> @@ -22,6 +22,7 @@ BEGIN {
> n_opts = 0
> n_langs = 0
> n_target_save = 0
> + n_target_vars = 0
> n_extra_vars = 0
> n_extra_target_vars = 0
> n_extra_masks = 0
> @@ -121,7 +122,20 @@ BEGIN {
> n_opts++;
> }
> else {
> - extra_masks[n_extra_masks++] = name
> + if($0 ~ "in")
> + {
> + target_var = opt_args("TargetVariable", $1)
> + var_index = find_index(target_var, target_vars, n_target_vars)
> + if (var_index == n_target_vars)
> + {
> + target_vars[n_target_vars++] = target_var
> + }
> + other_masks[var_index][n_other_mask[var_index]++] = name
> + }
> + else
> + {
> + extra_masks[n_extra_masks++] = name
> + }
> }
> }
> }
> diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
> index 71404f9eff6..70ca3d37719 100644
> --- a/gcc/opth-gen.awk
> +++ b/gcc/opth-gen.awk
> @@ -406,6 +406,18 @@ for (i = 0; i < n_extra_masks; i++) {
> print "#define MASK_" extra_masks[i] " (1U << " masknum[""]++ ")"
> }
>
> +for (i = 0; i < n_target_vars; i++)
> +{
> + if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
> + continue
> + for (j = 0; j < n_other_mask[i]; j++)
> + {
> + print "#define MASK_" other_masks[i][j] " (1U << " other_masknum[i][""]++ ")"
> + }
> + if (other_masknum[i][""] > 32)
> + print "#error too many target masks for" extra_target_vars[i]
> +}
> +
> for (var in masknum) {
> if (var != "" && host_wide_int[var] == "yes") {
> print "#if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] " > HOST_BITS_PER_WIDE_INT"
> @@ -419,6 +431,16 @@ for (var in masknum) {
> print "#error too many masks for " var
> }
> }
> +for (i = 0; i < n_target_vars; i++)
> +{
> + if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
> + continue
> + for (j = 0; j < n_other_mask[i]; j++)
> + {
> + print "#define TARGET_" other_masks[i][j] \
> + " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 0)"
> + }
> +}
> print ""
>
> for (i = 0; i < n_opts; i++) {
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PATCH v3] RISC-V:Optimize the MASK opt generation
2023-09-07 0:48 ` Tsukasa OI
@ 2023-09-07 1:17 ` Feng Wang
0 siblings, 0 replies; 7+ messages in thread
From: Feng Wang @ 2023-09-07 1:17 UTC (permalink / raw)
To: research_trasio; +Cc: gcc-patches
Thanks reminder, I should rebase again.
--------------
Feng Wang
>Hi,
>
>I will need to notify you that x_riscv_xventana_subext,
>MASK_XVENTANACONDOPS and TARGET_XVENTANACONDOPS are added (I think you
>want to rewrite those definitions like the rest). Also, be careful not
>to remove TARGET_ZICOND_LIKE.
>
>Thanks,
>Tsukasa
>
>On 2023/09/06 11:02, Feng Wang wrote:
>> This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
>> generation" and add the new explanation in the options.texi.
>> Please check the detail info on the
>> "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html"
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv-opts.h (MASK_ZICSR):
>> (MASK_ZIFENCEI): Delete;
>> (MASK_ZIHINTNTL): Ditto;
>> (MASK_ZIHINTPAUSE): Ditto;
>> (TARGET_ZICSR): Ditto;
>> (TARGET_ZIFENCEI): Ditto;
>> (TARGET_ZIHINTNTL): Ditto;
>> (TARGET_ZIHINTPAUSE):Ditto;
>> (MASK_ZAWRS): Ditto;
>> (TARGET_ZAWRS): Ditto;
>> (MASK_ZBA): Ditto;
>> (MASK_ZBB): Ditto;
>> (MASK_ZBC): Ditto;
>> (MASK_ZBS): Ditto;
>> (TARGET_ZBA): Ditto;
>> (TARGET_ZBB): Ditto;
>> (TARGET_ZBC): Ditto;
>> (TARGET_ZBS): Ditto;
>> (MASK_ZFINX): Ditto;
>> (MASK_ZDINX): Ditto;
>> (MASK_ZHINX): Ditto;
>> (MASK_ZHINXMIN): Ditto;
>> (TARGET_ZFINX): Ditto;
>> (TARGET_ZDINX): Ditto;
>> (TARGET_ZHINX): Ditto;
>> (TARGET_ZHINXMIN): Ditto;
>> (MASK_ZBKB): Ditto;
>> (MASK_ZBKC): Ditto;
>> (MASK_ZBKX): Ditto;
>> (MASK_ZKNE): Ditto;
>> (MASK_ZKND): Ditto;
>> (MASK_ZKNH): Ditto;
>> (MASK_ZKR): Ditto;
>> (MASK_ZKSED): Ditto;
>> (MASK_ZKSH): Ditto;
>> (MASK_ZKT): Ditto;
>> (TARGET_ZBKB): Ditto;
>> (TARGET_ZBKC): Ditto;
>> (TARGET_ZBKX): Ditto;
>> (TARGET_ZKNE): Ditto;
>> (TARGET_ZKND): Ditto;
>> (TARGET_ZKNH): Ditto;
>> (TARGET_ZKR): Ditto;
>> (TARGET_ZKSED): Ditto;
>> (TARGET_ZKSH): Ditto;
>> (TARGET_ZKT): Ditto;
>> (MASK_ZTSO): Ditto;
>> (TARGET_ZTSO): Ditto;
>> (MASK_VECTOR_ELEN_32): Ditto;
>> (MASK_VECTOR_ELEN_64): Ditto;
>> (MASK_VECTOR_ELEN_FP_32):Ditto;
>> (MASK_VECTOR_ELEN_FP_64):Ditto;
>> (MASK_VECTOR_ELEN_FP_16):Ditto;
>> (TARGET_VECTOR_ELEN_32): Ditto;
>> (TARGET_VECTOR_ELEN_64): Ditto;
>> (TARGET_VECTOR_ELEN_FP_32):Ditto;
>> (TARGET_VECTOR_ELEN_FP_64):Ditto;
>> (TARGET_VECTOR_ELEN_FP_16):Ditto;
>> (MASK_ZVBB): Ditto;
>> (MASK_ZVBC): Ditto;
>> (TARGET_ZVBB): Ditto;
>> (TARGET_ZVBC): Ditto;
>> (MASK_ZVKG): Ditto;
>> (MASK_ZVKNED): Ditto;
>> (MASK_ZVKNHA): Ditto;
>> (MASK_ZVKNHB): Ditto;
>> (MASK_ZVKSED): Ditto;
>> (MASK_ZVKSH): Ditto;
>> (MASK_ZVKN): Ditto;
>> (MASK_ZVKNC): Ditto;
>> (MASK_ZVKNG): Ditto;
>> (MASK_ZVKS): Ditto;
>> (MASK_ZVKSC): Ditto;
>> (MASK_ZVKSG): Ditto;
>> (MASK_ZVKT): Ditto;
>> (TARGET_ZVKG): Ditto;
>> (TARGET_ZVKNED): Ditto;
>> (TARGET_ZVKNHA): Ditto;
>> (TARGET_ZVKNHB): Ditto;
>> (TARGET_ZVKSED): Ditto;
>> (TARGET_ZVKSH): Ditto;
>> (TARGET_ZVKN): Ditto;
>> (TARGET_ZVKNC): Ditto;
>> (TARGET_ZVKNG): Ditto;
>> (TARGET_ZVKS): Ditto;
>> (TARGET_ZVKSC): Ditto;
>> (TARGET_ZVKSG): Ditto;
>> (TARGET_ZVKT): Ditto;
>> (MASK_ZVL32B): Ditto;
>> (MASK_ZVL64B): Ditto;
>> (MASK_ZVL128B): Ditto;
>> (MASK_ZVL256B): Ditto;
>> (MASK_ZVL512B): Ditto;
>> (MASK_ZVL1024B): Ditto;
>> (MASK_ZVL2048B): Ditto;
>> (MASK_ZVL4096B): Ditto;
>> (MASK_ZVL8192B): Ditto;
>> (MASK_ZVL16384B): Ditto;
>> (MASK_ZVL32768B): Ditto;
>> (MASK_ZVL65536B): Ditto;
>> (TARGET_ZVL32B): Ditto;
>> (TARGET_ZVL64B): Ditto;
>> (TARGET_ZVL128B): Ditto;
>> (TARGET_ZVL256B): Ditto;
>> (TARGET_ZVL512B): Ditto;
>> (TARGET_ZVL1024B): Ditto;
>> (TARGET_ZVL2048B): Ditto;
>> (TARGET_ZVL4096B): Ditto;
>> (TARGET_ZVL8192B): Ditto;
>> (TARGET_ZVL16384B): Ditto;
>> (TARGET_ZVL32768B): Ditto;
>> (TARGET_ZVL65536B): Ditto;
>> (MASK_ZICBOZ): Ditto;
>> (MASK_ZICBOM): Ditto;
>> (MASK_ZICBOP): Ditto;
>> (TARGET_ZICBOZ): Ditto;
>> (TARGET_ZICBOM): Ditto;
>> (TARGET_ZICBOP): Ditto;
>> (MASK_ZICOND): Ditto;
>> (TARGET_ZICOND): Ditto;
>> (MASK_ZFA): Ditto;
>> (TARGET_ZFA): Ditto;
>> (MASK_ZFHMIN): Ditto;
>> (MASK_ZFH): Ditto;
>> (MASK_ZVFHMIN): Ditto;
>> (MASK_ZVFH): Ditto;
>> (TARGET_ZFHMIN): Ditto;
>> (TARGET_ZFH): Ditto;
>> (TARGET_ZVFHMIN): Ditto;
>> (TARGET_ZVFH): Ditto;
>> (MASK_ZMMUL): Ditto;
>> (TARGET_ZMMUL): Ditto;
>> (MASK_ZCA): Ditto;
>> (MASK_ZCB): Ditto;
>> (MASK_ZCE): Ditto;
>> (MASK_ZCF): Ditto;
>> (MASK_ZCD): Ditto;
>> (MASK_ZCMP): Ditto;
>> (MASK_ZCMT): Ditto;
>> (TARGET_ZCA): Ditto;
>> (TARGET_ZCB): Ditto;
>> (TARGET_ZCE): Ditto;
>> (TARGET_ZCF): Ditto;
>> (TARGET_ZCD): Ditto;
>> (TARGET_ZCMP): Ditto;
>> (TARGET_ZCMT): Ditto;
>> (MASK_SVINVAL): Ditto;
>> (MASK_SVNAPOT): Ditto;
>> (TARGET_SVINVAL): Ditto;
>> (TARGET_SVNAPOT): Ditto;
>> (MASK_XTHEADBA): Ditto;
>> (MASK_XTHEADBB): Ditto;
>> (MASK_XTHEADBS): Ditto;
>> (MASK_XTHEADCMO): Ditto;
>> (MASK_XTHEADCONDMOV): Ditto;
>> (MASK_XTHEADFMEMIDX): Ditto;
>> (MASK_XTHEADFMV): Ditto;
>> (MASK_XTHEADINT): Ditto;
>> (MASK_XTHEADMAC): Ditto;
>> (MASK_XTHEADMEMIDX): Ditto;
>> (MASK_XTHEADMEMPAIR): Ditto;
>> (MASK_XTHEADSYNC): Ditto;
>> (TARGET_XTHEADBA): Ditto;
>> (TARGET_XTHEADBB): Ditto;
>> (TARGET_XTHEADBS): Ditto;
>> (TARGET_XTHEADCMO): Ditto;
>> (TARGET_XTHEADCONDMOV):Ditto;
>> (TARGET_XTHEADFMEMIDX):Ditto;
>> (TARGET_XTHEADFMV): Ditto;
>> (TARGET_XTHEADINT): Ditto;
>> (TARGET_XTHEADMAC): Ditto;
>> (TARGET_XTHEADMEMIDX): Ditto;
>> (TARGET_XTHEADMEMPAIR):Ditto;
>> (TARGET_XTHEADSYNC): Ditto;
>> * config/riscv/riscv.opt: Add new Mask defination.
>> * doc/options.texi: Add new explanation for the usage.
>> * opt-functions.awk: Add new function to find the index
>> of target variable from extra_target_vars.
>> * opt-read.awk: Add new function to store the Mask flags.
>> * opth-gen.awk: Add new function to output the defination of
>> Mask Macro and Target Macro.
>> ---
>> gcc/config/riscv/riscv-opts.h | 212 ----------------------------------
>> gcc/config/riscv/riscv.opt | 174 ++++++++++++++++++++++++++++
>> gcc/doc/options.texi | 6 +
>> gcc/opt-functions.awk | 11 ++
>> gcc/opt-read.awk | 16 ++-
>> gcc/opth-gen.awk | 22 ++++
>> 6 files changed, 228 insertions(+), 213 deletions(-)
>>
>> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
>> index 5ed69abd214..07aa3cc83db 100644
>> --- a/gcc/config/riscv/riscv-opts.h
>> +++ b/gcc/config/riscv/riscv-opts.h
>> @@ -99,192 +99,6 @@ enum riscv_entity
>> MAX_RISCV_ENTITIES
>> };
>>
>> -#define MASK_ZICSR (1 << 0)
>> -#define MASK_ZIFENCEI (1 << 1)
>> -#define MASK_ZIHINTNTL (1 << 2)
>> -#define MASK_ZIHINTPAUSE (1 << 3)
>> -
>> -#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
>> -#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
>> -#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
>> -#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0)
>> -
>> -#define MASK_ZAWRS (1 << 0)
>> -#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
>> -
>> -#define MASK_ZBA (1 << 0)
>> -#define MASK_ZBB (1 << 1)
>> -#define MASK_ZBC (1 << 2)
>> -#define MASK_ZBS (1 << 3)
>> -
>> -#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
>> -#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
>> -#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
>> -#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
>> -
>> -#define MASK_ZFINX (1 << 0)
>> -#define MASK_ZDINX (1 << 1)
>> -#define MASK_ZHINX (1 << 2)
>> -#define MASK_ZHINXMIN (1 << 3)
>> -
>> -#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
>> -#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
>> -#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
>> -#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
>> -
>> -#define MASK_ZBKB (1 << 0)
>> -#define MASK_ZBKC (1 << 1)
>> -#define MASK_ZBKX (1 << 2)
>> -#define MASK_ZKNE (1 << 3)
>> -#define MASK_ZKND (1 << 4)
>> -#define MASK_ZKNH (1 << 5)
>> -#define MASK_ZKR (1 << 6)
>> -#define MASK_ZKSED (1 << 7)
>> -#define MASK_ZKSH (1 << 8)
>> -#define MASK_ZKT (1 << 9)
>> -
>> -#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
>> -#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
>> -#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
>> -#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
>> -#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
>> -#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
>> -#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
>> -#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
>> -#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
>> -#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
>> -
>> -#define MASK_ZTSO (1 << 0)
>> -
>> -#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0)
>> -
>> -#define MASK_VECTOR_ELEN_32 (1 << 0)
>> -#define MASK_VECTOR_ELEN_64 (1 << 1)
>> -#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
>> -#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
>> -/* Align the bit index to riscv-vector-builtins.h. */
>> -#define MASK_VECTOR_ELEN_FP_16 (1 << 6)
>> -
>> -#define TARGET_VECTOR_ELEN_32 \
>> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
>> -#define TARGET_VECTOR_ELEN_64 \
>> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
>> -#define TARGET_VECTOR_ELEN_FP_32 \
>> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
>> -#define TARGET_VECTOR_ELEN_FP_64 \
>> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
>> -#define TARGET_VECTOR_ELEN_FP_16 \
>> - ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_16) != 0)
>> -
>> -#define MASK_ZVBB (1 << 0)
>> -#define MASK_ZVBC (1 << 1)
>> -
>> -#define TARGET_ZVBB ((riscv_zvb_subext & MASK_ZVBB) != 0)
>> -#define TARGET_ZVBC ((riscv_zvb_subext & MASK_ZVBC) != 0)
>> -
>> -#define MASK_ZVKG (1 << 0)
>> -#define MASK_ZVKNED (1 << 1)
>> -#define MASK_ZVKNHA (1 << 2)
>> -#define MASK_ZVKNHB (1 << 3)
>> -#define MASK_ZVKSED (1 << 4)
>> -#define MASK_ZVKSH (1 << 5)
>> -#define MASK_ZVKN (1 << 6)
>> -#define MASK_ZVKNC (1 << 7)
>> -#define MASK_ZVKNG (1 << 8)
>> -#define MASK_ZVKS (1 << 9)
>> -#define MASK_ZVKSC (1 << 10)
>> -#define MASK_ZVKSG (1 << 11)
>> -#define MASK_ZVKT (1 << 12)
>> -
>> -#define TARGET_ZVKG ((riscv_zvk_subext & MASK_ZVKG) != 0)
>> -#define TARGET_ZVKNED ((riscv_zvk_subext & MASK_ZVKNED) != 0)
>> -#define TARGET_ZVKNHA ((riscv_zvk_subext & MASK_ZVKNHA) != 0)
>> -#define TARGET_ZVKNHB ((riscv_zvk_subext & MASK_ZVKNHB) != 0)
>> -#define TARGET_ZVKSED ((riscv_zvk_subext & MASK_ZVKSED) != 0)
>> -#define TARGET_ZVKSH ((riscv_zvk_subext & MASK_ZVKSH) != 0)
>> -#define TARGET_ZVKN ((riscv_zvk_subext & MASK_ZVKN) != 0)
>> -#define TARGET_ZVKNC ((riscv_zvk_subext & MASK_ZVKNC) != 0)
>> -#define TARGET_ZVKNG ((riscv_zvk_subext & MASK_ZVKNG) != 0)
>> -#define TARGET_ZVKS ((riscv_zvk_subext & MASK_ZVKS) != 0)
>> -#define TARGET_ZVKSC ((riscv_zvk_subext & MASK_ZVKSC) != 0)
>> -#define TARGET_ZVKSG ((riscv_zvk_subext & MASK_ZVKSG) != 0)
>> -#define TARGET_ZVKT ((riscv_zvk_subext & MASK_ZVKT) != 0)
>> -
>> -#define MASK_ZVL32B (1 << 0)
>> -#define MASK_ZVL64B (1 << 1)
>> -#define MASK_ZVL128B (1 << 2)
>> -#define MASK_ZVL256B (1 << 3)
>> -#define MASK_ZVL512B (1 << 4)
>> -#define MASK_ZVL1024B (1 << 5)
>> -#define MASK_ZVL2048B (1 << 6)
>> -#define MASK_ZVL4096B (1 << 7)
>> -#define MASK_ZVL8192B (1 << 8)
>> -#define MASK_ZVL16384B (1 << 9)
>> -#define MASK_ZVL32768B (1 << 10)
>> -#define MASK_ZVL65536B (1 << 11)
>> -
>> -#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
>> -#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
>> -#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
>> -#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
>> -#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
>> -#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
>> -#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
>> -#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
>> -#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
>> -#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
>> -#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
>> -#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
>> -
>> -#define MASK_ZICBOZ (1 << 0)
>> -#define MASK_ZICBOM (1 << 1)
>> -#define MASK_ZICBOP (1 << 2)
>> -
>> -#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
>> -#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
>> -#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
>> -
>> -#define MASK_ZICOND (1 << 2)
>> -#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0)
>> -
>> -#define MASK_ZFA (1 << 0)
>> -#define TARGET_ZFA ((riscv_zfa_subext & MASK_ZFA) != 0)
>> -
>> -#define MASK_ZFHMIN (1 << 0)
>> -#define MASK_ZFH (1 << 1)
>> -#define MASK_ZVFHMIN (1 << 2)
>> -#define MASK_ZVFH (1 << 3)
>> -
>> -#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
>> -#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
>> -#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
>> -#define TARGET_ZVFH ((riscv_zf_subext & MASK_ZVFH) != 0)
>> -
>> -#define MASK_ZMMUL (1 << 0)
>> -#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
>> -
>> -#define MASK_ZCA (1 << 0)
>> -#define MASK_ZCB (1 << 1)
>> -#define MASK_ZCE (1 << 2)
>> -#define MASK_ZCF (1 << 3)
>> -#define MASK_ZCD (1 << 4)
>> -#define MASK_ZCMP (1 << 5)
>> -#define MASK_ZCMT (1 << 6)
>> -
>> -#define TARGET_ZCA ((riscv_zc_subext & MASK_ZCA) != 0)
>> -#define TARGET_ZCB ((riscv_zc_subext & MASK_ZCB) != 0)
>> -#define TARGET_ZCE ((riscv_zc_subext & MASK_ZCE) != 0)
>> -#define TARGET_ZCF ((riscv_zc_subext & MASK_ZCF) != 0)
>> -#define TARGET_ZCD ((riscv_zc_subext & MASK_ZCD) != 0)
>> -#define TARGET_ZCMP ((riscv_zc_subext & MASK_ZCMP) != 0)
>> -#define TARGET_ZCMT ((riscv_zc_subext & MASK_ZCMT) != 0)
>> -
>> -#define MASK_SVINVAL (1 << 0)
>> -#define MASK_SVNAPOT (1 << 1)
>> -
>> -#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
>> -#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
>> -
>> /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
>> set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
>> popcount to caclulate the minimal VLEN. */
>> @@ -293,32 +107,6 @@ enum riscv_entity
>> ? 0 \
>> : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
>>
>> -#define MASK_XTHEADBA (1 << 0)
>> -#define MASK_XTHEADBB (1 << 1)
>> -#define MASK_XTHEADBS (1 << 2)
>> -#define MASK_XTHEADCMO (1 << 3)
>> -#define MASK_XTHEADCONDMOV (1 << 4)
>> -#define MASK_XTHEADFMEMIDX (1 << 5)
>> -#define MASK_XTHEADFMV (1 << 6)
>> -#define MASK_XTHEADINT (1 << 7)
>> -#define MASK_XTHEADMAC (1 << 8)
>> -#define MASK_XTHEADMEMIDX (1 << 9)
>> -#define MASK_XTHEADMEMPAIR (1 << 10)
>> -#define MASK_XTHEADSYNC (1 << 11)
>> -
>> -#define TARGET_XTHEADBA ((riscv_xthead_subext & MASK_XTHEADBA) != 0)
>> -#define TARGET_XTHEADBB ((riscv_xthead_subext & MASK_XTHEADBB) != 0)
>> -#define TARGET_XTHEADBS ((riscv_xthead_subext & MASK_XTHEADBS) != 0)
>> -#define TARGET_XTHEADCMO ((riscv_xthead_subext & MASK_XTHEADCMO) != 0)
>> -#define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
>> -#define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
>> -#define TARGET_XTHEADFMV ((riscv_xthead_subext & MASK_XTHEADFMV) != 0)
>> -#define TARGET_XTHEADINT ((riscv_xthead_subext & MASK_XTHEADINT) != 0)
>> -#define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
>> -#define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
>> -#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
>> -#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
>> -
>> /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
>> is the highest priority choice and should not conflict with VLS modes. */
>> #define TARGET_VECTOR_VLS \
>> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
>> index d2407c3c502..4570c4b76c2 100644
>> --- a/gcc/config/riscv/riscv.opt
>> +++ b/gcc/config/riscv/riscv.opt
>> @@ -209,54 +209,228 @@ long riscv_stack_protector_guard_offset = 0
>> TargetVariable
>> int riscv_zi_subext
>>
>> +Mask(ZICSR) in TargetVariable(riscv_zi_subext)
>> +
>> +Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)
>> +
>> +Mask(ZIHINTNTL) in TargetVariable(riscv_zi_subext)
>> +
>> +Mask(ZIHINTPAUSE) in TargetVariable(riscv_zi_subext)
>> +
>> +Mask(ZICOND) in TargetVariable(riscv_zi_subext)
>> +
>> TargetVariable
>> int riscv_za_subext
>>
>> +Mask(ZAWRS) in TargetVariable(riscv_za_subext)
>> +
>> TargetVariable
>> int riscv_zb_subext
>>
>> +Mask(ZBA) in TargetVariable(riscv_zb_subext)
>> +
>> +Mask(ZBB) in TargetVariable(riscv_zb_subext)
>> +
>> +Mask(ZBC) in TargetVariable(riscv_zb_subext)
>> +
>> +Mask(ZBS) in TargetVariable(riscv_zb_subext)
>> +
>> TargetVariable
>> int riscv_zinx_subext
>>
>> +Mask(ZFINX) in TargetVariable(riscv_zinx_subext)
>> +
>> +Mask(ZDINX) in TargetVariable(riscv_zinx_subext)
>> +
>> +Mask(ZHINX) in TargetVariable(riscv_zinx_subext)
>> +
>> +Mask(ZHINXMIN) in TargetVariable(riscv_zinx_subext)
>> +
>> TargetVariable
>> int riscv_zk_subext
>>
>> +Mask(ZBKB) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZBKC) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZBKX) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKNE) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKND) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKNH) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKR) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKSED) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKSH) in TargetVariable(riscv_zk_subext)
>> +
>> +Mask(ZKT) in TargetVariable(riscv_zk_subext)
>> +
>> TargetVariable
>> int riscv_vector_elen_flags
>>
>> +Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
>> +
>> +Mask(VECTOR_ELEN_64) in TargetVariable(riscv_vector_elen_flags)
>> +
>> +Mask(VECTOR_ELEN_FP_32) in TargetVariable(riscv_vector_elen_flags)
>> +
>> +Mask(VECTOR_ELEN_FP_64) in TargetVariable(riscv_vector_elen_flags)
>> +
>> +Mask(VECTOR_ELEN_FP_16) in TargetVariable(riscv_vector_elen_flags)
>> +
>> TargetVariable
>> int riscv_zvl_flags
>>
>> +Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL128B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL256B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL512B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL1024B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL2048B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL4096B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL8192B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL16384B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL32768B) in TargetVariable(riscv_zvl_flags)
>> +
>> +Mask(ZVL65536B) in TargetVariable(riscv_zvl_flags)
>> +
>> TargetVariable
>> int riscv_zvb_subext
>>
>> +Mask(ZVBB) in TargetVariable(riscv_zvb_subext)
>> +
>> +Mask(ZVBC) in TargetVariable(riscv_zvb_subext)
>> +
>> TargetVariable
>> int riscv_zvk_subext
>>
>> +Mask(ZVKG) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKNED) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKNHA) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKNHB) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKSED) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKSH) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKN) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKNC) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKNG) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKS) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKSC) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKSG) in TargetVariable(riscv_zvk_subext)
>> +
>> +Mask(ZVKT) in TargetVariable(riscv_zvk_subext)
>> +
>> TargetVariable
>> int riscv_zicmo_subext
>>
>> +Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
>> +
>> +Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
>> +
>> +Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
>> +
>> TargetVariable
>> int riscv_zf_subext
>>
>> +Mask(ZFHMIN) in TargetVariable(riscv_zf_subext)
>> +
>> +Mask(ZFH) in TargetVariable(riscv_zf_subext)
>> +
>> +Mask(ZVFHMIN) in TargetVariable(riscv_zf_subext)
>> +
>> +Mask(ZVFH) in TargetVariable(riscv_zf_subext)
>> +
>> TargetVariable
>> int riscv_zfa_subext
>>
>> +Mask(ZFA) in TargetVariable(riscv_zfa_subext)
>> +
>> TargetVariable
>> int riscv_zm_subext
>>
>> +Mask(ZMMUL) in TargetVariable(riscv_zm_subext)
>> +
>> TargetVariable
>> int riscv_zc_subext
>>
>> +Mask(ZCA) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCB) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCE) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCF) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCD) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCMP) in TargetVariable(riscv_zc_subext)
>> +
>> +Mask(ZCMT) in TargetVariable(riscv_zc_subext)
>> +
>> TargetVariable
>> int riscv_sv_subext
>>
>> +Mask(SVINVAL) in TargetVariable(riscv_sv_subext)
>> +
>> +Mask(SVNAPOT) in TargetVariable(riscv_sv_subext)
>> +
>> TargetVariable
>> int riscv_ztso_subext
>>
>> +Mask(ZTSO) in TargetVariable(riscv_ztso_subext)
>> +
>> TargetVariable
>> int riscv_xthead_subext
>>
>> +Mask(XTHEADBA) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADBB) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADBS) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADCMO) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADCONDMOV) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADFMEMIDX) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADFMV) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADINT) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADMAC) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADMEMIDX) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADMEMPAIR) in TargetVariable(riscv_xthead_subext)
>> +
>> +Mask(XTHEADSYNC) in TargetVariable(riscv_xthead_subext)
>> +
>> Enum
>> Name(isa_spec_class) Type(enum riscv_isa_spec_class)
>> Supported ISA specs (for use with the -misa-spec= option):
>> diff --git a/gcc/doc/options.texi b/gcc/doc/options.texi
>> index f50063c9787..24663d8233e 100644
>> --- a/gcc/doc/options.texi
>> +++ b/gcc/doc/options.texi
>> @@ -409,6 +409,12 @@ the value 1 when the option is active and 0 otherwise. If you use @code{Var}
>> to attach the option to a different variable, the bitmask macro with be
>> called @code{OPTION_MASK_@var{name}}.
>>
>> +@item Mask(@var{name}) in TargetVariable(@var{other_target_flags})
>> +This method can be used to associate the option with a bit in @samp{other_target_flags}
>> +which has been defined,when the option number exceeds the bits of @code{target_flags}.
>> +The macro @code{MASK_@var{name}} and The @code{TARGET_@var{name}}
>> +will aslo be generated automatically as described above .
>> +
>> @item InverseMask(@var{othername})
>> @itemx InverseMask(@var{othername}, @var{thisname})
>> The option is the inverse of another option that has the
>> diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
>> index 36de4639318..cbfcf7dabcf 100644
>> --- a/gcc/opt-functions.awk
>> +++ b/gcc/opt-functions.awk
>> @@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option, uinteger_used)
>> else
>> return "-1, -1"
>> }
>> +
>> +# Find the index of target variable from extra_target_vars
>> +function find_index(var, var_arry, n_var_arry)
>> +{
>> + for (var_index = 0; var_index < n_var_arry; var_index++)
>> + {
>> + if (var_arry[var_index] == var)
>> + break
>> + }
>> + return var_index
>> +}
>> diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
>> index fc4e3d77910..0ff2e806373 100644
>> --- a/gcc/opt-read.awk
>> +++ b/gcc/opt-read.awk
>> @@ -22,6 +22,7 @@ BEGIN {
>> n_opts = 0
>> n_langs = 0
>> n_target_save = 0
>> + n_target_vars = 0
>> n_extra_vars = 0
>> n_extra_target_vars = 0
>> n_extra_masks = 0
>> @@ -121,7 +122,20 @@ BEGIN {
>> n_opts++;
>> }
>> else {
>> - extra_masks[n_extra_masks++] = name
>> + if($0 ~ "in")
>> + {
>> + target_var = opt_args("TargetVariable", $1)
>> + var_index = find_index(target_var, target_vars, n_target_vars)
>> + if (var_index == n_target_vars)
>> + {
>> + target_vars[n_target_vars++] = target_var
>> + }
>> + other_masks[var_index][n_other_mask[var_index]++] = name
>> + }
>> + else
>> + {
>> + extra_masks[n_extra_masks++] = name
>> + }
>> }
>> }
>> }
>> diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
>> index 71404f9eff6..70ca3d37719 100644
>> --- a/gcc/opth-gen.awk
>> +++ b/gcc/opth-gen.awk
>> @@ -406,6 +406,18 @@ for (i = 0; i < n_extra_masks; i++) {
>> print "#define MASK_" extra_masks[i] " (1U << " masknum[""]++ ")"
>> }
>>
>> +for (i = 0; i < n_target_vars; i++)
>> +{
>> + if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
>> + continue
>> + for (j = 0; j < n_other_mask[i]; j++)
>> + {
>> + print "#define MASK_" other_masks[i][j] " (1U << " other_masknum[i][""]++ ")"
>> + }
>> + if (other_masknum[i][""] > 32)
>> + print "#error too many target masks for" extra_target_vars[i]
>> +}
>> +
>> for (var in masknum) {
>> if (var != "" && host_wide_int[var] == "yes") {
>> print "#if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] " > HOST_BITS_PER_WIDE_INT"
>> @@ -419,6 +431,16 @@ for (var in masknum) {
>> print "#error too many masks for " var
>> }
>> }
>> +for (i = 0; i < n_target_vars; i++)
>> +{
>> + if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
>> + continue
>> + for (j = 0; j < n_other_mask[i]; j++)
>> + {
>> + print "#define TARGET_" other_masks[i][j] \
>> + " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 0)"
>> + }
>> +}
>> print ""
>>
>> for (i = 0; i < n_opts; i++) {
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: Re: [PATCH v3] RISC-V:Optimize the MASK opt generation
2023-10-03 2:38 ` Kito Cheng
@ 2023-10-07 1:00 ` Feng Wang
0 siblings, 0 replies; 7+ messages in thread
From: Feng Wang @ 2023-10-07 1:00 UTC (permalink / raw)
To: kito.cheng, Jeff Law; +Cc: David Edelsohn, gcc-patches
Hi, Kito & Jeff
Due to National Day reasons, I was unable to reply to the email in a timely manner.
Thank you for making the necessary changes to this patch. For the introduction of this bug,
I will also carefully summarize my experience and lessons to avoid the recurrence of such problems.
Thank you again!
--------------
Feng Wang
>Proposed fix, and verified with "mawk" and "gawk -P" (gawk with posix
>mode) on my linux also some other report it work on freebsd, just wait
>review :)
>
>https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631785.html
>
>On Tue, Oct 3, 2023 at 2:07 AM Jeff Law <jeffreyalaw@gmail.com> wrote:
>>
>>
>>
>> On 10/2/23 12:03, David Edelsohn wrote:
>> > On Mon, Oct 2, 2023 at 1:59 PM Jeff Law <jeffreyalaw@gmail.com
>> > <mailto:jeffreyalaw@gmail.com>> wrote:
>> >
>> >
>> >
>> > On 10/2/23 11:20, David Edelsohn wrote:
>> > > Wang,
>> > >
>> > > The AWK portions of this patch broke bootstrap on AIX.
>> > >
>> > > Also, the AWK portions are common code, not RISC-V specific. I
>> > don't
>> > > see anywhere that the common portions of the patch were reviewed or
>> > > approved by anyone with authority to approve the changes to the
>> > AWK files.
>> > >
>> > > This patch should not have been committed without approval by a
>> > reviewer
>> > > with authority for that portion of the compiler and should have been
>> > > tested on targets other than RISC-V if common parts of the
>> > compiler were
>> > > changed.
>> > I acked the generic bits. So the lack of testing on another target is
>> > on me.
>> >
>> >
>> > Hi, Jeff
>> >
>> > Sorry. I didn't see a comment from a global reviewer in the V3 thread.
>> NP.
>>
>> >
>> > I am using Gawk on AIX. After the change, I see a parse error from
>> > gawk. I'm rebuilding with a checkout just before the change to confirm
>> > that it was the source of the error, and it seems to be past that
>> > failure location. I didn't keep the exact error. Once I get past this
>> > build cycle, I'll reproduce it.
>> I think there's already a patch circulating which fixes this. It broke
>> at least one other platform. Hopefully it'll all be sorted out today.
>>
>>
>> jeff
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-10-07 1:00 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-06 2:02 [PATCH v3] RISC-V:Optimize the MASK opt generation Feng Wang
2023-09-06 3:42 ` Kito Cheng
2023-09-06 6:38 ` Feng Wang
2023-09-06 7:19 ` Kito Cheng
2023-09-07 0:48 ` Tsukasa OI
2023-09-07 1:17 ` Feng Wang
2023-10-02 17:20 David Edelsohn
2023-10-02 17:58 ` Jeff Law
2023-10-02 18:03 ` David Edelsohn
2023-10-02 18:06 ` Jeff Law
2023-10-03 2:38 ` Kito Cheng
2023-10-07 1:00 ` Feng Wang
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