From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 52E8B3858D37 for ; Mon, 11 Sep 2023 03:45:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 52E8B3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.10.130.252]) by gateway (Coremail) with SMTP id _____8Ax1fBZjf5k20QkAA--.5582S3; Mon, 11 Sep 2023 11:45:29 +0800 (CST) Received: from slurm-master.loongson.cn (unknown [10.10.130.252]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Dx_yNXjf5kzKZ2AA--.44820S4; Mon, 11 Sep 2023 11:45:27 +0800 (CST) From: Xiaolong Chen To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn, Xiaolong Chen Subject: [PATCH v3 0/9] Added support for SX/LSX vector instructions. Date: Mon, 11 Sep 2023 11:44:30 +0800 Message-Id: <20230911034439.8266-1-chenxiaolong@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:AQAAf8Dx_yNXjf5kzKZ2AA--.44820S4 X-CM-SenderInfo: hfkh05xldrz0tqj6z05rqj20fqof0/1tbiAQAJBWT78LYASQACsf X-Coremail-Antispam: 1Uk129KBj9fXoW3tr15uF4rAFWrKF4xZFWkuFX_yoW8JryrWo WkAF15KwnrGr4SgryUKrn3Xry8Kw1SyrsY9a9rurn8CF45Cr1jyF9Fkw1jvry3ZrsIqr15 Gr90gayDJrZIq3srl-sFpf9Il3svdjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUY17kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUGVWUXwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280 aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aV CY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxU25EfUUUUU X-Spam-Status: No, score=-6.0 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: v2 -> v3: Standardize the code using the GNU format. In order to better test the function of the vector instruction, the 128 and 256 bit test cases are further split according to the function of the instruction. Xiaolong Chen (9): LoongArch: Add tests of -mstrict-align option. LoongArch: Add testsuite framework for Loongson SX/ASX. LoongArch: Add tests for Loongson SX builtin functions. LoongArch:Added support for SX vector floating-point instructions. LoongArch:Add SX instructions for vector arithmetic addition operations. LoongArch:Add vector subtraction arithmetic operation SX instruction. LoongArch:Add vector arithmetic addition vsadd instruction. LoongArch:Added SX vector arithmetic multiplication instruction. LoongArch:Add SX instructions for vector arithmetic operations other than multiplication, addition, and subtraction. .../gcc.target/loongarch/strict-align.c | 12 + .../loongarch/vector/loongarch-vector.exp | 42 + .../loongarch/vector/lsx/lsx-builtin.c | 5038 +++++++++++++++++ .../loongarch/vector/lsx/lsx-vadd.c | 416 ++ .../loongarch/vector/lsx/lsx-vadda.c | 344 ++ .../loongarch/vector/lsx/lsx-vaddi.c | 251 + .../loongarch/vector/lsx/lsx-vaddwev-1.c | 335 ++ .../loongarch/vector/lsx/lsx-vaddwev-2.c | 344 ++ .../loongarch/vector/lsx/lsx-vaddwev-3.c | 425 ++ .../loongarch/vector/lsx/lsx-vaddwod-1.c | 408 ++ .../loongarch/vector/lsx/lsx-vaddwod-2.c | 344 ++ .../loongarch/vector/lsx/lsx-vaddwod-3.c | 237 + .../loongarch/vector/lsx/lsx-vavg-1.c | 398 ++ .../loongarch/vector/lsx/lsx-vavg-2.c | 308 + .../loongarch/vector/lsx/lsx-vavgr-1.c | 299 + .../loongarch/vector/lsx/lsx-vavgr-2.c | 317 ++ .../loongarch/vector/lsx/lsx-vdiv-1.c | 299 + .../loongarch/vector/lsx/lsx-vdiv-2.c | 254 + .../loongarch/vector/lsx/lsx-vexth-1.c | 342 ++ .../loongarch/vector/lsx/lsx-vexth-2.c | 182 + .../loongarch/vector/lsx/lsx-vfcvt-1.c | 398 ++ .../loongarch/vector/lsx/lsx-vfcvt-2.c | 278 + .../loongarch/vector/lsx/lsx-vffint-1.c | 161 + .../loongarch/vector/lsx/lsx-vffint-2.c | 264 + .../loongarch/vector/lsx/lsx-vffint-3.c | 102 + .../loongarch/vector/lsx/lsx-vfrint_d.c | 230 + .../loongarch/vector/lsx/lsx-vfrint_s.c | 350 ++ .../loongarch/vector/lsx/lsx-vftint-1.c | 349 ++ .../loongarch/vector/lsx/lsx-vftint-2.c | 695 +++ .../loongarch/vector/lsx/lsx-vftint-3.c | 1028 ++++ .../loongarch/vector/lsx/lsx-vftint-4.c | 345 ++ .../loongarch/vector/lsx/lsx-vhaddw-1.c | 488 ++ .../loongarch/vector/lsx/lsx-vhaddw-2.c | 452 ++ .../loongarch/vector/lsx/lsx-vhsubw-1.c | 327 ++ .../loongarch/vector/lsx/lsx-vhsubw-2.c | 353 ++ .../loongarch/vector/lsx/lsx-vldi.c | 61 + .../loongarch/vector/lsx/lsx-vmadd.c | 450 ++ .../loongarch/vector/lsx/lsx-vmaddwev-1.c | 472 ++ .../loongarch/vector/lsx/lsx-vmaddwev-2.c | 383 ++ .../loongarch/vector/lsx/lsx-vmaddwev-3.c | 383 ++ .../loongarch/vector/lsx/lsx-vmaddwod-1.c | 372 ++ .../loongarch/vector/lsx/lsx-vmaddwod-2.c | 438 ++ .../loongarch/vector/lsx/lsx-vmaddwod-3.c | 460 ++ .../loongarch/vector/lsx/lsx-vmax-1.c | 317 ++ .../loongarch/vector/lsx/lsx-vmax-2.c | 362 ++ .../loongarch/vector/lsx/lsx-vmaxi-1.c | 279 + .../loongarch/vector/lsx/lsx-vmaxi-2.c | 223 + .../loongarch/vector/lsx/lsx-vmin-1.c | 434 ++ .../loongarch/vector/lsx/lsx-vmin-2.c | 344 ++ .../loongarch/vector/lsx/lsx-vmini-1.c | 314 + .../loongarch/vector/lsx/lsx-vmini-2.c | 216 + .../loongarch/vector/lsx/lsx-vmskgez.c | 119 + .../loongarch/vector/lsx/lsx-vmskltz.c | 321 ++ .../loongarch/vector/lsx/lsx-vmsknz.c | 104 + .../loongarch/vector/lsx/lsx-vmsub.c | 461 ++ .../loongarch/vector/lsx/lsx-vmuh-1.c | 353 ++ .../loongarch/vector/lsx/lsx-vmuh-2.c | 372 ++ .../loongarch/vector/lsx/lsx-vmul.c | 282 + .../loongarch/vector/lsx/lsx-vmulwev-1.c | 434 ++ .../loongarch/vector/lsx/lsx-vmulwev-2.c | 344 ++ .../loongarch/vector/lsx/lsx-vmulwev-3.c | 245 + .../loongarch/vector/lsx/lsx-vmulwod-1.c | 272 + .../loongarch/vector/lsx/lsx-vmulwod-2.c | 282 + .../loongarch/vector/lsx/lsx-vmulwod-3.c | 308 + .../loongarch/vector/lsx/lsx-vneg.c | 321 ++ .../loongarch/vector/lsx/lsx-vsadd-1.c | 335 ++ .../loongarch/vector/lsx/lsx-vsadd-2.c | 345 ++ .../loongarch/vector/lsx/lsx-vsat-1.c | 231 + .../loongarch/vector/lsx/lsx-vsat-2.c | 272 + .../loongarch/vector/lsx/lsx-vsigncov.c | 425 ++ .../loongarch/vector/lsx/lsx-vssub-1.c | 398 ++ .../loongarch/vector/lsx/lsx-vssub-2.c | 408 ++ .../loongarch/vector/lsx/lsx-vsub.c | 381 ++ .../loongarch/vector/lsx/lsx-vsubi.c | 329 ++ .../loongarch/vector/lsx/lsx-vsubwev-1.c | 326 ++ .../loongarch/vector/lsx/lsx-vsubwev-2.c | 417 ++ .../loongarch/vector/lsx/lsx-vsubwod-1.c | 326 ++ .../loongarch/vector/lsx/lsx-vsubwod-2.c | 308 + .../loongarch/vector/simd_correctness_check.h | 54 + 79 files changed, 30696 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vadd.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vadda.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavgr-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavgr-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_d.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-4.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhaddw-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhaddw-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhsubw-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhsubw-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vldi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmadd.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaxi-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaxi-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmin-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmin-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmini-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmini-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmskgez.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmskltz.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmsknz.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmsub.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmuh-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmuh-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmul.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-3.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vneg.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsat-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsat-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsigncov.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssub-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssub-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsub.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubi.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwev-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwev-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwod-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwod-2.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h -- 2.20.1