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* [PATCH v3 0/9] Added support for SX/LSX vector instructions.
@ 2023-09-11  3:44 Xiaolong Chen
  2023-09-11  3:44 ` [PATCH v3 1/9] LoongArch: Add tests of -mstrict-align option Xiaolong Chen
                   ` (7 more replies)
  0 siblings, 8 replies; 10+ messages in thread
From: Xiaolong Chen @ 2023-09-11  3:44 UTC (permalink / raw)
  To: gcc-patches; +Cc: xry111, i, xuchenghua, chenglulu, Xiaolong Chen

v2 -> v3:
  Standardize the code using the GNU format.

  In order to better test the function of the vector instruction, the 128 and 256 
bit test cases are further split according to the function of the instruction.

Xiaolong Chen (9):
  LoongArch: Add tests of -mstrict-align option.
  LoongArch: Add testsuite framework for Loongson SX/ASX.
  LoongArch: Add tests for Loongson SX builtin functions.
  LoongArch:Added support for SX vector floating-point instructions.
  LoongArch:Add SX instructions for vector arithmetic addition
    operations.
  LoongArch:Add vector subtraction arithmetic operation SX instruction.
  LoongArch:Add vector arithmetic addition vsadd instruction.
  LoongArch:Added SX vector arithmetic multiplication instruction.
  LoongArch:Add SX instructions for vector arithmetic operations other
    than multiplication, addition, and subtraction.

 .../gcc.target/loongarch/strict-align.c       |   12 +
 .../loongarch/vector/loongarch-vector.exp     |   42 +
 .../loongarch/vector/lsx/lsx-builtin.c        | 5038 +++++++++++++++++
 .../loongarch/vector/lsx/lsx-vadd.c           |  416 ++
 .../loongarch/vector/lsx/lsx-vadda.c          |  344 ++
 .../loongarch/vector/lsx/lsx-vaddi.c          |  251 +
 .../loongarch/vector/lsx/lsx-vaddwev-1.c      |  335 ++
 .../loongarch/vector/lsx/lsx-vaddwev-2.c      |  344 ++
 .../loongarch/vector/lsx/lsx-vaddwev-3.c      |  425 ++
 .../loongarch/vector/lsx/lsx-vaddwod-1.c      |  408 ++
 .../loongarch/vector/lsx/lsx-vaddwod-2.c      |  344 ++
 .../loongarch/vector/lsx/lsx-vaddwod-3.c      |  237 +
 .../loongarch/vector/lsx/lsx-vavg-1.c         |  398 ++
 .../loongarch/vector/lsx/lsx-vavg-2.c         |  308 +
 .../loongarch/vector/lsx/lsx-vavgr-1.c        |  299 +
 .../loongarch/vector/lsx/lsx-vavgr-2.c        |  317 ++
 .../loongarch/vector/lsx/lsx-vdiv-1.c         |  299 +
 .../loongarch/vector/lsx/lsx-vdiv-2.c         |  254 +
 .../loongarch/vector/lsx/lsx-vexth-1.c        |  342 ++
 .../loongarch/vector/lsx/lsx-vexth-2.c        |  182 +
 .../loongarch/vector/lsx/lsx-vfcvt-1.c        |  398 ++
 .../loongarch/vector/lsx/lsx-vfcvt-2.c        |  278 +
 .../loongarch/vector/lsx/lsx-vffint-1.c       |  161 +
 .../loongarch/vector/lsx/lsx-vffint-2.c       |  264 +
 .../loongarch/vector/lsx/lsx-vffint-3.c       |  102 +
 .../loongarch/vector/lsx/lsx-vfrint_d.c       |  230 +
 .../loongarch/vector/lsx/lsx-vfrint_s.c       |  350 ++
 .../loongarch/vector/lsx/lsx-vftint-1.c       |  349 ++
 .../loongarch/vector/lsx/lsx-vftint-2.c       |  695 +++
 .../loongarch/vector/lsx/lsx-vftint-3.c       | 1028 ++++
 .../loongarch/vector/lsx/lsx-vftint-4.c       |  345 ++
 .../loongarch/vector/lsx/lsx-vhaddw-1.c       |  488 ++
 .../loongarch/vector/lsx/lsx-vhaddw-2.c       |  452 ++
 .../loongarch/vector/lsx/lsx-vhsubw-1.c       |  327 ++
 .../loongarch/vector/lsx/lsx-vhsubw-2.c       |  353 ++
 .../loongarch/vector/lsx/lsx-vldi.c           |   61 +
 .../loongarch/vector/lsx/lsx-vmadd.c          |  450 ++
 .../loongarch/vector/lsx/lsx-vmaddwev-1.c     |  472 ++
 .../loongarch/vector/lsx/lsx-vmaddwev-2.c     |  383 ++
 .../loongarch/vector/lsx/lsx-vmaddwev-3.c     |  383 ++
 .../loongarch/vector/lsx/lsx-vmaddwod-1.c     |  372 ++
 .../loongarch/vector/lsx/lsx-vmaddwod-2.c     |  438 ++
 .../loongarch/vector/lsx/lsx-vmaddwod-3.c     |  460 ++
 .../loongarch/vector/lsx/lsx-vmax-1.c         |  317 ++
 .../loongarch/vector/lsx/lsx-vmax-2.c         |  362 ++
 .../loongarch/vector/lsx/lsx-vmaxi-1.c        |  279 +
 .../loongarch/vector/lsx/lsx-vmaxi-2.c        |  223 +
 .../loongarch/vector/lsx/lsx-vmin-1.c         |  434 ++
 .../loongarch/vector/lsx/lsx-vmin-2.c         |  344 ++
 .../loongarch/vector/lsx/lsx-vmini-1.c        |  314 +
 .../loongarch/vector/lsx/lsx-vmini-2.c        |  216 +
 .../loongarch/vector/lsx/lsx-vmskgez.c        |  119 +
 .../loongarch/vector/lsx/lsx-vmskltz.c        |  321 ++
 .../loongarch/vector/lsx/lsx-vmsknz.c         |  104 +
 .../loongarch/vector/lsx/lsx-vmsub.c          |  461 ++
 .../loongarch/vector/lsx/lsx-vmuh-1.c         |  353 ++
 .../loongarch/vector/lsx/lsx-vmuh-2.c         |  372 ++
 .../loongarch/vector/lsx/lsx-vmul.c           |  282 +
 .../loongarch/vector/lsx/lsx-vmulwev-1.c      |  434 ++
 .../loongarch/vector/lsx/lsx-vmulwev-2.c      |  344 ++
 .../loongarch/vector/lsx/lsx-vmulwev-3.c      |  245 +
 .../loongarch/vector/lsx/lsx-vmulwod-1.c      |  272 +
 .../loongarch/vector/lsx/lsx-vmulwod-2.c      |  282 +
 .../loongarch/vector/lsx/lsx-vmulwod-3.c      |  308 +
 .../loongarch/vector/lsx/lsx-vneg.c           |  321 ++
 .../loongarch/vector/lsx/lsx-vsadd-1.c        |  335 ++
 .../loongarch/vector/lsx/lsx-vsadd-2.c        |  345 ++
 .../loongarch/vector/lsx/lsx-vsat-1.c         |  231 +
 .../loongarch/vector/lsx/lsx-vsat-2.c         |  272 +
 .../loongarch/vector/lsx/lsx-vsigncov.c       |  425 ++
 .../loongarch/vector/lsx/lsx-vssub-1.c        |  398 ++
 .../loongarch/vector/lsx/lsx-vssub-2.c        |  408 ++
 .../loongarch/vector/lsx/lsx-vsub.c           |  381 ++
 .../loongarch/vector/lsx/lsx-vsubi.c          |  329 ++
 .../loongarch/vector/lsx/lsx-vsubwev-1.c      |  326 ++
 .../loongarch/vector/lsx/lsx-vsubwev-2.c      |  417 ++
 .../loongarch/vector/lsx/lsx-vsubwod-1.c      |  326 ++
 .../loongarch/vector/lsx/lsx-vsubwod-2.c      |  308 +
 .../loongarch/vector/simd_correctness_check.h |   54 +
 79 files changed, 30696 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vadd.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vadda.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddi.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwev-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vaddwod-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavgr-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavgr-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_d.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-4.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhaddw-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhaddw-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhsubw-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vhsubw-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vldi.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmadd.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwev-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaddwod-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaxi-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaxi-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmin-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmin-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmini-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmini-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmskgez.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmskltz.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmsknz.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmsub.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmuh-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmuh-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmul.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwev-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmulwod-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vneg.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsat-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsat-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsigncov.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssub-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vssub-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsub.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubi.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwev-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwev-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwod-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsubwod-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h

-- 
2.20.1


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Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-11  3:44 [PATCH v3 0/9] Added support for SX/LSX vector instructions Xiaolong Chen
2023-09-11  3:44 ` [PATCH v3 1/9] LoongArch: Add tests of -mstrict-align option Xiaolong Chen
2023-09-11  3:44 ` [PATCH v3 2/9] LoongArch: Add testsuite framework for Loongson SX/ASX Xiaolong Chen
2023-09-11  3:44 ` [PATCH v3 3/9] LoongArch: Add tests for Loongson SX builtin functions Xiaolong Chen
2023-09-11  3:44 ` [PATCH v3 4/9] LoongArch:Added support for SX vector floating-point instructions Xiaolong Chen
2023-09-11  4:11   ` Xi Ruoyao
2023-09-11  3:44 ` [PATCH v3 5/9] LoongArch:Add SX instructions for vector arithmetic addition operations Xiaolong Chen
2023-09-11  3:44 ` [PATCH v3 6/9] LoongArch:Add vector subtraction arithmetic operation SX instruction Xiaolong Chen
2023-09-11  3:44 ` [PATCH v3 7/9] LoongArch:Add vector arithmetic addition vsadd instruction Xiaolong Chen
2023-09-11  3:44 ` [PATCH v3 8/9] LoongArch:Added SX vector arithmetic multiplication instruction Xiaolong Chen

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