From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id A38D53858C52 for ; Fri, 15 Sep 2023 13:23:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A38D53858C52 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694784200; x=1726320200; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=tMN8hiQSxt23IkRTTNf4P+R0wbDcMtHB6Sv7dL65h1U=; b=ZkQ6teunV/nHwgceqjHn774CeGybR3qZSUzU8qnC4aL/aiYJVWllzO9M RFbvHq2xCP53VnFoFlfY8BOw2b35chA/2YcxUhaS5lOgfp9Xbuw+YvwbH r+pT9y1TLKIQy919my3O4DbaYU9K4F5ZWMWVZDCm68hDsx4E27yUd67kB 0i07VLw/+46cvX9CRpzuOET+cepUqwUz+mxybxMCbO999kKu0nv8k1KSv CiW/ZP05RT4WkTChLKZ8fyc5CQRO0REuwEKUOpGlbmhAgB2Dt+/Q3Y+AV LHsx4bqq3ogQvqZp5n+k1xifsG4eSqDnSUs5perka3WbjYa3fsQEWtxIV Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10834"; a="378160100" X-IronPort-AV: E=Sophos;i="6.02,149,1688454000"; d="scan'208";a="378160100" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2023 06:23:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10834"; a="774318311" X-IronPort-AV: E=Sophos;i="6.02,149,1688454000"; d="scan'208";a="774318311" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga008.jf.intel.com with ESMTP; 15 Sep 2023 06:23:13 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 5B2161005669; Fri, 15 Sep 2023 21:23:12 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support FP SGNJX autovec for VLS mode Date: Fri, 15 Sep 2023 21:23:02 +0800 Message-Id: <20230915132302.3468514-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to allow the VLS mode autovec for the floating-point binary operation SGNJX. Give sample code as below: void test (float * restrict out, float * restrict in1, float * restrict in2) { for (int i = 0; i < 128; i++) out[i] = in1[i] * copysignf (1.0, in2[i]); } Before this patch: test: li a5,128 vsetvli zero,a5,e32,m1,ta,ma vle32.v v2,0(a1) lui a4,%hi(.LC0) flw fa5,%lo(.LC0)(a4) vfmv.v.f v1,fa5 vle32.v v3,0(a2) vfsgnj.vv v1,v1,v3 vfmul.vv v1,v1,v2 vse32.v v1,0(a0) ret After this patch: test: li a5,128 vsetvli zero,a5,e32,m1,ta,ma vle32.v v1,0(a1) vle32.v v2,0(a2) vfsgnjx.vv v1,v1,v2 vse32.v v1,0(a0) ret This SGNJX autovec acts on function call copysignf/copysignf in math.h too. And it depends on the option -ffast-math. gcc/ChangeLog: * config/riscv/autovec-vls.md (xorsign3): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: New macro. * gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/autovec-vls.md | 21 +++++++++ .../gcc.target/riscv/rvv/autovec/vls/def.h | 8 ++++ .../rvv/autovec/vls/floating-point-sgnjx-1.c | 43 +++++++++++++++++++ .../rvv/autovec/vls/floating-point-sgnjx-2.c | 31 +++++++++++++ 4 files changed, 103 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md index 6f48f7d6232..d4ed2081537 100644 --- a/gcc/config/riscv/autovec-vls.md +++ b/gcc/config/riscv/autovec-vls.md @@ -289,6 +289,27 @@ (define_insn_and_split "copysign3" [(set_attr "type" "vector")] ) +;; ------------------------------------------------------------------------- +;; Includes: +;; - vfsgnjx.vv +;; - vfsgnjx.vf +;; ------------------------------------------------------------------------- +(define_insn_and_split "xorsign3" + [(set (match_operand:VLSF 0 "register_operand") + (unspec:VLSF + [(match_operand:VLSF 1 "register_operand") + (match_operand:VLSF 2 "register_operand")] UNSPEC_VXORSIGN))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VXORSIGN, mode), + riscv_vector::BINARY_OP, operands); + DONE; + } +) + ;; ------------------------------------------------------------------------------- ;; ---- [INT] Unary operations ;; ------------------------------------------------------------------------------- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 1edc1910920..81c4570836b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -258,3 +258,11 @@ typedef double v512df __attribute__ ((vector_size (4096))); for (int i = 0; i < NUM; ++i) \ a[i] = (b[i] > c[i]) OP (d[i] < e[i]); \ } + +#define DEF_SGNJX_VV(PREFIX, NUM, TYPE, CALL) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = b[i] * CALL (1.0, c[i]); \ + } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c new file mode 100644 index 00000000000..86c23ef0436 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" + +DEF_SGNJX_VV (sgnj, 1, _Float16, __builtin_copysignf16) +DEF_SGNJX_VV (sgnj, 2, _Float16, __builtin_copysignf16) +DEF_SGNJX_VV (sgnj, 4, _Float16, __builtin_copysignf16) +DEF_SGNJX_VV (sgnj, 8, _Float16, __builtin_copysignf16) +DEF_SGNJX_VV (sgnj, 16, _Float16, __builtin_copysignf16) +DEF_SGNJX_VV (sgnj, 32, _Float16, __builtin_copysignf16) +DEF_SGNJX_VV (sgnj, 64, _Float16, __builtin_copysignf16) +DEF_SGNJX_VV (sgnj, 128, _Float16, __builtin_copysignf16) +DEF_SGNJX_VV (sgnj, 256, _Float16, __builtin_copysignf16) +DEF_SGNJX_VV (sgnj, 512, _Float16, __builtin_copysignf16) +DEF_SGNJX_VV (sgnj, 1024, _Float16, __builtin_copysignf16) +DEF_SGNJX_VV (sgnj, 2048, _Float16, __builtin_copysignf16) + +DEF_SGNJX_VV (sgnj, 1, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 2, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 4, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 8, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 16, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 32, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 64, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 128, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 256, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 512, float, __builtin_copysignf) +DEF_SGNJX_VV (sgnj, 1024, float, __builtin_copysignf) + +DEF_SGNJX_VV (sgnj, 1, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 2, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 4, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 8, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 16, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 32, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 64, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 128, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 256, double, __builtin_copysign) +DEF_SGNJX_VV (sgnj, 512, double, __builtin_copysign) + +/* { dg-final { scan-assembler-times {vfsgnjx\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c new file mode 100644 index 00000000000..7e017de6a25 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnjx-2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" +#include + +DEF_SGNJX_VV (sgnj, 1, float, copysignf) +DEF_SGNJX_VV (sgnj, 2, float, copysignf) +DEF_SGNJX_VV (sgnj, 4, float, copysignf) +DEF_SGNJX_VV (sgnj, 8, float, copysignf) +DEF_SGNJX_VV (sgnj, 16, float, copysignf) +DEF_SGNJX_VV (sgnj, 32, float, copysignf) +DEF_SGNJX_VV (sgnj, 64, float, copysignf) +DEF_SGNJX_VV (sgnj, 128, float, copysignf) +DEF_SGNJX_VV (sgnj, 256, float, copysignf) +DEF_SGNJX_VV (sgnj, 512, float, copysignf) +DEF_SGNJX_VV (sgnj, 1024, float, copysignf) + +DEF_SGNJX_VV (sgnj, 1, double, copysign) +DEF_SGNJX_VV (sgnj, 2, double, copysign) +DEF_SGNJX_VV (sgnj, 4, double, copysign) +DEF_SGNJX_VV (sgnj, 8, double, copysign) +DEF_SGNJX_VV (sgnj, 16, double, copysign) +DEF_SGNJX_VV (sgnj, 32, double, copysign) +DEF_SGNJX_VV (sgnj, 64, double, copysign) +DEF_SGNJX_VV (sgnj, 128, double, copysign) +DEF_SGNJX_VV (sgnj, 256, double, copysign) +DEF_SGNJX_VV (sgnj, 512, double, copysign) + +/* { dg-final { scan-assembler-times {vfsgnjx\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ -- 2.34.1