[PATCH] RISC-V: Remove redundant vec_duplicate pattern

[Juzhe-Zhong <juzhe.zhong@rivai.ai>]

Currently, VLS and VLA patterns are different.
VLA is define_expand
VLS is define_insn_and_split

It makes no sense that they are different pattern format.
Merge them into same pattern (define_insn_and_split).
It can also be helpful for the future vv -> vx fwprop optimization.

gcc/ChangeLog:

	* config/riscv/riscv-selftests.cc (run_broadcast_selftests): Adapt selftests.
	* config/riscv/vector.md (@vec_duplicate<mode>): Remove.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr111313.c: Adapt test.

---
 gcc/config/riscv/riscv-selftests.cc            |  4 ++--
 gcc/config/riscv/vector.md                     | 18 +++---------------
 .../gcc.target/riscv/rvv/autovec/pr111313.c    |  4 ++--
 3 files changed, 7 insertions(+), 19 deletions(-)

diff --git a/gcc/config/riscv/riscv-selftests.cc b/gcc/config/riscv/riscv-selftests.cc
index b16b5c15286..cdc863ee4f7 100644
--- a/gcc/config/riscv/riscv-selftests.cc
+++ b/gcc/config/riscv/riscv-selftests.cc
@@ -343,7 +343,7 @@ run_broadcast_selftests (void)
 	  rtx mem = gen_rtx_MEM (inner_mode, addr);                            \
 	  expand_vector_broadcast (mode, mem);                                 \
 	  insn = get_last_insn ();                                             \
-	  src = XEXP (SET_SRC (PATTERN (insn)), 1);                            \
+	  src = SET_SRC (PATTERN (insn));                                      \
 	  ASSERT_TRUE (MEM_P (XEXP (src, 0)));                                 \
 	  ASSERT_TRUE (                                                        \
 	    rtx_equal_p (src, gen_rtx_VEC_DUPLICATE (mode, XEXP (src, 0))));   \
@@ -353,7 +353,7 @@ run_broadcast_selftests (void)
 	  rtx reg = gen_reg_rtx (inner_mode);                                  \
 	  expand_vector_broadcast (mode, reg);                                 \
 	  insn = get_last_insn ();                                             \
-	  src = XEXP (SET_SRC (PATTERN (insn)), 1);                            \
+	  src = SET_SRC (PATTERN (insn));                                      \
 	  ASSERT_TRUE (REG_P (XEXP (src, 0)));                                 \
 	  ASSERT_TRUE (                                                        \
 	    rtx_equal_p (src, gen_rtx_VEC_DUPLICATE (mode, XEXP (src, 0))));   \
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 39b550c1bff..6d3c43e05ee 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1371,22 +1371,10 @@
 ;; This pattern only handles duplicates of non-constant inputs.
 ;; Constant vectors go through the movm pattern instead.
 ;; So "direct_broadcast_operand" can only be mem or reg, no CONSTANT.
-(define_expand "@vec_duplicate<mode>"
-  [(set (match_operand:V 0 "register_operand")
-	(vec_duplicate:V
-	  (match_operand:<VEL> 1 "direct_broadcast_operand")))]
-  "TARGET_VECTOR"
-  {
-    riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
-				    riscv_vector::UNARY_OP, operands);
-    DONE;
-  }
-)
-
 (define_insn_and_split "@vec_duplicate<mode>"
-  [(set (match_operand:VLS 0 "register_operand")
-        (vec_duplicate:VLS
-          (match_operand:<VEL> 1 "reg_or_int_operand")))]
+  [(set (match_operand:V_VLS 0 "register_operand")
+        (vec_duplicate:V_VLS
+          (match_operand:<VEL> 1 "direct_broadcast_operand")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
index 1da1b8ce6fb..1e01cfefd47 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #define K 32
 short in[2*K][K];
@@ -17,4 +17,4 @@ foo ()
   }
 }
 
-/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmv\.v\.x} 1 } } */
-- 
2.36.3