* [Committed] RISC-V: Support VLS unary floating-point patterns
@ 2023-09-19 11:26 Juzhe-Zhong
2023-09-20 0:34 ` Patrick O'Neill
0 siblings, 1 reply; 13+ messages in thread
From: Juzhe-Zhong @ 2023-09-19 11:26 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, kito.cheng, jeffreyalaw, rdapp.gcc, Juzhe-Zhong
Extend current VLA patterns with VLS modes.
Regression all passed.
gcc/ChangeLog:
* config/riscv/autovec.md: Extend VLS modes.
* config/riscv/vector.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test.
* gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test.
---
gcc/config/riscv/autovec.md | 12 ++---
gcc/config/riscv/vector.md | 20 +++----
.../gcc.target/riscv/rvv/autovec/vls/def.h | 3 +-
.../gcc.target/riscv/rvv/autovec/vls/neg-2.c | 52 +++++++++++++++++++
4 files changed, 70 insertions(+), 17 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 769ef6daa36..75ed7ae4f2e 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1031,9 +1031,9 @@
;; - vfneg.v/vfabs.v
;; -------------------------------------------------------------------------------
(define_insn_and_split "<optab><mode>2"
- [(set (match_operand:VF 0 "register_operand")
- (any_float_unop_nofrm:VF
- (match_operand:VF 1 "register_operand")))]
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (any_float_unop_nofrm:V_VLSF
+ (match_operand:V_VLSF 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -1052,9 +1052,9 @@
;; - vfsqrt.v
;; -------------------------------------------------------------------------------
(define_insn_and_split "<optab><mode>2"
- [(set (match_operand:VF 0 "register_operand")
- (any_float_unop:VF
- (match_operand:VF 1 "register_operand")))]
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (any_float_unop:V_VLSF
+ (match_operand:V_VLSF 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f7f37da692a..f66ffebba24 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6756,8 +6756,8 @@
;; -------------------------------------------------------------------------------
(define_insn "@pred_<optab><mode>"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
@@ -6768,9 +6768,9 @@
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
- (any_float_unop:VF
- (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (any_float_unop:V_VLSF
+ (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
@@ -6783,8 +6783,8 @@
(symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
- [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
- (if_then_else:VF
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
+ (if_then_else:V_VLSF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
@@ -6793,9 +6793,9 @@
(match_operand 7 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_float_unop_nofrm:VF
- (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
- (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
+ (any_float_unop_nofrm:V_VLSF
+ (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vf<insn>.v\t%0,%3%p1"
[(set_attr "type" "<float_insn_type>")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 5df90704885..d7b721b4e3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -1,4 +1,5 @@
#include <stdint-gcc.h>
+#include <math.h>
typedef int8_t v1qi __attribute__ ((vector_size (1)));
typedef int8_t v2qi __attribute__ ((vector_size (2)));
@@ -210,7 +211,7 @@ typedef double v512df __attribute__ ((vector_size (4096)));
PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) \
{ \
for (int i = 0; i < NUM; ++i) \
- a[i] = OP b[i]; \
+ a[i] = OP (b[i]); \
}
#define DEF_CALL_VV(PREFIX, NUM, TYPE, CALL) \
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
new file mode 100644
index 00000000000..c2ab0098afa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
+
+#include "def.h"
+
+DEF_OP_V (neg, 2, _Float16, -)
+DEF_OP_V (neg, 4, _Float16, -)
+DEF_OP_V (neg, 8, _Float16, -)
+DEF_OP_V (neg, 16, _Float16, -)
+DEF_OP_V (neg, 32, _Float16, -)
+DEF_OP_V (neg, 64, _Float16, -)
+DEF_OP_V (neg, 128, _Float16, -)
+DEF_OP_V (neg, 256, _Float16, -)
+DEF_OP_V (neg, 512, _Float16, -)
+DEF_OP_V (neg, 1024, _Float16, -)
+DEF_OP_V (neg, 2048, _Float16, -)
+
+DEF_OP_V (neg, 2, float, -)
+DEF_OP_V (neg, 4, float, -)
+DEF_OP_V (neg, 8, float, -)
+DEF_OP_V (neg, 16, float, -)
+DEF_OP_V (neg, 32, float, -)
+DEF_OP_V (neg, 64, float, -)
+DEF_OP_V (neg, 128, float, -)
+DEF_OP_V (neg, 256, float, -)
+DEF_OP_V (neg, 512, float, -)
+DEF_OP_V (neg, 1024, float, -)
+
+DEF_OP_V (neg, 2, double, -)
+DEF_OP_V (neg, 4, double, -)
+DEF_OP_V (neg, 8, double, -)
+DEF_OP_V (neg, 16, double, -)
+DEF_OP_V (neg, 32, double, -)
+DEF_OP_V (neg, 64, double, -)
+DEF_OP_V (neg, 128, double, -)
+DEF_OP_V (neg, 256, double, -)
+DEF_OP_V (neg, 512, double, -)
+
+/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
--
2.36.3
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-19 11:26 [Committed] RISC-V: Support VLS unary floating-point patterns Juzhe-Zhong
@ 2023-09-20 0:34 ` Patrick O'Neill
2023-09-20 0:43 ` juzhe.zhong
0 siblings, 1 reply; 13+ messages in thread
From: Patrick O'Neill @ 2023-09-20 0:34 UTC (permalink / raw)
To: Juzhe-Zhong, Robin Dapp, gcc-patches
Cc: kito.cheng, kito.cheng, jeffreyalaw, Palmer Dabbelt, Edwin Lu,
joern.rennecke, jeremy.bennett, gnu-toolchain
Hi,
This patch highlights an issue Edwin and I have been having with the
testsuite where rv64 testcases are run when testing rv32gcv.
There's a large number of new failures in the rv32gcv testsuite from
this seemingly innocuous patch.
https://github.com/ewlu/riscv-gnu-toolchain/issues/166
(The repo is still a WIP - eventually will be non-gating patchworks
pre-commit CI)
From Edwin and my investigation the failures for rv32gcv look like [1].
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
fatal error: gnu/stubs-lp64d.h: No such file or directory
compilation terminated.
Top of the failing testcase:
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
#include "def.h"
The dg-options explicitly set rv64gcv, so I don't think this testcase
should even be executed.
For the 3 new failures on rv64gcv, they all explicitly set rv32gcv.
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
These are seen on non-multilib builds. Multilib rv32/64gc does not
appear to have the same issue when compiling (we're currently testing
multilib rv32/64gcv to see if they encounter issues when executing).
Are other people seeing similar errors/is this a known issue?
Patrick
[1]:
Executing on host:
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
-B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
-O3 -ftree-vectorize --param riscv-autovec-preference=scalable
-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffat-lto-objects
-fno-ident -S -o floating-point-mul-3.s (timeout = 600)
spawn -ignore SIGHUP
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
-B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
-O3 -ftree-vectorize --param riscv-autovec-preference=scalable
-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffat-lto-objects
-fno-ident -S -o floating-point-mul-3.s
In file included from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h:2,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c:4:
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
fatal error: gnu/stubs-lp64d.h: No such file or directory
compilation terminated.
compiler exited with status 1
FAIL: gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c -O3
-ftree-vectorize --param riscv-autovec-preference=scalable (test for
excess errors)
On 9/19/23 04:26, Juzhe-Zhong wrote:
> Extend current VLA patterns with VLS modes.
>
> Regression all passed.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Extend VLS modes.
> * config/riscv/vector.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test.
> * gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test.
>
> ---
> gcc/config/riscv/autovec.md | 12 ++---
> gcc/config/riscv/vector.md | 20 +++----
> .../gcc.target/riscv/rvv/autovec/vls/def.h | 3 +-
> .../gcc.target/riscv/rvv/autovec/vls/neg-2.c | 52 +++++++++++++++++++
> 4 files changed, 70 insertions(+), 17 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 769ef6daa36..75ed7ae4f2e 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1031,9 +1031,9 @@
> ;; - vfneg.v/vfabs.v
> ;; -------------------------------------------------------------------------------
> (define_insn_and_split "<optab><mode>2"
> - [(set (match_operand:VF 0 "register_operand")
> - (any_float_unop_nofrm:VF
> - (match_operand:VF 1 "register_operand")))]
> + [(set (match_operand:V_VLSF 0 "register_operand")
> + (any_float_unop_nofrm:V_VLSF
> + (match_operand:V_VLSF 1 "register_operand")))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> @@ -1052,9 +1052,9 @@
> ;; - vfsqrt.v
> ;; -------------------------------------------------------------------------------
> (define_insn_and_split "<optab><mode>2"
> - [(set (match_operand:VF 0 "register_operand")
> - (any_float_unop:VF
> - (match_operand:VF 1 "register_operand")))]
> + [(set (match_operand:V_VLSF 0 "register_operand")
> + (any_float_unop:V_VLSF
> + (match_operand:V_VLSF 1 "register_operand")))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index f7f37da692a..f66ffebba24 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -6756,8 +6756,8 @@
> ;; -------------------------------------------------------------------------------
>
> (define_insn "@pred_<optab><mode>"
> - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
> - (if_then_else:VF
> + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
> + (if_then_else:V_VLSF
> (unspec:<VM>
> [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
> (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
> @@ -6768,9 +6768,9 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)
> (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> - (any_float_unop:VF
> - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> + (any_float_unop:V_VLSF
> + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
> + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> "TARGET_VECTOR"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> @@ -6783,8 +6783,8 @@
> (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> (define_insn "@pred_<optab><mode>"
> - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
> - (if_then_else:VF
> + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
> + (if_then_else:V_VLSF
> (unspec:<VM>
> [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
> (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
> @@ -6793,9 +6793,9 @@
> (match_operand 7 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> - (any_float_unop_nofrm:VF
> - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> + (any_float_unop_nofrm:V_VLSF
> + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
> + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> "TARGET_VECTOR"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> index 5df90704885..d7b721b4e3e 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> @@ -1,4 +1,5 @@
> #include <stdint-gcc.h>
> +#include <math.h>
>
> typedef int8_t v1qi __attribute__ ((vector_size (1)));
> typedef int8_t v2qi __attribute__ ((vector_size (2)));
> @@ -210,7 +211,7 @@ typedef double v512df __attribute__ ((vector_size (4096)));
> PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) \
> { \
> for (int i = 0; i < NUM; ++i) \
> - a[i] = OP b[i]; \
> + a[i] = OP (b[i]); \
> }
>
> #define DEF_CALL_VV(PREFIX, NUM, TYPE, CALL) \
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> new file mode 100644
> index 00000000000..c2ab0098afa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> @@ -0,0 +1,52 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
> +
> +#include "def.h"
> +
> +DEF_OP_V (neg, 2, _Float16, -)
> +DEF_OP_V (neg, 4, _Float16, -)
> +DEF_OP_V (neg, 8, _Float16, -)
> +DEF_OP_V (neg, 16, _Float16, -)
> +DEF_OP_V (neg, 32, _Float16, -)
> +DEF_OP_V (neg, 64, _Float16, -)
> +DEF_OP_V (neg, 128, _Float16, -)
> +DEF_OP_V (neg, 256, _Float16, -)
> +DEF_OP_V (neg, 512, _Float16, -)
> +DEF_OP_V (neg, 1024, _Float16, -)
> +DEF_OP_V (neg, 2048, _Float16, -)
> +
> +DEF_OP_V (neg, 2, float, -)
> +DEF_OP_V (neg, 4, float, -)
> +DEF_OP_V (neg, 8, float, -)
> +DEF_OP_V (neg, 16, float, -)
> +DEF_OP_V (neg, 32, float, -)
> +DEF_OP_V (neg, 64, float, -)
> +DEF_OP_V (neg, 128, float, -)
> +DEF_OP_V (neg, 256, float, -)
> +DEF_OP_V (neg, 512, float, -)
> +DEF_OP_V (neg, 1024, float, -)
> +
> +DEF_OP_V (neg, 2, double, -)
> +DEF_OP_V (neg, 4, double, -)
> +DEF_OP_V (neg, 8, double, -)
> +DEF_OP_V (neg, 16, double, -)
> +DEF_OP_V (neg, 32, double, -)
> +DEF_OP_V (neg, 64, double, -)
> +DEF_OP_V (neg, 128, double, -)
> +DEF_OP_V (neg, 256, double, -)
> +DEF_OP_V (neg, 512, double, -)
> +
> +/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
> +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-20 0:34 ` Patrick O'Neill
@ 2023-09-20 0:43 ` juzhe.zhong
2023-09-20 0:52 ` Kito Cheng
0 siblings, 1 reply; 13+ messages in thread
From: juzhe.zhong @ 2023-09-20 0:43 UTC (permalink / raw)
To: Patrick O'Neill, Robin Dapp, gcc-patches
Cc: kito.cheng, Kito.cheng, jeffreyalaw, palmer, Edwin Lu,
joern.rennecke, jeremy.bennett, gnu-toolchain
[-- Attachment #1: Type: text/plain, Size: 12373 bytes --]
I didn't see this issue.
They should be the bogus FAILs.
We should either fix testcases or ignore them.
juzhe.zhong@rivai.ai
From: Patrick O'Neill
Date: 2023-09-20 08:34
To: Juzhe-Zhong; Robin Dapp; gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; Palmer Dabbelt; Edwin Lu; joern.rennecke; jeremy.bennett; gnu-toolchain
Subject: Re: [Committed] RISC-V: Support VLS unary floating-point patterns
Hi,
This patch highlights an issue Edwin and I have been having with the
testsuite where rv64 testcases are run when testing rv32gcv.
There's a large number of new failures in the rv32gcv testsuite from
this seemingly innocuous patch.
https://github.com/ewlu/riscv-gnu-toolchain/issues/166
(The repo is still a WIP - eventually will be non-gating patchworks
pre-commit CI)
From Edwin and my investigation the failures for rv32gcv look like [1].
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
fatal error: gnu/stubs-lp64d.h: No such file or directory
compilation terminated.
Top of the failing testcase:
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
#include "def.h"
The dg-options explicitly set rv64gcv, so I don't think this testcase
should even be executed.
For the 3 new failures on rv64gcv, they all explicitly set rv32gcv.
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
These are seen on non-multilib builds. Multilib rv32/64gc does not
appear to have the same issue when compiling (we're currently testing
multilib rv32/64gcv to see if they encounter issues when executing).
Are other people seeing similar errors/is this a known issue?
Patrick
[1]:
Executing on host:
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
-B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
-O3 -ftree-vectorize --param riscv-autovec-preference=scalable
-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffat-lto-objects
-fno-ident -S -o floating-point-mul-3.s (timeout = 600)
spawn -ignore SIGHUP
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
-B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
-O3 -ftree-vectorize --param riscv-autovec-preference=scalable
-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffat-lto-objects
-fno-ident -S -o floating-point-mul-3.s
In file included from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h:2,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c:4:
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
fatal error: gnu/stubs-lp64d.h: No such file or directory
compilation terminated.
compiler exited with status 1
FAIL: gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c -O3
-ftree-vectorize --param riscv-autovec-preference=scalable (test for
excess errors)
On 9/19/23 04:26, Juzhe-Zhong wrote:
> Extend current VLA patterns with VLS modes.
>
> Regression all passed.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Extend VLS modes.
> * config/riscv/vector.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test.
> * gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test.
>
> ---
> gcc/config/riscv/autovec.md | 12 ++---
> gcc/config/riscv/vector.md | 20 +++----
> .../gcc.target/riscv/rvv/autovec/vls/def.h | 3 +-
> .../gcc.target/riscv/rvv/autovec/vls/neg-2.c | 52 +++++++++++++++++++
> 4 files changed, 70 insertions(+), 17 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 769ef6daa36..75ed7ae4f2e 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1031,9 +1031,9 @@
> ;; - vfneg.v/vfabs.v
> ;; -------------------------------------------------------------------------------
> (define_insn_and_split "<optab><mode>2"
> - [(set (match_operand:VF 0 "register_operand")
> - (any_float_unop_nofrm:VF
> - (match_operand:VF 1 "register_operand")))]
> + [(set (match_operand:V_VLSF 0 "register_operand")
> + (any_float_unop_nofrm:V_VLSF
> + (match_operand:V_VLSF 1 "register_operand")))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> @@ -1052,9 +1052,9 @@
> ;; - vfsqrt.v
> ;; -------------------------------------------------------------------------------
> (define_insn_and_split "<optab><mode>2"
> - [(set (match_operand:VF 0 "register_operand")
> - (any_float_unop:VF
> - (match_operand:VF 1 "register_operand")))]
> + [(set (match_operand:V_VLSF 0 "register_operand")
> + (any_float_unop:V_VLSF
> + (match_operand:V_VLSF 1 "register_operand")))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index f7f37da692a..f66ffebba24 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -6756,8 +6756,8 @@
> ;; -------------------------------------------------------------------------------
>
> (define_insn "@pred_<optab><mode>"
> - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
> - (if_then_else:VF
> + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
> + (if_then_else:V_VLSF
> (unspec:<VM>
> [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
> (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
> @@ -6768,9 +6768,9 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)
> (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> - (any_float_unop:VF
> - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> + (any_float_unop:V_VLSF
> + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
> + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> "TARGET_VECTOR"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> @@ -6783,8 +6783,8 @@
> (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> (define_insn "@pred_<optab><mode>"
> - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
> - (if_then_else:VF
> + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
> + (if_then_else:V_VLSF
> (unspec:<VM>
> [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
> (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
> @@ -6793,9 +6793,9 @@
> (match_operand 7 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> - (any_float_unop_nofrm:VF
> - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> + (any_float_unop_nofrm:V_VLSF
> + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
> + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> "TARGET_VECTOR"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> index 5df90704885..d7b721b4e3e 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> @@ -1,4 +1,5 @@
> #include <stdint-gcc.h>
> +#include <math.h>
>
> typedef int8_t v1qi __attribute__ ((vector_size (1)));
> typedef int8_t v2qi __attribute__ ((vector_size (2)));
> @@ -210,7 +211,7 @@ typedef double v512df __attribute__ ((vector_size (4096)));
> PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) \
> { \
> for (int i = 0; i < NUM; ++i) \
> - a[i] = OP b[i]; \
> + a[i] = OP (b[i]); \
> }
>
> #define DEF_CALL_VV(PREFIX, NUM, TYPE, CALL) \
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> new file mode 100644
> index 00000000000..c2ab0098afa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> @@ -0,0 +1,52 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
> +
> +#include "def.h"
> +
> +DEF_OP_V (neg, 2, _Float16, -)
> +DEF_OP_V (neg, 4, _Float16, -)
> +DEF_OP_V (neg, 8, _Float16, -)
> +DEF_OP_V (neg, 16, _Float16, -)
> +DEF_OP_V (neg, 32, _Float16, -)
> +DEF_OP_V (neg, 64, _Float16, -)
> +DEF_OP_V (neg, 128, _Float16, -)
> +DEF_OP_V (neg, 256, _Float16, -)
> +DEF_OP_V (neg, 512, _Float16, -)
> +DEF_OP_V (neg, 1024, _Float16, -)
> +DEF_OP_V (neg, 2048, _Float16, -)
> +
> +DEF_OP_V (neg, 2, float, -)
> +DEF_OP_V (neg, 4, float, -)
> +DEF_OP_V (neg, 8, float, -)
> +DEF_OP_V (neg, 16, float, -)
> +DEF_OP_V (neg, 32, float, -)
> +DEF_OP_V (neg, 64, float, -)
> +DEF_OP_V (neg, 128, float, -)
> +DEF_OP_V (neg, 256, float, -)
> +DEF_OP_V (neg, 512, float, -)
> +DEF_OP_V (neg, 1024, float, -)
> +
> +DEF_OP_V (neg, 2, double, -)
> +DEF_OP_V (neg, 4, double, -)
> +DEF_OP_V (neg, 8, double, -)
> +DEF_OP_V (neg, 16, double, -)
> +DEF_OP_V (neg, 32, double, -)
> +DEF_OP_V (neg, 64, double, -)
> +DEF_OP_V (neg, 128, double, -)
> +DEF_OP_V (neg, 256, double, -)
> +DEF_OP_V (neg, 512, double, -)
> +
> +/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
> +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-20 0:43 ` juzhe.zhong
@ 2023-09-20 0:52 ` Kito Cheng
2023-09-20 0:54 ` juzhe.zhong
0 siblings, 1 reply; 13+ messages in thread
From: Kito Cheng @ 2023-09-20 0:52 UTC (permalink / raw)
To: 钟居哲
Cc: Patrick O'Neill, Robin Dapp, gcc-patches, Kito.cheng,
jeffreyalaw, palmer, Edwin Lu, joern.rennecke, jeremy.bennett,
gnu-toolchain
[-- Attachment #1: Type: text/plain, Size: 13428 bytes --]
It seems because math.h, similar issue as stdint.h, does math.h necessary
for the test case?
juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> 於 2023年9月20日 週三 08:44 寫道：
> I didn't see this issue.
> They should be the bogus FAILs.
> We should either fix testcases or ignore them.
>
> ------------------------------
> juzhe.zhong@rivai.ai
>
>
> *From:* Patrick O'Neill <patrick@rivosinc.com>
> *Date:* 2023-09-20 08:34
> *To:* Juzhe-Zhong <juzhe.zhong@rivai.ai>; Robin Dapp <rdapp.gcc@gmail.com>;
> gcc-patches <gcc-patches@gcc.gnu.org>
> *CC:* kito.cheng <kito.cheng@gmail.com>; kito.cheng
> <kito.cheng@sifive.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Palmer
> Dabbelt <palmer@rivosinc.com>; Edwin Lu <ewlu@rivosinc.com>;
> joern.rennecke <joern.rennecke@embecosm.com>; jeremy.bennett
> <jeremy.bennett@embecosm.com>; gnu-toolchain <gnu-toolchain@rivosinc.com>
> *Subject:* Re: [Committed] RISC-V: Support VLS unary floating-point
> patterns
> Hi,
>
> This patch highlights an issue Edwin and I have been having with the
> testsuite where rv64 testcases are run when testing rv32gcv.
>
> There's a large number of new failures in the rv32gcv testsuite from
> this seemingly innocuous patch.
>
> https://github.com/ewlu/riscv-gnu-toolchain/issues/166
> (The repo is still a WIP - eventually will be non-gating patchworks
> pre-commit CI)
>
> From Edwin and my investigation the failures for rv32gcv look like [1].
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
>
> fatal error: gnu/stubs-lp64d.h: No such file or directory
> compilation terminated.
>
> Top of the failing testcase:
> /* { dg-do compile } */
> /* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
> -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" }
> */
>
> #include "def.h"
>
> The dg-options explicitly set rv64gcv, so I don't think this testcase
> should even be executed.
>
> For the 3 new failures on rv64gcv, they all explicitly set rv32gcv.
> /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
>
> These are seen on non-multilib builds. Multilib rv32/64gc does not
> appear to have the same issue when compiling (we're currently testing
> multilib rv32/64gcv to see if they encounter issues when executing).
>
> Are other people seeing similar errors/is this a known issue?
>
> Patrick
>
> [1]:
> Executing on host:
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
>
> -B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
>
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
>
> -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
> -O3 -ftree-vectorize --param riscv-autovec-preference=scalable
> -march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns
> -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffat-lto-objects
> -fno-ident -S -o floating-point-mul-3.s (timeout = 600)
> spawn -ignore SIGHUP
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
>
> -B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
>
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
>
> -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
> -O3 -ftree-vectorize --param riscv-autovec-preference=scalable
> -march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns
> -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffat-lto-objects
> -fno-ident -S -o floating-point-mul-3.s
> In file included from
>
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
> from
>
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
> from
>
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
> from
>
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h:2,
> from
>
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c:4:
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
>
> fatal error: gnu/stubs-lp64d.h: No such file or directory
> compilation terminated.
> compiler exited with status 1
> FAIL: gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c -O3
> -ftree-vectorize --param riscv-autovec-preference=scalable (test for
> excess errors)
>
> On 9/19/23 04:26, Juzhe-Zhong wrote:
> > Extend current VLA patterns with VLS modes.
> >
> > Regression all passed.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/autovec.md: Extend VLS modes.
> > * config/riscv/vector.md: Ditto.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test.
> > * gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test.
> >
> > ---
> > gcc/config/riscv/autovec.md | 12 ++---
> > gcc/config/riscv/vector.md | 20 +++----
> > .../gcc.target/riscv/rvv/autovec/vls/def.h | 3 +-
> > .../gcc.target/riscv/rvv/autovec/vls/neg-2.c | 52 +++++++++++++++++++
> > 4 files changed, 70 insertions(+), 17 deletions(-)
> > create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> >
> > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> > index 769ef6daa36..75ed7ae4f2e 100644
> > --- a/gcc/config/riscv/autovec.md
> > +++ b/gcc/config/riscv/autovec.md
> > @@ -1031,9 +1031,9 @@
> > ;; - vfneg.v/vfabs.v
> > ;;
> -------------------------------------------------------------------------------
> > (define_insn_and_split "<optab><mode>2"
> > - [(set (match_operand:VF 0 "register_operand")
> > - (any_float_unop_nofrm:VF
> > - (match_operand:VF 1 "register_operand")))]
> > + [(set (match_operand:V_VLSF 0 "register_operand")
> > + (any_float_unop_nofrm:V_VLSF
> > + (match_operand:V_VLSF 1 "register_operand")))]
> > "TARGET_VECTOR && can_create_pseudo_p ()"
> > "#"
> > "&& 1"
> > @@ -1052,9 +1052,9 @@
> > ;; - vfsqrt.v
> > ;;
> -------------------------------------------------------------------------------
> > (define_insn_and_split "<optab><mode>2"
> > - [(set (match_operand:VF 0 "register_operand")
> > - (any_float_unop:VF
> > - (match_operand:VF 1 "register_operand")))]
> > + [(set (match_operand:V_VLSF 0 "register_operand")
> > + (any_float_unop:V_VLSF
> > + (match_operand:V_VLSF 1 "register_operand")))]
> > "TARGET_VECTOR && can_create_pseudo_p ()"
> > "#"
> > "&& 1"
> > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> > index f7f37da692a..f66ffebba24 100644
> > --- a/gcc/config/riscv/vector.md
> > +++ b/gcc/config/riscv/vector.md
> > @@ -6756,8 +6756,8 @@
> > ;;
> -------------------------------------------------------------------------------
> >
> > (define_insn "@pred_<optab><mode>"
> > - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr,
> vr")
> > - (if_then_else:VF
> > + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd,
> vr, vr")
> > + (if_then_else:V_VLSF
> > (unspec:<VM>
> > [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
> > (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
> > @@ -6768,9 +6768,9 @@
> > (reg:SI VL_REGNUM)
> > (reg:SI VTYPE_REGNUM)
> > (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> > - (any_float_unop:VF
> > - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> > - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > + (any_float_unop:V_VLSF
> > + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr,
> vr"))
> > + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu,
> 0")))]
> > "TARGET_VECTOR"
> > "vf<insn>.v\t%0,%3%p1"
> > [(set_attr "type" "<float_insn_type>")
> > @@ -6783,8 +6783,8 @@
> > (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
> >
> > (define_insn "@pred_<optab><mode>"
> > - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr,
> vr")
> > - (if_then_else:VF
> > + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd,
> vr, vr")
> > + (if_then_else:V_VLSF
> > (unspec:<VM>
> > [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
> > (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
> > @@ -6793,9 +6793,9 @@
> > (match_operand 7 "const_int_operand" " i, i, i, i")
> > (reg:SI VL_REGNUM)
> > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> > - (any_float_unop_nofrm:VF
> > - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> > - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> > + (any_float_unop_nofrm:V_VLSF
> > + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr,
> vr"))
> > + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu,
> 0")))]
> > "TARGET_VECTOR"
> > "vf<insn>.v\t%0,%3%p1"
> > [(set_attr "type" "<float_insn_type>")
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> > index 5df90704885..d7b721b4e3e 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> > @@ -1,4 +1,5 @@
> > #include <stdint-gcc.h>
> > +#include <math.h>
> >
> > typedef int8_t v1qi __attribute__ ((vector_size (1)));
> > typedef int8_t v2qi __attribute__ ((vector_size (2)));
> > @@ -210,7 +211,7 @@ typedef double v512df __attribute__ ((vector_size
> (4096)));
> > PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict
> b) \
> >
> {
> \
> > for (int i = 0; i < NUM;
> ++i) \
> > - a[i] = OP
> b[i]; \
> > + a[i] = OP
> (b[i]); \
> > }
> >
> > #define DEF_CALL_VV(PREFIX, NUM, TYPE,
> CALL) \
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> > new file mode 100644
> > index 00000000000..c2ab0098afa
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> > @@ -0,0 +1,52 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
> -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
> -fdump-tree-optimized" } */
> > +
> > +#include "def.h"
> > +
> > +DEF_OP_V (neg, 2, _Float16, -)
> > +DEF_OP_V (neg, 4, _Float16, -)
> > +DEF_OP_V (neg, 8, _Float16, -)
> > +DEF_OP_V (neg, 16, _Float16, -)
> > +DEF_OP_V (neg, 32, _Float16, -)
> > +DEF_OP_V (neg, 64, _Float16, -)
> > +DEF_OP_V (neg, 128, _Float16, -)
> > +DEF_OP_V (neg, 256, _Float16, -)
> > +DEF_OP_V (neg, 512, _Float16, -)
> > +DEF_OP_V (neg, 1024, _Float16, -)
> > +DEF_OP_V (neg, 2048, _Float16, -)
> > +
> > +DEF_OP_V (neg, 2, float, -)
> > +DEF_OP_V (neg, 4, float, -)
> > +DEF_OP_V (neg, 8, float, -)
> > +DEF_OP_V (neg, 16, float, -)
> > +DEF_OP_V (neg, 32, float, -)
> > +DEF_OP_V (neg, 64, float, -)
> > +DEF_OP_V (neg, 128, float, -)
> > +DEF_OP_V (neg, 256, float, -)
> > +DEF_OP_V (neg, 512, float, -)
> > +DEF_OP_V (neg, 1024, float, -)
> > +
> > +DEF_OP_V (neg, 2, double, -)
> > +DEF_OP_V (neg, 4, double, -)
> > +DEF_OP_V (neg, 8, double, -)
> > +DEF_OP_V (neg, 16, double, -)
> > +DEF_OP_V (neg, 32, double, -)
> > +DEF_OP_V (neg, 64, double, -)
> > +DEF_OP_V (neg, 128, double, -)
> > +DEF_OP_V (neg, 256, double, -)
> > +DEF_OP_V (neg, 512, double, -)
> > +
> > +/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30
> } } */
> > +/* { dg-final { scan-assembler-not {csrr} } } */
> > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
>
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-20 0:52 ` Kito Cheng
@ 2023-09-20 0:54 ` juzhe.zhong
2023-09-20 1:12 ` Patrick O'Neill
0 siblings, 1 reply; 13+ messages in thread
From: juzhe.zhong @ 2023-09-20 0:54 UTC (permalink / raw)
To: kito.cheng
Cc: Patrick O'Neill, Robin Dapp, gcc-patches, Kito.cheng,
jeffreyalaw, palmer, Edwin Lu, joern.rennecke, jeremy.bennett,
gnu-toolchain
[-- Attachment #1: Type: text/plain, Size: 13307 bytes --]
I think we could remove match.h.
Hi, @Patrick. Could you verify it?
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 2292372d7a3..674098e9ba6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -1,5 +1,4 @@
#include <stdint-gcc.h>
-#include <math.h>
and commit it.
Thanks.
juzhe.zhong@rivai.ai
From: Kito Cheng
Date: 2023-09-20 08:52
To: 钟居哲
CC: Patrick O'Neill; Robin Dapp; gcc-patches; Kito.cheng; jeffreyalaw; palmer; Edwin Lu; joern.rennecke; jeremy.bennett; gnu-toolchain
Subject: Re: Re: [Committed] RISC-V: Support VLS unary floating-point patterns
It seems because math.h, similar issue as stdint.h, does math.h necessary for the test case?
juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> 於 2023年9月20日 週三 08:44 寫道：
I didn't see this issue.
They should be the bogus FAILs.
We should either fix testcases or ignore them.
juzhe.zhong@rivai.ai
From: Patrick O'Neill
Date: 2023-09-20 08:34
To: Juzhe-Zhong; Robin Dapp; gcc-patches
CC: kito.cheng; kito.cheng; jeffreyalaw; Palmer Dabbelt; Edwin Lu; joern.rennecke; jeremy.bennett; gnu-toolchain
Subject: Re: [Committed] RISC-V: Support VLS unary floating-point patterns
Hi,
This patch highlights an issue Edwin and I have been having with the
testsuite where rv64 testcases are run when testing rv32gcv.
There's a large number of new failures in the rv32gcv testsuite from
this seemingly innocuous patch.
https://github.com/ewlu/riscv-gnu-toolchain/issues/166
(The repo is still a WIP - eventually will be non-gating patchworks
pre-commit CI)
From Edwin and my investigation the failures for rv32gcv look like [1].
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
fatal error: gnu/stubs-lp64d.h: No such file or directory
compilation terminated.
Top of the failing testcase:
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
-fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
#include "def.h"
The dg-options explicitly set rv64gcv, so I don't think this testcase
should even be executed.
For the 3 new failures on rv64gcv, they all explicitly set rv32gcv.
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
These are seen on non-multilib builds. Multilib rv32/64gc does not
appear to have the same issue when compiling (we're currently testing
multilib rv32/64gcv to see if they encounter issues when executing).
Are other people seeing similar errors/is this a known issue?
Patrick
[1]:
Executing on host:
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
-B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
-O3 -ftree-vectorize --param riscv-autovec-preference=scalable
-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffat-lto-objects
-fno-ident -S -o floating-point-mul-3.s (timeout = 600)
spawn -ignore SIGHUP
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
-B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
-O3 -ftree-vectorize --param riscv-autovec-preference=scalable
-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns
-fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffat-lto-objects
-fno-ident -S -o floating-point-mul-3.s
In file included from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h:2,
from
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c:4:
/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
fatal error: gnu/stubs-lp64d.h: No such file or directory
compilation terminated.
compiler exited with status 1
FAIL: gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c -O3
-ftree-vectorize --param riscv-autovec-preference=scalable (test for
excess errors)
On 9/19/23 04:26, Juzhe-Zhong wrote:
> Extend current VLA patterns with VLS modes.
>
> Regression all passed.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Extend VLS modes.
> * config/riscv/vector.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test.
> * gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test.
>
> ---
> gcc/config/riscv/autovec.md | 12 ++---
> gcc/config/riscv/vector.md | 20 +++----
> .../gcc.target/riscv/rvv/autovec/vls/def.h | 3 +-
> .../gcc.target/riscv/rvv/autovec/vls/neg-2.c | 52 +++++++++++++++++++
> 4 files changed, 70 insertions(+), 17 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 769ef6daa36..75ed7ae4f2e 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1031,9 +1031,9 @@
> ;; - vfneg.v/vfabs.v
> ;; -------------------------------------------------------------------------------
> (define_insn_and_split "<optab><mode>2"
> - [(set (match_operand:VF 0 "register_operand")
> - (any_float_unop_nofrm:VF
> - (match_operand:VF 1 "register_operand")))]
> + [(set (match_operand:V_VLSF 0 "register_operand")
> + (any_float_unop_nofrm:V_VLSF
> + (match_operand:V_VLSF 1 "register_operand")))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> @@ -1052,9 +1052,9 @@
> ;; - vfsqrt.v
> ;; -------------------------------------------------------------------------------
> (define_insn_and_split "<optab><mode>2"
> - [(set (match_operand:VF 0 "register_operand")
> - (any_float_unop:VF
> - (match_operand:VF 1 "register_operand")))]
> + [(set (match_operand:V_VLSF 0 "register_operand")
> + (any_float_unop:V_VLSF
> + (match_operand:V_VLSF 1 "register_operand")))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index f7f37da692a..f66ffebba24 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -6756,8 +6756,8 @@
> ;; -------------------------------------------------------------------------------
>
> (define_insn "@pred_<optab><mode>"
> - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
> - (if_then_else:VF
> + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
> + (if_then_else:V_VLSF
> (unspec:<VM>
> [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
> (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
> @@ -6768,9 +6768,9 @@
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)
> (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> - (any_float_unop:VF
> - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> + (any_float_unop:V_VLSF
> + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
> + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> "TARGET_VECTOR"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> @@ -6783,8 +6783,8 @@
> (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
>
> (define_insn "@pred_<optab><mode>"
> - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
> - (if_then_else:VF
> + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
> + (if_then_else:V_VLSF
> (unspec:<VM>
> [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
> (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
> @@ -6793,9 +6793,9 @@
> (match_operand 7 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> - (any_float_unop_nofrm:VF
> - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
> - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> + (any_float_unop_nofrm:V_VLSF
> + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
> + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
> "TARGET_VECTOR"
> "vf<insn>.v\t%0,%3%p1"
> [(set_attr "type" "<float_insn_type>")
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> index 5df90704885..d7b721b4e3e 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> @@ -1,4 +1,5 @@
> #include <stdint-gcc.h>
> +#include <math.h>
>
> typedef int8_t v1qi __attribute__ ((vector_size (1)));
> typedef int8_t v2qi __attribute__ ((vector_size (2)));
> @@ -210,7 +211,7 @@ typedef double v512df __attribute__ ((vector_size (4096)));
> PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b) \
> { \
> for (int i = 0; i < NUM; ++i) \
> - a[i] = OP b[i]; \
> + a[i] = OP (b[i]); \
> }
>
> #define DEF_CALL_VV(PREFIX, NUM, TYPE, CALL) \
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> new file mode 100644
> index 00000000000..c2ab0098afa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> @@ -0,0 +1,52 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
> +
> +#include "def.h"
> +
> +DEF_OP_V (neg, 2, _Float16, -)
> +DEF_OP_V (neg, 4, _Float16, -)
> +DEF_OP_V (neg, 8, _Float16, -)
> +DEF_OP_V (neg, 16, _Float16, -)
> +DEF_OP_V (neg, 32, _Float16, -)
> +DEF_OP_V (neg, 64, _Float16, -)
> +DEF_OP_V (neg, 128, _Float16, -)
> +DEF_OP_V (neg, 256, _Float16, -)
> +DEF_OP_V (neg, 512, _Float16, -)
> +DEF_OP_V (neg, 1024, _Float16, -)
> +DEF_OP_V (neg, 2048, _Float16, -)
> +
> +DEF_OP_V (neg, 2, float, -)
> +DEF_OP_V (neg, 4, float, -)
> +DEF_OP_V (neg, 8, float, -)
> +DEF_OP_V (neg, 16, float, -)
> +DEF_OP_V (neg, 32, float, -)
> +DEF_OP_V (neg, 64, float, -)
> +DEF_OP_V (neg, 128, float, -)
> +DEF_OP_V (neg, 256, float, -)
> +DEF_OP_V (neg, 512, float, -)
> +DEF_OP_V (neg, 1024, float, -)
> +
> +DEF_OP_V (neg, 2, double, -)
> +DEF_OP_V (neg, 4, double, -)
> +DEF_OP_V (neg, 8, double, -)
> +DEF_OP_V (neg, 16, double, -)
> +DEF_OP_V (neg, 32, double, -)
> +DEF_OP_V (neg, 64, double, -)
> +DEF_OP_V (neg, 128, double, -)
> +DEF_OP_V (neg, 256, double, -)
> +DEF_OP_V (neg, 512, double, -)
> +
> +/* { dg-final { scan-assembler-times {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
> +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */
> +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-20 0:54 ` juzhe.zhong
@ 2023-09-20 1:12 ` Patrick O'Neill
2023-09-20 17:47 ` Patrick O'Neill
0 siblings, 1 reply; 13+ messages in thread
From: Patrick O'Neill @ 2023-09-20 1:12 UTC (permalink / raw)
To: juzhe.zhong, kito.cheng
Cc: Robin Dapp, gcc-patches, Kito.cheng, jeffreyalaw, palmer,
Edwin Lu, joern.rennecke, jeremy.bennett, gnu-toolchain
[-- Attachment #1: Type: text/plain, Size: 19471 bytes --]
I'll let it run overnight and see if this helps. Even before this patch,
I was seeing 233 stubs related failures for rv32gcv and 7 for rv64gcv so
this won't fix all the issues.
It's easily replicated using upstream riscv-gnu-toolchain
git clone https://github.com/riscv-collab/riscv-gnu-toolchain
cd riscv-gnu-toolchain
git submodule update --init gcc
cd gcc
git pull master
cd ..
mkdir build
cd build
../configure --prefix=$(pwd) --with-arch=rv32gcv --with-abi=ilp32d
make report-linux -j32
Then search for "stubs" in the debug logs
(/build-gcc-linux-stage2/gcc/testsuite/*.log)
Patrick
On 9/19/23 17:54, juzhe.zhong@rivai.ai wrote:
> I think we could remove match.h.
>
> Hi, @Patrick. Could you verify it?
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> index 2292372d7a3..674098e9ba6 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> @@ -1,5 +1,4 @@
> #include <stdint-gcc.h>
> -#include <math.h>
>
> and commit it.
>
> Thanks.
> ------------------------------------------------------------------------
> juzhe.zhong@rivai.ai
>
> *From:* Kito Cheng <mailto:kito.cheng@gmail.com>
> *Date:* 2023-09-20 08:52
> *To:* 钟居哲 <mailto:juzhe.zhong@rivai.ai>
> *CC:* Patrick O'Neill <mailto:patrick@rivosinc.com>; Robin Dapp
> <mailto:rdapp.gcc@gmail.com>; gcc-patches
> <mailto:gcc-patches@gcc.gnu.org>; Kito.cheng
> <mailto:kito.cheng@sifive.com>; jeffreyalaw
> <mailto:jeffreyalaw@gmail.com>; palmer
> <mailto:palmer@rivosinc.com>; Edwin Lu <mailto:ewlu@rivosinc.com>;
> joern.rennecke <mailto:joern.rennecke@embecosm.com>;
> jeremy.bennett <mailto:jeremy.bennett@embecosm.com>; gnu-toolchain
> <mailto:gnu-toolchain@rivosinc.com>
> *Subject:* Re: Re: [Committed] RISC-V: Support VLS unary
> floating-point patterns
> It seems because math.h, similar issue as stdint.h, does math.h
> necessary for the test case?
>
> juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> 於 2023年9月20日 週三
> 08:44 寫道：
>
> I didn't see this issue.
> They should be the bogus FAILs.
> We should either fix testcases or ignore them.
>
> ------------------------------------------------------------------------
> juzhe.zhong@rivai.ai
>
> *From:* Patrick O'Neill <mailto:patrick@rivosinc.com>
> *Date:* 2023-09-20 08:34
> *To:* Juzhe-Zhong <mailto:juzhe.zhong@rivai.ai>; Robin
> Dapp <mailto:rdapp.gcc@gmail.com>; gcc-patches
> <mailto:gcc-patches@gcc.gnu.org>
> *CC:* kito.cheng <mailto:kito.cheng@gmail.com>; kito.cheng
> <mailto:kito.cheng@sifive.com>; jeffreyalaw
> <mailto:jeffreyalaw@gmail.com>; Palmer Dabbelt
> <mailto:palmer@rivosinc.com>; Edwin Lu
> <mailto:ewlu@rivosinc.com>; joern.rennecke
> <mailto:joern.rennecke@embecosm.com>; jeremy.bennett
> <mailto:jeremy.bennett@embecosm.com>; gnu-toolchain
> <mailto:gnu-toolchain@rivosinc.com>
> *Subject:* Re: [Committed] RISC-V: Support VLS unary
> floating-point patterns
> Hi,
> This patch highlights an issue Edwin and I have been
> having with the
> testsuite where rv64 testcases are run when testing rv32gcv.
> There's a large number of new failures in the rv32gcv
> testsuite from
> this seemingly innocuous patch.
> https://github.com/ewlu/riscv-gnu-toolchain/issues/166
> (The repo is still a WIP - eventually will be non-gating
> patchworks
> pre-commit CI)
> From Edwin and my investigation the failures for rv32gcv
> look like [1].
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
>
> fatal error: gnu/stubs-lp64d.h: No such file or directory
> compilation terminated.
> Top of the failing testcase:
> /* { dg-do compile } */
> /* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
> -fno-schedule-insns -fno-schedule-insns2
> --param=riscv-autovec-lmul=m8" } */
> #include "def.h"
> The dg-options explicitly set rv64gcv, so I don't think
> this testcase
> should even be executed.
> For the 3 new failures on rv64gcv, they all explicitly set
> rv32gcv.
> /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
> These are seen on non-multilib builds. Multilib rv32/64gc
> does not
> appear to have the same issue when compiling (we're
> currently testing
> multilib rv32/64gcv to see if they encounter issues when
> executing).
> Are other people seeing similar errors/is this a known issue?
> Patrick
> [1]:
> Executing on host:
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
>
> -B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
>
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
>
> -march=rv32gcv -mabi=ilp32d -mcmodel=medlow
> -fdiagnostics-plain-output
> -O3 -ftree-vectorize --param
> riscv-autovec-preference=scalable
> -march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
> -fno-schedule-insns
> -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
> -ffat-lto-objects
> -fno-ident -S -o floating-point-mul-3.s (timeout = 600)
> spawn -ignore SIGHUP
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
>
> -B/home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
>
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c
>
> -march=rv32gcv -mabi=ilp32d -mcmodel=medlow
> -fdiagnostics-plain-output
> -O3 -ftree-vectorize --param
> riscv-autovec-preference=scalable
> -march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3
> -fno-schedule-insns
> -fno-schedule-insns2 --param=riscv-autovec-lmul=m8
> -ffat-lto-objects
> -fno-ident -S -o floating-point-mul-3.s
> In file included from
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
> from
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
> from
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
> from
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h:2,
> from
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c:4:
> /home/runner/work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
>
> fatal error: gnu/stubs-lp64d.h: No such file or directory
> compilation terminated.
> compiler exited with status 1
> FAIL:
> gcc.target/riscv/rvv/autovec/vls/floating-point-mul-3.c -O3
> -ftree-vectorize --param riscv-autovec-preference=scalable
> (test for
> excess errors)
> On 9/19/23 04:26, Juzhe-Zhong wrote:
> > Extend current VLA patterns with VLS modes.
> >
> > Regression all passed.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/autovec.md: Extend VLS modes.
> > * config/riscv/vector.md: Ditto.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test.
> > * gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test.
> >
> > ---
> > gcc/config/riscv/autovec.md | 12 ++---
> > gcc/config/riscv/vector.md | 20 +++----
> > .../gcc.target/riscv/rvv/autovec/vls/def.h | 3 +-
> > .../gcc.target/riscv/rvv/autovec/vls/neg-2.c | 52
> +++++++++++++++++++
> > 4 files changed, 70 insertions(+), 17 deletions(-)
> > create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> >
> > diff --git a/gcc/config/riscv/autovec.md
> b/gcc/config/riscv/autovec.md
> > index 769ef6daa36..75ed7ae4f2e 100644
> > --- a/gcc/config/riscv/autovec.md
> > +++ b/gcc/config/riscv/autovec.md
> > @@ -1031,9 +1031,9 @@
> > ;; - vfneg.v/vfabs.v
> > ;;
> -------------------------------------------------------------------------------
> > (define_insn_and_split "<optab><mode>2"
> > - [(set (match_operand:VF 0 "register_operand")
> > - (any_float_unop_nofrm:VF
> > - (match_operand:VF 1 "register_operand")))]
> > + [(set (match_operand:V_VLSF 0 "register_operand")
> > + (any_float_unop_nofrm:V_VLSF
> > + (match_operand:V_VLSF 1 "register_operand")))]
> > "TARGET_VECTOR && can_create_pseudo_p ()"
> > "#"
> > "&& 1"
> > @@ -1052,9 +1052,9 @@
> > ;; - vfsqrt.v
> > ;;
> -------------------------------------------------------------------------------
> > (define_insn_and_split "<optab><mode>2"
> > - [(set (match_operand:VF 0 "register_operand")
> > - (any_float_unop:VF
> > - (match_operand:VF 1 "register_operand")))]
> > + [(set (match_operand:V_VLSF 0 "register_operand")
> > + (any_float_unop:V_VLSF
> > + (match_operand:V_VLSF 1 "register_operand")))]
> > "TARGET_VECTOR && can_create_pseudo_p ()"
> > "#"
> > "&& 1"
> > diff --git a/gcc/config/riscv/vector.md
> b/gcc/config/riscv/vector.md
> > index f7f37da692a..f66ffebba24 100644
> > --- a/gcc/config/riscv/vector.md
> > +++ b/gcc/config/riscv/vector.md
> > @@ -6756,8 +6756,8 @@
> > ;;
> -------------------------------------------------------------------------------
> >
> > (define_insn "@pred_<optab><mode>"
> > - [(set (match_operand:VF 0
> "register_operand" "=vd, vd, vr, vr")
> > - (if_then_else:VF
> > + [(set (match_operand:V_VLSF 0
> "register_operand" "=vd, vd, vr, vr")
> > + (if_then_else:V_VLSF
> > (unspec:<VM>
> > [(match_operand:<VM> 1 "vector_mask_operand" " vm,
> vm,Wc1,Wc1")
> > (match_operand 4 "vector_length_operand" " rK,
> rK, rK, rK")
> > @@ -6768,9 +6768,9 @@
> > (reg:SI VL_REGNUM)
> > (reg:SI VTYPE_REGNUM)
> > (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> > - (any_float_unop:VF
> > - (match_operand:VF 3 "register_operand" " vr,
> vr, vr, vr"))
> > - (match_operand:VF 2 "vector_merge_operand" "
> vu, 0, vu, 0")))]
> > + (any_float_unop:V_VLSF
> > + (match_operand:V_VLSF 3 "register_operand" "
> vr, vr, vr, vr"))
> > + (match_operand:V_VLSF 2 "vector_merge_operand" "
> vu, 0, vu, 0")))]
> > "TARGET_VECTOR"
> > "vf<insn>.v\t%0,%3%p1"
> > [(set_attr "type" "<float_insn_type>")
> > @@ -6783,8 +6783,8 @@
> > (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
> >
> > (define_insn "@pred_<optab><mode>"
> > - [(set (match_operand:VF 0
> "register_operand" "=vd, vd, vr, vr")
> > - (if_then_else:VF
> > + [(set (match_operand:V_VLSF 0
> "register_operand" "=vd, vd, vr, vr")
> > + (if_then_else:V_VLSF
> > (unspec:<VM>
> > [(match_operand:<VM> 1 "vector_mask_operand" " vm,
> vm,Wc1,Wc1")
> > (match_operand 4 "vector_length_operand" " rK,
> rK, rK, rK")
> > @@ -6793,9 +6793,9 @@
> > (match_operand 7 "const_int_operand" "
> i, i, i, i")
> > (reg:SI VL_REGNUM)
> > (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> > - (any_float_unop_nofrm:VF
> > - (match_operand:VF 3 "register_operand" " vr,
> vr, vr, vr"))
> > - (match_operand:VF 2 "vector_merge_operand" "
> vu, 0, vu, 0")))]
> > + (any_float_unop_nofrm:V_VLSF
> > + (match_operand:V_VLSF 3 "register_operand" "
> vr, vr, vr, vr"))
> > + (match_operand:V_VLSF 2 "vector_merge_operand" "
> vu, 0, vu, 0")))]
> > "TARGET_VECTOR"
> > "vf<insn>.v\t%0,%3%p1"
> > [(set_attr "type" "<float_insn_type>")
> > diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> > index 5df90704885..d7b721b4e3e 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> > @@ -1,4 +1,5 @@
> > #include <stdint-gcc.h>
> > +#include <math.h>
> >
> > typedef int8_t v1qi __attribute__ ((vector_size (1)));
> > typedef int8_t v2qi __attribute__ ((vector_size (2)));
> > @@ -210,7 +211,7 @@ typedef double v512df __attribute__
> ((vector_size (4096)));
> > PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE
> *restrict b) \
> > { \
> > for (int i = 0; i < NUM; ++i) \
> > - a[i] = OP b[i]; \
> > + a[i] = OP (b[i]); \
> > }
> >
> > #define DEF_CALL_VV(PREFIX, NUM, TYPE,
> CALL) \
> > diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> > new file mode 100644
> > index 00000000000..c2ab0098afa
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/neg-2.c
> > @@ -0,0 +1,52 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b
> -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2
> --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */
> > +
> > +#include "def.h"
> > +
> > +DEF_OP_V (neg, 2, _Float16, -)
> > +DEF_OP_V (neg, 4, _Float16, -)
> > +DEF_OP_V (neg, 8, _Float16, -)
> > +DEF_OP_V (neg, 16, _Float16, -)
> > +DEF_OP_V (neg, 32, _Float16, -)
> > +DEF_OP_V (neg, 64, _Float16, -)
> > +DEF_OP_V (neg, 128, _Float16, -)
> > +DEF_OP_V (neg, 256, _Float16, -)
> > +DEF_OP_V (neg, 512, _Float16, -)
> > +DEF_OP_V (neg, 1024, _Float16, -)
> > +DEF_OP_V (neg, 2048, _Float16, -)
> > +
> > +DEF_OP_V (neg, 2, float, -)
> > +DEF_OP_V (neg, 4, float, -)
> > +DEF_OP_V (neg, 8, float, -)
> > +DEF_OP_V (neg, 16, float, -)
> > +DEF_OP_V (neg, 32, float, -)
> > +DEF_OP_V (neg, 64, float, -)
> > +DEF_OP_V (neg, 128, float, -)
> > +DEF_OP_V (neg, 256, float, -)
> > +DEF_OP_V (neg, 512, float, -)
> > +DEF_OP_V (neg, 1024, float, -)
> > +
> > +DEF_OP_V (neg, 2, double, -)
> > +DEF_OP_V (neg, 4, double, -)
> > +DEF_OP_V (neg, 8, double, -)
> > +DEF_OP_V (neg, 16, double, -)
> > +DEF_OP_V (neg, 32, double, -)
> > +DEF_OP_V (neg, 64, double, -)
> > +DEF_OP_V (neg, 128, double, -)
> > +DEF_OP_V (neg, 256, double, -)
> > +DEF_OP_V (neg, 512, double, -)
> > +
> > +/* { dg-final { scan-assembler-times
> {vfneg\.v\s+v[0-9]+,\s*v[0-9]+} 30 } } */
> > +/* { dg-final { scan-assembler-not {csrr} } } */
> > +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "16,16" "optimized"
> } } */
> > +/* { dg-final { scan-tree-dump-not "32,32" "optimized"
> } } */
> > +/* { dg-final { scan-tree-dump-not "64,64" "optimized"
> } } */
> > +/* { dg-final { scan-tree-dump-not "128,128"
> "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "256,256"
> "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "512,512"
> "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "1024,1024"
> "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "2048,2048"
> "optimized" } } */
> > +/* { dg-final { scan-tree-dump-not "4096,4096"
> "optimized" } } */
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-20 1:12 ` Patrick O'Neill
@ 2023-09-20 17:47 ` Patrick O'Neill
2023-09-20 22:00 ` 钟居哲
2023-09-21 10:20 ` Palmer Dabbelt
0 siblings, 2 replies; 13+ messages in thread
From: Patrick O'Neill @ 2023-09-20 17:47 UTC (permalink / raw)
To: juzhe.zhong
Cc: Robin Dapp, gcc-patches, Kito.cheng, jeffreyalaw, palmer,
Edwin Lu, joern.rennecke, jeremy.bennett, gnu-toolchain,
Kito Cheng
[-- Attachment #1: Type: text/plain, Size: 4756 bytes --]
Juzhe,
On a more general note, are we expecting #include <math.h> to cause a
testcase to fail?
My motivation is to make the testsuite less noisy when checking for
regressions. For example, a patch like this one:
https://patchwork.sourceware.org/project/gcc/patch/20230920023059.1728132-1-pan2.li@intel.com/
is showing 4 new failures on rv32gcv from the {dg-do compile} testcases
that #include <math.h>. I might be wrong, but those don't look like real
failures to me [1][2][3].
On glibc rv64gcv I'm seeing tests like:
gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
fail with similar missing stubs-ilp32d.h errors.
I want to sanity-check with other people that they are seeing similar
errors and that these errors indicate something wrong with the testsuite.
If nobody else is seeing these errors, I'd like to hear how you're
running the testsuite so I can debug the riscv-gnu-toolchain repo.
Patrick
[1]:
Executing on host:
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
-B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
-O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fno-vect-cost-model -ffast-math -fno-schedule-insns
-fno-schedule-insns2 -S -o math-ceil-1.s (timeout = 600)
spawn -ignore SIGHUP
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
-B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
-march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
-O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fno-vect-cost-model -ffast-math -fno-schedule-insns
-fno-schedule-insns2 -S -o math-ceil-1.s
In file included from
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
from
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
from
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
from
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h:1,
from
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c:5:
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
fatal error: gnu/stubs-lp64d.h: No such file or directory
compilation terminated.
compiler exited with status 1
FAIL: gcc.target/riscv/rvv/autovec/math-ceil-1.c -O3 -ftree-vectorize
(test for excess errors)
[2]:
https://github.com/ewlu/riscv-gnu-toolchain/issues/170
[3]:
This also extends beyond math.h. I'm seeing similar failures for
testcases like
gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c that
#include <stdint.h>.
On 9/19/23 18:12, Patrick O'Neill wrote:
>
> I'll let it run overnight and see if this helps. Even before this patch,
> I was seeing 233 stubs related failures for rv32gcv and 7 for rv64gcv so
> this won't fix all the issues.
>
> It's easily replicated using upstream riscv-gnu-toolchain
> git clone https://github.com/riscv-collab/riscv-gnu-toolchain
> cd riscv-gnu-toolchain
> git submodule update --init gcc
> cd gcc
> git pull master
> cd ..
> mkdir build
> cd build
> ../configure --prefix=$(pwd) --with-arch=rv32gcv --with-abi=ilp32d
> make report-linux -j32
>
> Then search for "stubs" in the debug logs
> (/build-gcc-linux-stage2/gcc/testsuite/*.log)
>
> Patrick
>
> On 9/19/23 17:54, juzhe.zhong@rivai.ai wrote:
>> I think we could remove match.h.
>>
>> Hi, @Patrick. Could you verify it?
>>
>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>> index 2292372d7a3..674098e9ba6 100644
>> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>> @@ -1,5 +1,4 @@
>> #include <stdint-gcc.h>
>> -#include <math.h>
>>
>> and commit it.
>>
>> Thanks.
>> ------------------------------------------------------------------------
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-20 17:47 ` Patrick O'Neill
@ 2023-09-20 22:00 ` 钟居哲
2023-09-21 10:20 ` Palmer Dabbelt
1 sibling, 0 replies; 13+ messages in thread
From: 钟居哲 @ 2023-09-20 22:00 UTC (permalink / raw)
To: patrick
Cc: rdapp.gcc, gcc-patches, kito.cheng, Jeff Law, palmer, ewlu,
Joern Rennecke, jeremy.bennett, gnu-toolchain
[-- Attachment #1: Type: text/plain, Size: 5177 bytes --]
>> On a more general note, are we expecting #include <math.h> to cause a
>> testcase to fail?
Well, actually I am not familiar with this stuff.
We include match.h is because we need it.
For example, CEIL/FLOOR,...etc.
I don't know how to avoid those bogus failures.
juzhe.zhong@rivai.ai
From: Patrick O'Neill
Date: 2023-09-21 01:47
To: juzhe.zhong@rivai.ai
CC: Robin Dapp; gcc-patches; Kito.cheng; jeffreyalaw; palmer; Edwin Lu; joern.rennecke; jeremy.bennett; gnu-toolchain; Kito Cheng
Subject: Re: [Committed] RISC-V: Support VLS unary floating-point patterns
Juzhe,
On a more general note, are we expecting #include <math.h> to cause a
testcase to fail?
My motivation is to make the testsuite less noisy when checking for
regressions. For example, a patch like this one:
https://patchwork.sourceware.org/project/gcc/patch/20230920023059.1728132-1-pan2.li@intel.com/
is showing 4 new failures on rv32gcv from the {dg-do compile} testcases
that #include <math.h>. I might be wrong, but those don't look like real
failures to me [1][2][3].
On glibc rv64gcv I'm seeing tests like:
gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
fail with similar missing stubs-ilp32d.h errors.
I want to sanity-check with other people that they are seeing similar
errors and that these errors indicate something wrong with the testsuite.
If nobody else is seeing these errors, I'd like to hear how you're
running the testsuite so I can debug the riscv-gnu-toolchain repo.
Patrick
[1]:
Executing on host: /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2 -S -o math-ceil-1.s (timeout = 600)
spawn -ignore SIGHUP /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/ /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2 -S -o math-ceil-1.s
In file included from /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
from /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
from /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
from /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h:1,
from /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c:5:
/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11: fatal error: gnu/stubs-lp64d.h: No such file or directory
compilation terminated.
compiler exited with status 1
FAIL: gcc.target/riscv/rvv/autovec/math-ceil-1.c -O3 -ftree-vectorize (test for excess errors)
[2]:
https://github.com/ewlu/riscv-gnu-toolchain/issues/170
[3]:
This also extends beyond math.h. I'm seeing similar failures for
testcases like
gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c that
#include <stdint.h>.
On 9/19/23 18:12, Patrick O'Neill wrote:
I'll let it run overnight and see if this helps. Even before this patch,
I was seeing 233 stubs related failures for rv32gcv and 7 for rv64gcv so
this won't fix all the issues.
It's easily replicated using upstream riscv-gnu-toolchain
git clone https://github.com/riscv-collab/riscv-gnu-toolchain
cd riscv-gnu-toolchain
git submodule update --init gcc
cd gcc
git pull master
cd ..
mkdir build
cd build
../configure --prefix=$(pwd) --with-arch=rv32gcv --with-abi=ilp32d
make report-linux -j32
Then search for "stubs" in the debug logs (/build-gcc-linux-stage2/gcc/testsuite/*.log)
Patrick
On 9/19/23 17:54, juzhe.zhong@rivai.ai wrote:
I think we could remove match.h.
Hi, @Patrick. Could you verify it?
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index 2292372d7a3..674098e9ba6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -1,5 +1,4 @@
#include <stdint-gcc.h>
-#include <math.h>
and commit it.
Thanks.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-20 17:47 ` Patrick O'Neill
2023-09-20 22:00 ` 钟居哲
@ 2023-09-21 10:20 ` Palmer Dabbelt
2023-09-21 11:24 ` Kito Cheng
2023-09-21 16:14 ` Patrick O'Neill
1 sibling, 2 replies; 13+ messages in thread
From: Palmer Dabbelt @ 2023-09-21 10:20 UTC (permalink / raw)
To: Patrick O'Neill
Cc: juzhe.zhong, rdapp.gcc, gcc-patches, kito.cheng, jeffreyalaw,
ewlu, joern.rennecke, jeremy.bennett, gnu-toolchain, kito.cheng
On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
> Juzhe,
>
> On a more general note, are we expecting #include <math.h> to cause a
> testcase to fail?
>
> My motivation is to make the testsuite less noisy when checking for
> regressions. For example, a patch like this one:
> https://patchwork.sourceware.org/project/gcc/patch/20230920023059.1728132-1-pan2.li@intel.com/
> is showing 4 new failures on rv32gcv from the {dg-do compile} testcases
> that #include <math.h>. I might be wrong, but those don't look like real
> failures to me [1][2][3].
>
> On glibc rv64gcv I'm seeing tests like:
> gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
> fail with similar missing stubs-ilp32d.h errors.
>
> I want to sanity-check with other people that they are seeing similar
> errors and that these errors indicate something wrong with the testsuite.
> If nobody else is seeing these errors, I'd like to hear how you're
> running the testsuite so I can debug the riscv-gnu-toolchain repo.
>
> Patrick
>
> [1]:
> Executing on host:
> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
> -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
> -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
> -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
> -fno-vect-cost-model -ffast-math -fno-schedule-insns
> -fno-schedule-insns2 -S -o math-ceil-1.s (timeout = 600)
> spawn -ignore SIGHUP
> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
> -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
> -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
> -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
> -fno-vect-cost-model -ffast-math -fno-schedule-insns
> -fno-schedule-insns2 -S -o math-ceil-1.s
> In file included from
> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
> from
> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
> from
> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
> from
> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h:1,
> from
> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c:5:
> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
> fatal error: gnu/stubs-lp64d.h: No such file or directory
That looks like a toolchain build/configuration issue, not a test issue.
IIRC this comes up from time to time, something's probably broken in
riscv-gnu-toolchain but I'm not sure what's wrong.
I get a working setup with just `./configure --enable-linux
--disable-multilib` and the latest riscv-gnu-toolchain master. How are
you building things?
> compilation terminated.
> compiler exited with status 1
> FAIL: gcc.target/riscv/rvv/autovec/math-ceil-1.c -O3 -ftree-vectorize
> (test for excess errors)
>
> [2]:
> https://github.com/ewlu/riscv-gnu-toolchain/issues/170
>
> [3]:
> This also extends beyond math.h. I'm seeing similar failures for
> testcases like
> gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c that
> #include <stdint.h>.
>
>
> On 9/19/23 18:12, Patrick O'Neill wrote:
>>
>> I'll let it run overnight and see if this helps. Even before this patch,
>> I was seeing 233 stubs related failures for rv32gcv and 7 for rv64gcv so
>> this won't fix all the issues.
>>
>> It's easily replicated using upstream riscv-gnu-toolchain
>> git clone https://github.com/riscv-collab/riscv-gnu-toolchain
>> cd riscv-gnu-toolchain
>> git submodule update --init gcc
>> cd gcc
>> git pull master
>> cd ..
>> mkdir build
>> cd build
>> ../configure --prefix=$(pwd) --with-arch=rv32gcv --with-abi=ilp32d
>> make report-linux -j32
>>
>> Then search for "stubs" in the debug logs
>> (/build-gcc-linux-stage2/gcc/testsuite/*.log)
>>
>> Patrick
>>
>> On 9/19/23 17:54, juzhe.zhong@rivai.ai wrote:
>>> I think we could remove match.h.
>>>
>>> Hi, @Patrick. Could you verify it?
>>>
>>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>>> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>>> index 2292372d7a3..674098e9ba6 100644
>>> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>>> @@ -1,5 +1,4 @@
>>> #include <stdint-gcc.h>
>>> -#include <math.h>
>>>
>>> and commit it.
>>>
>>> Thanks.
>>> ------------------------------------------------------------------------
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-21 10:20 ` Palmer Dabbelt
@ 2023-09-21 11:24 ` Kito Cheng
2023-09-21 11:26 ` Palmer Dabbelt
2023-09-21 16:14 ` Patrick O'Neill
1 sibling, 1 reply; 13+ messages in thread
From: Kito Cheng @ 2023-09-21 11:24 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Patrick O'Neill, juzhe.zhong, rdapp.gcc, gcc-patches,
jeffreyalaw, ewlu, joern.rennecke, jeremy.bennett, gnu-toolchain
GCC has built in function[1] for those math function stuff, e.g.
__builtin_ceilf, so we don't really need math.h :)
[1] https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
On Thu, Sep 21, 2023 at 11:20 AM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
> > Juzhe,
> >
> > On a more general note, are we expecting #include <math.h> to cause a
> > testcase to fail?
> >
> > My motivation is to make the testsuite less noisy when checking for
> > regressions. For example, a patch like this one:
> > https://patchwork.sourceware.org/project/gcc/patch/20230920023059.1728132-1-pan2.li@intel.com/
> > is showing 4 new failures on rv32gcv from the {dg-do compile} testcases
> > that #include <math.h>. I might be wrong, but those don't look like real
> > failures to me [1][2][3].
> >
> > On glibc rv64gcv I'm seeing tests like:
> > gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
> > fail with similar missing stubs-ilp32d.h errors.
> >
> > I want to sanity-check with other people that they are seeing similar
> > errors and that these errors indicate something wrong with the testsuite.
> > If nobody else is seeing these errors, I'd like to hear how you're
> > running the testsuite so I can debug the riscv-gnu-toolchain repo.
> >
> > Patrick
> >
> > [1]:
> > Executing on host:
> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
> > -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
> > -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
> > -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
> > -fno-vect-cost-model -ffast-math -fno-schedule-insns
> > -fno-schedule-insns2 -S -o math-ceil-1.s (timeout = 600)
> > spawn -ignore SIGHUP
> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
> > -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
> > -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
> > -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
> > -fno-vect-cost-model -ffast-math -fno-schedule-insns
> > -fno-schedule-insns2 -S -o math-ceil-1.s
> > In file included from
> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
> > from
> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
> > from
> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
> > from
> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h:1,
> > from
> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c:5:
> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
> > fatal error: gnu/stubs-lp64d.h: No such file or directory
>
> That looks like a toolchain build/configuration issue, not a test issue.
> IIRC this comes up from time to time, something's probably broken in
> riscv-gnu-toolchain but I'm not sure what's wrong.
>
> I get a working setup with just `./configure --enable-linux
> --disable-multilib` and the latest riscv-gnu-toolchain master. How are
> you building things?
>
> > compilation terminated.
> > compiler exited with status 1
> > FAIL: gcc.target/riscv/rvv/autovec/math-ceil-1.c -O3 -ftree-vectorize
> > (test for excess errors)
> >
> > [2]:
> > https://github.com/ewlu/riscv-gnu-toolchain/issues/170
> >
> > [3]:
> > This also extends beyond math.h. I'm seeing similar failures for
> > testcases like
> > gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c that
> > #include <stdint.h>.
> >
> >
> > On 9/19/23 18:12, Patrick O'Neill wrote:
> >>
> >> I'll let it run overnight and see if this helps. Even before this patch,
> >> I was seeing 233 stubs related failures for rv32gcv and 7 for rv64gcv so
> >> this won't fix all the issues.
> >>
> >> It's easily replicated using upstream riscv-gnu-toolchain
> >> git clone https://github.com/riscv-collab/riscv-gnu-toolchain
> >> cd riscv-gnu-toolchain
> >> git submodule update --init gcc
> >> cd gcc
> >> git pull master
> >> cd ..
> >> mkdir build
> >> cd build
> >> ../configure --prefix=$(pwd) --with-arch=rv32gcv --with-abi=ilp32d
> >> make report-linux -j32
> >>
> >> Then search for "stubs" in the debug logs
> >> (/build-gcc-linux-stage2/gcc/testsuite/*.log)
> >>
> >> Patrick
> >>
> >> On 9/19/23 17:54, juzhe.zhong@rivai.ai wrote:
> >>> I think we could remove match.h.
> >>>
> >>> Hi, @Patrick. Could you verify it?
> >>>
> >>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> >>> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> >>> index 2292372d7a3..674098e9ba6 100644
> >>> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> >>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
> >>> @@ -1,5 +1,4 @@
> >>> #include <stdint-gcc.h>
> >>> -#include <math.h>
> >>>
> >>> and commit it.
> >>>
> >>> Thanks.
> >>> ------------------------------------------------------------------------
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-21 11:24 ` Kito Cheng
@ 2023-09-21 11:26 ` Palmer Dabbelt
0 siblings, 0 replies; 13+ messages in thread
From: Palmer Dabbelt @ 2023-09-21 11:26 UTC (permalink / raw)
To: kito.cheng
Cc: Patrick O'Neill, juzhe.zhong, rdapp.gcc, gcc-patches,
jeffreyalaw, ewlu, joern.rennecke, jeremy.bennett, gnu-toolchain
On Thu, 21 Sep 2023 04:24:48 PDT (-0700), kito.cheng@sifive.com wrote:
> GCC has built in function[1] for those math function stuff, e.g.
> __builtin_ceilf, so we don't really need math.h :)
>
> [1] https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
That's probably the right way to go for the test suite. Something's
still wrong somewhere with Patrick's builds, though...
>
> On Thu, Sep 21, 2023 at 11:20 AM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>>
>> On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
>> > Juzhe,
>> >
>> > On a more general note, are we expecting #include <math.h> to cause a
>> > testcase to fail?
>> >
>> > My motivation is to make the testsuite less noisy when checking for
>> > regressions. For example, a patch like this one:
>> > https://patchwork.sourceware.org/project/gcc/patch/20230920023059.1728132-1-pan2.li@intel.com/
>> > is showing 4 new failures on rv32gcv from the {dg-do compile} testcases
>> > that #include <math.h>. I might be wrong, but those don't look like real
>> > failures to me [1][2][3].
>> >
>> > On glibc rv64gcv I'm seeing tests like:
>> > gcc.target/riscv/rvv/autovec/unop/vnot-rv32gcv.c
>> > fail with similar missing stubs-ilp32d.h errors.
>> >
>> > I want to sanity-check with other people that they are seeing similar
>> > errors and that these errors indicate something wrong with the testsuite.
>> > If nobody else is seeing these errors, I'd like to hear how you're
>> > running the testsuite so I can debug the riscv-gnu-toolchain repo.
>> >
>> > Patrick
>> >
>> > [1]:
>> > Executing on host:
>> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
>> > -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
>> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
>> > -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
>> > -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
>> > -fno-vect-cost-model -ffast-math -fno-schedule-insns
>> > -fno-schedule-insns2 -S -o math-ceil-1.s (timeout = 600)
>> > spawn -ignore SIGHUP
>> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
>> > -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
>> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
>> > -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
>> > -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
>> > -fno-vect-cost-model -ffast-math -fno-schedule-insns
>> > -fno-schedule-insns2 -S -o math-ceil-1.s
>> > In file included from
>> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
>> > from
>> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
>> > from
>> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
>> > from
>> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h:1,
>> > from
>> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c:5:
>> > /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
>> > fatal error: gnu/stubs-lp64d.h: No such file or directory
>>
>> That looks like a toolchain build/configuration issue, not a test issue.
>> IIRC this comes up from time to time, something's probably broken in
>> riscv-gnu-toolchain but I'm not sure what's wrong.
>>
>> I get a working setup with just `./configure --enable-linux
>> --disable-multilib` and the latest riscv-gnu-toolchain master. How are
>> you building things?
>>
>> > compilation terminated.
>> > compiler exited with status 1
>> > FAIL: gcc.target/riscv/rvv/autovec/math-ceil-1.c -O3 -ftree-vectorize
>> > (test for excess errors)
>> >
>> > [2]:
>> > https://github.com/ewlu/riscv-gnu-toolchain/issues/170
>> >
>> > [3]:
>> > This also extends beyond math.h. I'm seeing similar failures for
>> > testcases like
>> > gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c that
>> > #include <stdint.h>.
>> >
>> >
>> > On 9/19/23 18:12, Patrick O'Neill wrote:
>> >>
>> >> I'll let it run overnight and see if this helps. Even before this patch,
>> >> I was seeing 233 stubs related failures for rv32gcv and 7 for rv64gcv so
>> >> this won't fix all the issues.
>> >>
>> >> It's easily replicated using upstream riscv-gnu-toolchain
>> >> git clone https://github.com/riscv-collab/riscv-gnu-toolchain
>> >> cd riscv-gnu-toolchain
>> >> git submodule update --init gcc
>> >> cd gcc
>> >> git pull master
>> >> cd ..
>> >> mkdir build
>> >> cd build
>> >> ../configure --prefix=$(pwd) --with-arch=rv32gcv --with-abi=ilp32d
>> >> make report-linux -j32
>> >>
>> >> Then search for "stubs" in the debug logs
>> >> (/build-gcc-linux-stage2/gcc/testsuite/*.log)
>> >>
>> >> Patrick
>> >>
>> >> On 9/19/23 17:54, juzhe.zhong@rivai.ai wrote:
>> >>> I think we could remove match.h.
>> >>>
>> >>> Hi, @Patrick. Could you verify it?
>> >>>
>> >>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>> >>> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>> >>> index 2292372d7a3..674098e9ba6 100644
>> >>> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>> >>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
>> >>> @@ -1,5 +1,4 @@
>> >>> #include <stdint-gcc.h>
>> >>> -#include <math.h>
>> >>>
>> >>> and commit it.
>> >>>
>> >>> Thanks.
>> >>> ------------------------------------------------------------------------
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-21 10:20 ` Palmer Dabbelt
2023-09-21 11:24 ` Kito Cheng
@ 2023-09-21 16:14 ` Patrick O'Neill
2023-09-21 17:43 ` Patrick O'Neill
1 sibling, 1 reply; 13+ messages in thread
From: Patrick O'Neill @ 2023-09-21 16:14 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: juzhe.zhong, rdapp.gcc, gcc-patches, kito.cheng, jeffreyalaw,
ewlu, joern.rennecke, jeremy.bennett, gnu-toolchain
On 9/21/23 03:20, Palmer Dabbelt wrote:
> On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
>> ...
>>
>> [1]:
>> Executing on host:
>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
>>
>> -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
>>
>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
>>
>> -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
>> -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
>> -fno-vect-cost-model -ffast-math -fno-schedule-insns
>> -fno-schedule-insns2 -S -o math-ceil-1.s (timeout = 600)
>> spawn -ignore SIGHUP
>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
>>
>> -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
>>
>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
>>
>> -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
>> -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
>> -fno-vect-cost-model -ffast-math -fno-schedule-insns
>> -fno-schedule-insns2 -S -o math-ceil-1.s
>> In file included from
>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
>>
>> from
>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
>>
>> from
>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
>>
>> from
>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h:1,
>>
>> from
>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c:5:
>>
>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
>>
>> fatal error: gnu/stubs-lp64d.h: No such file or directory
>
> That looks like a toolchain build/configuration issue, not a test
> issue. IIRC this comes up from time to time, something's probably
> broken in riscv-gnu-toolchain but I'm not sure what's wrong.
>
> I get a working setup with just `./configure --enable-linux
> --disable-multilib` and the latest riscv-gnu-toolchain master. How are
> you building things?
I've kicked off a few builds to confirm but I use:
git clone https://github.com/riscv-collab/riscv-gnu-toolchain
cd riscv-gnu-toolchain
git submodule update --init gcc
cd gcc && git checkout master && cd ..
mkdir build && cd build
../configure --prefix=$(pwd) --with-arch=rv32gcv --with-abi=ilp32d
Make sure you bump gcc to tip of tree!
The latest riscv-gnu-toolchain master uses gcc 12.2 which doesn't have
the testcases that are failing (rvv folder):
https://github.com/gcc-mirror/gcc/tree/2ee5e4300186a92ad73f1a1a64cb918dc76c8d67/gcc/testsuite/gcc.target/riscv
The failures only show up for tests in:
gcc.target/riscv/rvv/
gcc.dg/vect/costmodel/riscv/rvv/
After bumping gcc and using your command (with --prefix)
../configure --enable-linux --disable-multilib --prefix=$(pwd)
I still get the missing stubs failures.
I've also tried this with the build directory both inside and outside
the repo and that doesn't make a difference.
Patrick
>
>> compilation terminated.
>> compiler exited with status 1
>> FAIL: gcc.target/riscv/rvv/autovec/math-ceil-1.c -O3 -ftree-vectorize
>> (test for excess errors)
>>
>> [2]:
>> https://github.com/ewlu/riscv-gnu-toolchain/issues/170
>>
>> [3]:
>> This also extends beyond math.h. I'm seeing similar failures for
>> testcases like
>> gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c that
>> #include <stdint.h>.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Committed] RISC-V: Support VLS unary floating-point patterns
2023-09-21 16:14 ` Patrick O'Neill
@ 2023-09-21 17:43 ` Patrick O'Neill
0 siblings, 0 replies; 13+ messages in thread
From: Patrick O'Neill @ 2023-09-21 17:43 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: juzhe.zhong, rdapp.gcc, gcc-patches, kito.cheng, jeffreyalaw,
ewlu, joern.rennecke, jeremy.bennett, gnu-toolchain
On 9/21/23 09:14, Patrick O'Neill wrote:
>
> On 9/21/23 03:20, Palmer Dabbelt wrote:
>> On Wed, 20 Sep 2023 10:47:23 PDT (-0700), Patrick O'Neill wrote:
>>> ...
>>>
>>> [1]:
>>> Executing on host:
>>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
>>>
>>> -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
>>>
>>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
>>>
>>> -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
>>> -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
>>> -fno-vect-cost-model -ffast-math -fno-schedule-insns
>>> -fno-schedule-insns2 -S -o math-ceil-1.s (timeout = 600)
>>> spawn -ignore SIGHUP
>>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/xgcc
>>>
>>> -B/github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/build-gcc-linux-stage2/gcc/
>>>
>>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c
>>>
>>> -march=rv32gcv -mabi=ilp32d -mcmodel=medlow -fdiagnostics-plain-output
>>> -O3 -ftree-vectorize -march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
>>> -fno-vect-cost-model -ffast-math -fno-schedule-insns
>>> -fno-schedule-insns2 -S -o math-ceil-1.s
>>> In file included from
>>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/features.h:515,
>>>
>>> from
>>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/bits/libc-header-start.h:33,
>>>
>>> from
>>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/math.h:27,
>>>
>>> from
>>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/test-math.h:1,
>>>
>>> from
>>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/math-ceil-1.c:5:
>>>
>>> /github/ewlu-runner-2/_work/riscv-gnu-toolchain/riscv-gnu-toolchain/build/sysroot/usr/include/gnu/stubs.h:17:11:
>>>
>>> fatal error: gnu/stubs-lp64d.h: No such file or directory
>>
>> That looks like a toolchain build/configuration issue, not a test
>> issue. IIRC this comes up from time to time, something's probably
>> broken in riscv-gnu-toolchain but I'm not sure what's wrong.
>>
>> I get a working setup with just `./configure --enable-linux
>> --disable-multilib` and the latest riscv-gnu-toolchain master. How
>> are you building things?
> I've kicked off a few builds to confirm but I use:
The non-multilib runs finished and still have issues.
The missing-stubs failures go away when building with multilib - so at
least now I have something to compare against :)
I'll dig into why and see what's needed for non-multilib tests to pass.
Patrick
>
> git clone https://github.com/riscv-collab/riscv-gnu-toolchain
> cd riscv-gnu-toolchain
> git submodule update --init gcc
> cd gcc && git checkout master && cd ..
> mkdir build && cd build
> ../configure --prefix=$(pwd) --with-arch=rv32gcv --with-abi=ilp32d
>
> Make sure you bump gcc to tip of tree!
> The latest riscv-gnu-toolchain master uses gcc 12.2 which doesn't have
> the testcases that are failing (rvv folder):
> https://github.com/gcc-mirror/gcc/tree/2ee5e4300186a92ad73f1a1a64cb918dc76c8d67/gcc/testsuite/gcc.target/riscv
>
>
> The failures only show up for tests in:
> gcc.target/riscv/rvv/
> gcc.dg/vect/costmodel/riscv/rvv/
>
> After bumping gcc and using your command (with --prefix)
> ../configure --enable-linux --disable-multilib --prefix=$(pwd)
> I still get the missing stubs failures.
>
> I've also tried this with the build directory both inside and outside
> the repo and that doesn't make a difference.
>
> Patrick
>
>>
>>> compilation terminated.
>>> compiler exited with status 1
>>> FAIL: gcc.target/riscv/rvv/autovec/math-ceil-1.c -O3 -ftree-vectorize
>>> (test for excess errors)
>>>
>>> [2]:
>>> https://github.com/ewlu/riscv-gnu-toolchain/issues/170
>>>
>>> [3]:
>>> This also extends beyond math.h. I'm seeing similar failures for
>>> testcases like
>>> gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c that
>>> #include <stdint.h>.
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2023-09-19 11:26 [Committed] RISC-V: Support VLS unary floating-point patterns Juzhe-Zhong
2023-09-20 0:34 ` Patrick O'Neill
2023-09-20 0:43 ` juzhe.zhong
2023-09-20 0:52 ` Kito Cheng
2023-09-20 0:54 ` juzhe.zhong
2023-09-20 1:12 ` Patrick O'Neill
2023-09-20 17:47 ` Patrick O'Neill
2023-09-20 22:00 ` 钟居哲
2023-09-21 10:20 ` Palmer Dabbelt
2023-09-21 11:24 ` Kito Cheng
2023-09-21 11:26 ` Palmer Dabbelt
2023-09-21 16:14 ` Patrick O'Neill
2023-09-21 17:43 ` Patrick O'Neill
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