From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by sourceware.org (Postfix) with ESMTPS id A7DD83858410 for ; Tue, 19 Sep 2023 15:07:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A7DD83858410 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-31f7400cb74so5143003f8f.2 for ; Tue, 19 Sep 2023 08:07:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1695136060; x=1695740860; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=coQ86Ki6T/9eu0flDxjTZX33wO9BfXKQqYgs3W9pDY8=; b=f+8tuI7Et66e5niLFvX8y700BNaJxof3VceiWtedVqRqr+jO+WqNJGfF9mI3wv9mF8 nmY/7+O6s0TeVnMiDCOicPnyLRQyPCivFk5aiDA1mRMS9kBoxJMGxWiyDunRb7EXTBTy 7r+J9Z2SO3G2BxhO5JO7dKFW7C+0T6EGuetANbVnj2Py3cscqTzInVS1URXtO0s5iXQq gCH+zPNrdMA8W8Q1pDG7SsBPGFCjd/dSztlE7g7tiW+vS8l47CeVxaKFo+h1AKRZqAEf SU7Zzktd729zHYiaEQfTUcOj6h9M9NNuyABYTVtUwnnHWyySlpdFWkVikWRL4zD7W3/g psfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695136060; x=1695740860; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=coQ86Ki6T/9eu0flDxjTZX33wO9BfXKQqYgs3W9pDY8=; b=UTE+6YmOWwX4ebhY8FEytCTIVS9JFLqyjH4fTTsOZWkz7yMGUfwGPyUQz42FsecTRH Ubh4HjruKuHLyhMlIRGV3R8NO7awNbu8EXHewwUR4783Hh3cRj3BgQ/xxDHuC7UekiNy Ib5cg0LfInpzMIOFuvB6So8m0dBFUOhgs24mSYfWe+6Dnu/LbqxHLKLDcr7SvYv9E+AX oYNU8Jwls/Ndof1XTK4En3SXrl/7yFtzfs0BF9/6ozGStFYXrFfG85CI7Mpiv2lgQNZh ujlO5jainiFN4qGjhjbagu3xP5GNKve7Ul5udQRdAOlfliZhKTPNg7xuygxQ5MP22nYy Ixuw== X-Gm-Message-State: AOJu0YwoHq82E2HAoj0Vz9YBvlksvTpkius+t5xVM8sQxwcvRjwONUzQ Yob6wyj0j4YezmnYuv7MOv2e0HLlUgHKry3jlEg= X-Google-Smtp-Source: AGHT+IEZmG30EfZy52RFEpyyEeJS8faJviZdkovC6Bd/qnOrU+QMuXSr2uFoYmrijBWcQBLyQC+KJQ== X-Received: by 2002:a05:6000:1942:b0:317:5d3d:c9df with SMTP id e2-20020a056000194200b003175d3dc9dfmr9379541wry.18.1695136059215; Tue, 19 Sep 2023 08:07:39 -0700 (PDT) Received: from troughton.sou.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id b17-20020a5d4d91000000b0031c855d52efsm15652996wru.87.2023.09.19.08.07.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Sep 2023 08:07:38 -0700 (PDT) From: Mary Bennett To: gcc-patches@gcc.gnu.org Subject: [PATCH 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Date: Tue, 19 Sep 2023 16:07:32 +0100 Message-Id: <20230919150734.2854664-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch series presents the comprehensive implementation of the MAC and ALU extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin RISC-V: Add support for XCValu extension in CV32E40P RISC-V: Add support for XCVmac extension in CV32E40P gcc/common/config/riscv/riscv-common.cc | 6 + gcc/config/riscv/constraints.md | 7 + gcc/config/riscv/corev.def | 43 ++ gcc/config/riscv/corev.md | 675 ++++++++++++++++++ gcc/config/riscv/predicates.md | 5 + gcc/config/riscv/riscv-builtins.cc | 13 + gcc/config/riscv/riscv-ftypes.def | 11 + gcc/config/riscv/riscv-opts.h | 7 + gcc/config/riscv/riscv.cc | 7 + gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/riscv.opt | 3 + gcc/doc/extend.texi | 174 +++++ .../gcc.target/riscv/cv-alu-compile.c | 252 +++++++ .../riscv/cv-alu-fail-compile-addn.c | 11 + .../riscv/cv-alu-fail-compile-addrn.c | 11 + .../riscv/cv-alu-fail-compile-addun.c | 11 + .../riscv/cv-alu-fail-compile-addurn.c | 11 + .../riscv/cv-alu-fail-compile-clip.c | 11 + .../riscv/cv-alu-fail-compile-clipu.c | 11 + .../riscv/cv-alu-fail-compile-subn.c | 11 + .../riscv/cv-alu-fail-compile-subrn.c | 11 + .../riscv/cv-alu-fail-compile-subun.c | 11 + .../riscv/cv-alu-fail-compile-suburn.c | 11 + .../gcc.target/riscv/cv-alu-fail-compile.c | 32 + .../gcc.target/riscv/cv-mac-compile.c | 198 +++++ .../riscv/cv-mac-fail-compile-mac.c | 25 + .../riscv/cv-mac-fail-compile-machhsn.c | 24 + .../riscv/cv-mac-fail-compile-machhsrn.c | 24 + .../riscv/cv-mac-fail-compile-machhun.c | 24 + .../riscv/cv-mac-fail-compile-machhurn.c | 24 + .../riscv/cv-mac-fail-compile-macsn.c | 24 + .../riscv/cv-mac-fail-compile-macsrn.c | 24 + .../riscv/cv-mac-fail-compile-macun.c | 24 + .../riscv/cv-mac-fail-compile-macurn.c | 24 + .../riscv/cv-mac-fail-compile-msu.c | 25 + .../riscv/cv-mac-fail-compile-mulhhsn.c | 24 + .../riscv/cv-mac-fail-compile-mulhhsrn.c | 24 + .../riscv/cv-mac-fail-compile-mulhhun.c | 24 + .../riscv/cv-mac-fail-compile-mulhhurn.c | 24 + .../riscv/cv-mac-fail-compile-mulsn.c | 24 + .../riscv/cv-mac-fail-compile-mulsrn.c | 24 + .../riscv/cv-mac-fail-compile-mulun.c | 24 + .../riscv/cv-mac-fail-compile-mulurn.c | 24 + .../riscv/cv-mac-test-autogeneration.c | 18 + gcc/testsuite/lib/target-supports.exp | 26 + 45 files changed, 2022 insertions(+) create mode 100644 gcc/config/riscv/corev.def create mode 100644 gcc/config/riscv/corev.md create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-msu.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-test-autogeneration.c -- 2.34.1