From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by sourceware.org (Postfix) with ESMTPS id 74D6B3858D20 for ; Wed, 20 Sep 2023 05:40:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 74D6B3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp72t1695188395tlzn2ffk Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 20 Sep 2023 13:39:54 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: q4jtFqBCDINDY4/mGhAQ9GAKk+f08vH9ji8rp8U+0GpTILDgPQDF8Wr+tR+i/ Ea0XSN0z+wnPoK/g4DIEOntJXuz4Zp9sL/jspiusGzhUIYylpfrGBc23phCgSvUlV2aHaIy MCnnjw+HIi50/tZ4PMDDWBVqbupUaEOLW+rMM6/0SbToby5Ez2YS1zw4vml5cFq97wjiUsA +NR5uDEK47BEJkgLgf1e2WaNq6Qt+tFOHRmBggeRZVuiK+SVtYY5M2FeUE6HgvwtGzzNMVD 82de0sOw4s7Lugpw5lEZjWK8v3Qd9A6i8q2rNYQNsLZgkHbtS9dBaie8yObpPZGTYoq1IJ/ /jJb5A5IVRikGwBetkGsiQrk+skhHjllZg8bykEzeo8k+zTPeQXlT+xcDRaHnrUWuDDynLx 18utl8iPqS8= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 13113648034046390395 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH] RISC-V: Fixed ICE caused by missing operand Date: Wed, 20 Sep 2023 13:39:54 +0800 Message-Id: <20230920053954.3454414-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This ICE appears in GCC compiled with -O2 flags. PR target/111488 gcc/ChangeLog: * config/riscv/autovec-opt.md: Add missed operand. --- gcc/config/riscv/autovec-opt.md | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index cef9f157e99..66c77ad6ebb 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -957,7 +957,8 @@ riscv_vector::emit_vlmax_insn (extend_icode, riscv_vector::UNARY_OP, extend_ops); - rtx ops[] = {operands[0], tmp, operands[3], operands[1]}; + rtx ops[] = {operands[0], tmp, operands[3], operands[1], + RVV_VUNDEF(mode)}; riscv_vector::emit_vlmax_insn (code_for_pred_mul_plus (mode), riscv_vector::TERNARY_OP, ops); DONE; @@ -1008,7 +1009,8 @@ rtx ext_ops[] = {tmp, operands[2]}; riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops); - rtx ops[] = {operands[0], tmp, operands[3], operands[1]}; + rtx ops[] = {operands[0], tmp, operands[3], operands[1], + RVV_VUNDEF(mode)}; riscv_vector::emit_vlmax_insn (code_for_pred_mul (PLUS, mode), riscv_vector::TERNARY_OP_FRM_DYN, ops); DONE; @@ -1059,7 +1061,8 @@ rtx ext_ops[] = {tmp, operands[2]}; riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops); - rtx ops[] = {operands[0], tmp, operands[3], operands[1]}; + rtx ops[] = {operands[0], tmp, operands[3], operands[1], + RVV_VUNDEF(mode)}; riscv_vector::emit_vlmax_insn (code_for_pred_mul_neg (PLUS, mode), riscv_vector::TERNARY_OP_FRM_DYN, ops); DONE; @@ -1110,7 +1113,8 @@ rtx ext_ops[] = {tmp, operands[2]}; riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops); - rtx ops[] = {operands[0], tmp, operands[3], operands[1]}; + rtx ops[] = {operands[0], tmp, operands[3], operands[1], + RVV_VUNDEF(mode)}; riscv_vector::emit_vlmax_insn (code_for_pred_mul (MINUS, mode), riscv_vector::TERNARY_OP_FRM_DYN, ops); DONE; @@ -1163,7 +1167,8 @@ rtx ext_ops[] = {tmp, operands[2]}; riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ext_ops); - rtx ops[] = {operands[0], tmp, operands[3], operands[1]}; + rtx ops[] = {operands[0], tmp, operands[3], operands[1], + RVV_VUNDEF(mode)}; riscv_vector::emit_vlmax_insn (code_for_pred_mul_neg (MINUS, mode), riscv_vector::TERNARY_OP_FRM_DYN, ops); DONE; -- 2.36.3