[PATCH] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions

[Lehua Ding <lehua.ding@rivai.ai>]

This patch adjusts the comments of the
emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions.
The purpose of the adjustment is to make it clear that vlmax here is not
VLMAX as defined inside the RVV ISA. This is because this function is used
by RVV mode (e.g. RVVM1SImode) in addition to VLS mode (V16QI). For RVV mode,
it means the same thing, for VLS mode, it indicates setting the vl to the
number of units of the mode. Changed the comment because I didn't think of
a better name. If there is a suitable name, feel free to discuss it.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (emit_nonvlmax_insn): Adjust comments.
	(emit_vlmax_insn_lra): Adjust comments.

---
 gcc/config/riscv/riscv-v.cc | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 64a71a128d4..df4d2ac1b2b 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -347,9 +347,8 @@ private:
   expand_operand m_ops[MAX_OPERANDS];
 };

-/* Emit RVV insn which vl is VLMAX.
-   This function can only be used before LRA pass or
-   for VLS_AVL_IMM modes.  */
+/* Emit RVV insn which vl is the number of units of the vector mode.
+   This function can only be used before LRA pass or for VLS_AVL_IMM modes.  */
 void
 emit_vlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops)
 {
@@ -357,23 +356,23 @@ emit_vlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops)
   e.emit_insn ((enum insn_code) icode, ops);
 }

-/* Emit RVV insn which vl is VL.  */
+/* Like emit_vlmax_insn but can be only used after LRA pass that can't create
+   pseudo register.  */
 void
-emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
+emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
 {
-  insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, false);
+  gcc_assert (!can_create_pseudo_p ());
+
+  insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true);
   e.set_vl (vl);
   e.emit_insn ((enum insn_code) icode, ops);
 }

-/* Emit RVV insn which vl is VL but the AVL_TYPE insn attr is VLMAX.
-   This function used after LRA pass that cann't create pseudo register.  */
+/* Emit RVV insn which vl is the VL argument.  */
 void
-emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
+emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
 {
-  gcc_assert (!can_create_pseudo_p ());
-
-  insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true);
+  insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, false);
   e.set_vl (vl);
   e.emit_insn ((enum insn_code) icode, ops);
 }
--
2.36.3