From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 453343857344 for ; Thu, 21 Sep 2023 07:22:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 453343857344 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695280958; x=1726816958; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=owD7NPFKEgXvFNvrr4kgpy4brLhFmsPxptjOgX2J078=; b=U0u4NsNRzF94Fywz/wC0zJOroI6jTZK6D4PhkuuhFJWIbEBQvb9p6lkL mpnmlqkBBtDjy9pwRZ4h/Gq3kL6uLUuO8M6ZJH0kOm878D5TlwXBaDcrc wort2VEOr32lj4H9TyG65X0AvDreOiWlNWibQR74lJAlklbdnF4wSUsBG FzQpjxgG9p93PMWE3/z1efgnxkrW4jayeVDTG98MAn2+3SHJMl8wI/KAO NWVvw4hciDDqmFILe2DbonotuibFq+Ghqc1imbDZNxUBoiLEjnZaWcFxJ aFiS/Wol/Axj/1r9BIqoc+GMEyMVe3No1uusaR+sgH9axXVoVEbfPlRXd w==; X-IronPort-AV: E=McAfee;i="6600,9927,10839"; a="380352163" X-IronPort-AV: E=Sophos;i="6.03,164,1694761200"; d="scan'208";a="380352163" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2023 00:22:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10839"; a="817262195" X-IronPort-AV: E=Sophos;i="6.03,164,1694761200"; d="scan'208";a="817262195" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 21 Sep 2023 00:22:17 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 6694C100513E; Thu, 21 Sep 2023 15:22:14 +0800 (CST) From: "Hu, Lin1" To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com, haochen.jiang@intel.com Subject: [PATCH 16/18] Support -mevex512 for AVX512{IFMA,VBMI,VNNI,BF16,VPOPCNTDQ,VBMI2,BITALG,VP2INTERSECT},VAES,GFNI,VPCLMULQDQ intrins Date: Thu, 21 Sep 2023 15:20:11 +0800 Message-Id: <20230921072013.2124750-17-lin1.hu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230921072013.2124750-1-lin1.hu@intel.com> References: <20230921072013.2124750-1-lin1.hu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Haochen Jiang gcc/ChangeLog: * config/i386/sse.md (VI1_AVX512VL): Add TARGET_EVEX512. (VI8_FVL): Ditto. (VI1_AVX512F): Ditto. (VI1_AVX512VNNI): Ditto. (VI1_AVX512VL_F): Ditto. (VI12_VI48F_AVX512VL): Ditto. (*avx512f_permvar_truncv32hiv32qi_1): Ditto. (sdot_prod): Ditto. (VEC_PERM_AVX2): Ditto. (VPERMI2): Ditto. (VPERMI2I): Ditto. (vpmadd52v8di): Ditto. (usdot_prod): Ditto. (vpdpbusd_v16si): Ditto. (vpdpbusds_v16si): Ditto. (vpdpwssd_v16si): Ditto. (vpdpwssds_v16si): Ditto. (VI48_AVX512VP2VL): Ditto. (avx512vp2intersect_2intersectv16si): Ditto. (VF_AVX512BF16VL): Ditto. (VF1_AVX512_256): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr90096.c: Adjust error message. Co-authored-by: Hu, Lin1 --- gcc/config/i386/sse.md | 56 +++++++++++++------------ gcc/testsuite/gcc.target/i386/pr90096.c | 2 +- 2 files changed, 31 insertions(+), 27 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e59f6bf4410..a5a95b9de66 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -298,7 +298,7 @@ (V32BF "TARGET_EVEX512") (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) (define_mode_iterator VI1_AVX512VL - [V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")]) + [(V64QI "TARGET_EVEX512") (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")]) ;; All vector modes (define_mode_iterator V @@ -531,7 +531,7 @@ [(V8DI "TARGET_AVX512F && TARGET_EVEX512") (V4DI "TARGET_AVX") V2DI]) (define_mode_iterator VI8_FVL - [(V8DI "TARGET_AVX512F") V4DI (V2DI "TARGET_AVX512VL")]) + [(V8DI "TARGET_AVX512F && TARGET_EVEX512") V4DI (V2DI "TARGET_AVX512VL")]) (define_mode_iterator VI8_AVX512VL [(V8DI "TARGET_EVEX512") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) @@ -546,10 +546,10 @@ [(V64QI "TARGET_AVX512BW && TARGET_EVEX512") (V32QI "TARGET_AVX2") V16QI]) (define_mode_iterator VI1_AVX512F - [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI]) + [(V64QI "TARGET_AVX512F && TARGET_EVEX512") (V32QI "TARGET_AVX") V16QI]) (define_mode_iterator VI1_AVX512VNNI - [(V64QI "TARGET_AVX512VNNI") (V32QI "TARGET_AVX2") V16QI]) + [(V64QI "TARGET_AVX512VNNI && TARGET_EVEX512") (V32QI "TARGET_AVX2") V16QI]) (define_mode_iterator VI12_256_512_AVX512VL [(V64QI "TARGET_EVEX512") (V32QI "TARGET_AVX512VL") @@ -599,7 +599,7 @@ V8DI ]) (define_mode_iterator VI1_AVX512VL_F - [V32QI (V16QI "TARGET_AVX512VL") (V64QI "TARGET_AVX512F")]) + [V32QI (V16QI "TARGET_AVX512VL") (V64QI "TARGET_AVX512F && TARGET_EVEX512")]) (define_mode_iterator VI8_AVX2_AVX512BW [(V8DI "TARGET_AVX512BW && TARGET_EVEX512") (V4DI "TARGET_AVX2") V2DI]) @@ -923,8 +923,8 @@ (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL") - V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") - V32HI (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")]) + (V64QI "TARGET_EVEX512") (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL") + (V32HI "TARGET_EVEX512") (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")]) (define_mode_iterator VI48F_256 [V8SI V8SF V4DI V4DF]) @@ -14217,7 +14217,7 @@ (const_int 26) (const_int 27) (const_int 28) (const_int 29) (const_int 30) (const_int 31)])))] - "TARGET_AVX512VBMI && ix86_pre_reload_split ()" + "TARGET_AVX512VBMI && TARGET_EVEX512 && ix86_pre_reload_split ()" "#" "&& 1" [(set (match_dup 0) @@ -16040,7 +16040,7 @@ "TARGET_SSE2" { /* Try with vnni instructions. */ - if (( == 64 && TARGET_AVX512VNNI) + if (( == 64 && TARGET_AVX512VNNI && TARGET_EVEX512) || ( < 64 && ((TARGET_AVX512VNNI && TARGET_AVX512VL) || TARGET_AVXVNNI))) { @@ -17320,7 +17320,8 @@ (V8DF "TARGET_AVX512F && TARGET_EVEX512") (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8DI "TARGET_AVX512F && TARGET_EVEX512") - (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V64QI "TARGET_AVX512VBMI") + (V32HI "TARGET_AVX512BW && TARGET_EVEX512") + (V64QI "TARGET_AVX512VBMI && TARGET_EVEX512") (V32HF "TARGET_AVX512FP16")]) (define_expand "vec_perm" @@ -26983,7 +26984,8 @@ (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX512BW && TARGET_AVX512VL") (V8HI "TARGET_AVX512BW && TARGET_AVX512VL") - (V64QI "TARGET_AVX512VBMI") (V32QI "TARGET_AVX512VBMI && TARGET_AVX512VL") + (V64QI "TARGET_AVX512VBMI && TARGET_EVEX512") + (V32QI "TARGET_AVX512VBMI && TARGET_AVX512VL") (V16QI "TARGET_AVX512VBMI && TARGET_AVX512VL")]) (define_mode_iterator VPERMI2I @@ -26993,7 +26995,8 @@ (V32HI "TARGET_AVX512BW && TARGET_EVEX512") (V16HI "TARGET_AVX512BW && TARGET_AVX512VL") (V8HI "TARGET_AVX512BW && TARGET_AVX512VL") - (V64QI "TARGET_AVX512VBMI") (V32QI "TARGET_AVX512VBMI && TARGET_AVX512VL") + (V64QI "TARGET_AVX512VBMI && TARGET_EVEX512") + (V32QI "TARGET_AVX512VBMI && TARGET_AVX512VL") (V16QI "TARGET_AVX512VBMI && TARGET_AVX512VL")]) (define_expand "_vpermi2var3_mask" @@ -28977,7 +28980,7 @@ (match_operand:V8DI 2 "register_operand" "v") (match_operand:V8DI 3 "nonimmediate_operand" "vm")] VPMADD52))] - "TARGET_AVX512IFMA" + "TARGET_AVX512IFMA && TARGET_EVEX512" "vpmadd52\t{%3, %2, %0|%0, %2, %3}" [(set_attr "type" "ssemuladd") (set_attr "prefix" "evex") @@ -29579,9 +29582,9 @@ (match_operand:VI1_AVX512VNNI 1 "register_operand") (match_operand:VI1_AVX512VNNI 2 "register_operand") (match_operand: 3 "register_operand")] - "( == 64 - ||((TARGET_AVX512VNNI && TARGET_AVX512VL) - || TARGET_AVXVNNI))" + "(( == 64 && TARGET_EVEX512) + || ((TARGET_AVX512VNNI && TARGET_AVX512VL) + || TARGET_AVXVNNI))" { operands[1] = lowpart_subreg (mode, force_reg (mode, operands[1]), @@ -29602,7 +29605,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPBUSD))] - "TARGET_AVX512VNNI" + "TARGET_AVX512VNNI && TARGET_EVEX512" "vpdpbusd\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -29670,7 +29673,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPBUSDS))] - "TARGET_AVX512VNNI" + "TARGET_AVX512VNNI && TARGET_EVEX512" "vpdpbusds\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -29738,7 +29741,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPWSSD))] - "TARGET_AVX512VNNI" + "TARGET_AVX512VNNI && TARGET_EVEX512" "vpdpwssd\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -29806,7 +29809,7 @@ (match_operand:V16SI 2 "register_operand" "v") (match_operand:V16SI 3 "nonimmediate_operand" "vm")] UNSPEC_VPDPWSSDS))] - "TARGET_AVX512VNNI" + "TARGET_AVX512VNNI && TARGET_EVEX512" "vpdpwssds\t{%3, %2, %0|%0, %2, %3}" [(set_attr ("prefix") ("evex"))]) @@ -29929,9 +29932,9 @@ (set_attr "mode" "")]) (define_mode_iterator VI48_AVX512VP2VL - [V8DI - (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") - (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")]) + [(V8DI "TARGET_EVEX512") + (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL") + (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")]) (define_mode_iterator MASK_DWI [P2QI P2HI]) @@ -29972,12 +29975,12 @@ (unspec:P2HI [(match_operand:V16SI 1 "register_operand" "v") (match_operand:V16SI 2 "vector_operand" "vm")] UNSPEC_VP2INTERSECT))] - "TARGET_AVX512VP2INTERSECT" + "TARGET_AVX512VP2INTERSECT && TARGET_EVEX512" "vp2intersectd\t{%2, %1, %0|%0, %1, %2}" [(set_attr ("prefix") ("evex"))]) (define_mode_iterator VF_AVX512BF16VL - [V32BF (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) + [(V32BF "TARGET_EVEX512") (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) ;; Converting from BF to SF (define_mode_attr bf16_cvt_2sf [(V32BF "V16SF") (V16BF "V8SF") (V8BF "V4SF")]) @@ -30070,7 +30073,8 @@ "TARGET_AVX512BF16 && TARGET_AVX512VL" "vcvtneps2bf16{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}") -(define_mode_iterator VF1_AVX512_256 [V16SF (V8SF "TARGET_AVX512VL")]) +(define_mode_iterator VF1_AVX512_256 + [(V16SF "TARGET_EVEX512") (V8SF "TARGET_AVX512VL")]) (define_expand "avx512f_cvtneps2bf16__maskz" [(match_operand: 0 "register_operand") diff --git a/gcc/testsuite/gcc.target/i386/pr90096.c b/gcc/testsuite/gcc.target/i386/pr90096.c index 871e0ffc691..74f052ea8e5 100644 --- a/gcc/testsuite/gcc.target/i386/pr90096.c +++ b/gcc/testsuite/gcc.target/i386/pr90096.c @@ -10,7 +10,7 @@ volatile __mmask64 m64; void foo (int i) { - x1 = _mm512_gf2p8affineinv_epi64_epi8 (x1, x2, 3); /* { dg-error "needs isa option -mgfni -mavx512f" } */ + x1 = _mm512_gf2p8affineinv_epi64_epi8 (x1, x2, 3); /* { dg-error "needs isa option -mevex512 -mgfni -mavx512f" } */ } #ifdef __x86_64__ -- 2.31.1