From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 68A48385703C for ; Thu, 21 Sep 2023 07:22:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 68A48385703C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695280959; x=1726816959; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4WjSflmpm+nytvYcfQp5oGl2ohkto/29GbQ7KBJPK9E=; b=auS06QOLtoyNMD8FEHipZzwUi1HezI+6Y3f0Kq4orPKH1sAbapsDxuAh jE96B1y5Nw2kwDOmc+OK6e0uHGV3BxWVZNDjaJaheYL55GLX2TwVnLksk 9pB6sJuJDG2K1ihqVmpH0AYjf7edZPwD+swj0BbTjweJAbHoW8zA3cMbu xVHzlyfoS3Eq0FqzgorBMudy4blM/Q7XFNiKwzf4VGlr+2eSJmjcG5c3u kv3x57AtBz4OLpdke0E5NotsK7nnneEqvwilomRpoO5VhH3wZJXVXn0wu JrVN5XYnVVE1c7XmjSkr7nSKV4PY2iRhG02zWkrL0ihb3Df6jWE0MmA+Q Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10839"; a="380352159" X-IronPort-AV: E=Sophos;i="6.03,164,1694761200"; d="scan'208";a="380352159" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2023 00:22:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10839"; a="817262190" X-IronPort-AV: E=Sophos;i="6.03,164,1694761200"; d="scan'208";a="817262190" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 21 Sep 2023 00:22:17 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 6AE49100514D; Thu, 21 Sep 2023 15:22:14 +0800 (CST) From: "Hu, Lin1" To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com, haochen.jiang@intel.com Subject: [PATCH 18/18] Allow -mno-evex512 usage Date: Thu, 21 Sep 2023 15:20:13 +0800 Message-Id: <20230921072013.2124750-19-lin1.hu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230921072013.2124750-1-lin1.hu@intel.com> References: <20230921072013.2124750-1-lin1.hu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Haochen Jiang gcc/ChangeLog: * config/i386/i386.opt: Allow -mno-evex512. gcc/testsuite/ChangeLog: * gcc.target/i386/noevex512-1.c: New test. * gcc.target/i386/noevex512-2.c: Ditto. * gcc.target/i386/noevex512-3.c: Ditto. --- gcc/config/i386/i386.opt | 2 +- gcc/testsuite/gcc.target/i386/noevex512-1.c | 13 +++++++++++++ gcc/testsuite/gcc.target/i386/noevex512-2.c | 13 +++++++++++++ gcc/testsuite/gcc.target/i386/noevex512-3.c | 13 +++++++++++++ 4 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/noevex512-1.c create mode 100644 gcc/testsuite/gcc.target/i386/noevex512-2.c create mode 100644 gcc/testsuite/gcc.target/i386/noevex512-3.c diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 6d8601b1f75..34fc167af82 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1312,5 +1312,5 @@ Target Alias(mtune-ctrl=, use_scatter, ^use_scatter) Enable vectorization for scatter instruction. mevex512 -Target RejectNegative Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save +Target Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save Support 512 bit vector built-in functions and code generation. diff --git a/gcc/testsuite/gcc.target/i386/noevex512-1.c b/gcc/testsuite/gcc.target/i386/noevex512-1.c new file mode 100644 index 00000000000..7fd45f15be6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/noevex512-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -march=x86-64 -mavx512f -mno-evex512 -Wno-psabi" } */ +/* { dg-final { scan-assembler-not ".%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__m512d +foo () +{ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/noevex512-2.c b/gcc/testsuite/gcc.target/i386/noevex512-2.c new file mode 100644 index 00000000000..1c206e385d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/noevex512-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mavx512bw -mno-evex512" } */ + +#include + +long long +foo (long long c) +{ + register long long a __asm ("k7") = c; + long long b = foo (a); + asm volatile ("" : "+k" (b)); /* { dg-error "inconsistent operand constraints in an 'asm'" } */ + return b; +} diff --git a/gcc/testsuite/gcc.target/i386/noevex512-3.c b/gcc/testsuite/gcc.target/i386/noevex512-3.c new file mode 100644 index 00000000000..10e00c2d61c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/noevex512-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -Wno-psabi -mavx512f" } */ +/* { dg-final { scan-assembler-not ".%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("no-evex512"))) __m512d +foo () +{ + __m512d a, b; + a = a + b; + return a; +} -- 2.31.1