From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id 392DE3858D39 for ; Thu, 21 Sep 2023 22:47:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 392DE3858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp75t1695336444tf3oz2gn Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 22 Sep 2023 06:47:23 +0800 (CST) X-QQ-SSF: 01400000002000G0V000B00A0000000 X-QQ-FEAT: Up5lG24IcOjkLkpARbhglsHTCNkTjJL8x4Gi/vDjIMsMwQHhjNySKU0ruEOR/ 5GZnkFQRNz3wFbfkphW7tmKCGWxSqwDErute2Gnj5w/cCg6xz7rcwICFjP7ZJCjwM+v58G2 dkEtW7qJtjtYBhQx+NPjBW5F1z+qveIGJYwqCvmBl8u68w1aTY0/HPsj6KqAtnFCSPGpFQQ OWn5eHw0Jti8bpBV7hm9V343nDff1MUvR/wtVoHWnfWXhlMhn4dcE6KDeFB2fUdr3R+Alx7 mmJefX2JqKaezDonbt3lECcHElLS4ALWghkL7nb3oVBhJ7MU/wHJsLBqJb/ynd7uwNLlJfx xPjwUvIjSKS+iGHsMAvgtnJQYuwzJsQ7nTHptDEE20SWJUdS+f7bBlvrsMfkA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 15238380100308141459 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Add VLS integer ABS support Date: Fri, 22 Sep 2023 06:47:22 +0800 Message-Id: <20230921224722.3070110-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_PASS,TXREP,T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Regression passed. Committed. gcc/ChangeLog: * config/riscv/autovec.md: Extend VLS modes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/abs-2.c: New test. --- gcc/config/riscv/autovec.md | 6 +- .../gcc.target/riscv/rvv/autovec/vls/abs-2.c | 62 +++++++++++++++++++ 2 files changed, 65 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index f0f1abc4e82..c895d41376d 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1004,9 +1004,9 @@ ;; ------------------------------------------------------------------------------- (define_insn_and_split "abs2" - [(set (match_operand:VI 0 "register_operand") - (abs:VI - (match_operand:VI 1 "register_operand")))] + [(set (match_operand:V_VLSI 0 "register_operand") + (abs:V_VLSI + (match_operand:V_VLSI 1 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c new file mode 100644 index 00000000000..e98f5c4bbf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/abs-2.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (neg, 4, int8_t, __builtin_abs) +DEF_OP_V (neg, 8, int8_t, __builtin_abs) +DEF_OP_V (neg, 16, int8_t, __builtin_abs) +DEF_OP_V (neg, 32, int8_t, __builtin_abs) +DEF_OP_V (neg, 64, int8_t, __builtin_abs) +DEF_OP_V (neg, 128, int8_t, __builtin_abs) +DEF_OP_V (neg, 256, int8_t, __builtin_abs) +DEF_OP_V (neg, 512, int8_t, __builtin_abs) +DEF_OP_V (neg, 1024, int8_t, __builtin_abs) +DEF_OP_V (neg, 2048, int8_t, __builtin_abs) +DEF_OP_V (neg, 4096, int8_t, __builtin_abs) + +DEF_OP_V (neg, 4, int16_t, __builtin_abs) +DEF_OP_V (neg, 8, int16_t, __builtin_abs) +DEF_OP_V (neg, 16, int16_t, __builtin_abs) +DEF_OP_V (neg, 32, int16_t, __builtin_abs) +DEF_OP_V (neg, 64, int16_t, __builtin_abs) +DEF_OP_V (neg, 128, int16_t, __builtin_abs) +DEF_OP_V (neg, 256, int16_t, __builtin_abs) +DEF_OP_V (neg, 512, int16_t, __builtin_abs) +DEF_OP_V (neg, 1024, int16_t, __builtin_abs) +DEF_OP_V (neg, 2048, int16_t, __builtin_abs) + +DEF_OP_V (neg, 4, int32_t, __builtin_abs) +DEF_OP_V (neg, 8, int32_t, __builtin_abs) +DEF_OP_V (neg, 16, int32_t, __builtin_abs) +DEF_OP_V (neg, 32, int32_t, __builtin_abs) +DEF_OP_V (neg, 64, int32_t, __builtin_abs) +DEF_OP_V (neg, 128, int32_t, __builtin_abs) +DEF_OP_V (neg, 256, int32_t, __builtin_abs) +DEF_OP_V (neg, 512, int32_t, __builtin_abs) +DEF_OP_V (neg, 1024, int32_t, __builtin_abs) + +DEF_OP_V (neg, 4, int64_t, __builtin_abs) +DEF_OP_V (neg, 8, int64_t, __builtin_abs) +DEF_OP_V (neg, 16, int64_t, __builtin_abs) +DEF_OP_V (neg, 32, int64_t, __builtin_abs) +DEF_OP_V (neg, 64, int64_t, __builtin_abs) +DEF_OP_V (neg, 128, int64_t, __builtin_abs) +DEF_OP_V (neg, 256, int64_t, __builtin_abs) +DEF_OP_V (neg, 512, int64_t, __builtin_abs) + +/* { dg-final { scan-assembler-times {vneg\.v} 38 } } */ +/* { dg-final { scan-assembler-times {vmslt\.vi} 38 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ -- 2.36.3