From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id 25DBC3857359 for ; Fri, 22 Sep 2023 10:56:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 25DBC3857359 Authentication-Results: sourceware.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=gmail.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695380202; x=1726916202; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=U5ZLvJ4SwCIjPl+J/Skh9hWeQmCYGasr82BA37Hz7Yk=; b=jGcGGByxLcWwpR5WXWPlns81iZEfKVc/HIogf55ekEUdb11MExpi0BTx De8m1kbV2+pZPs2CiVuSghKqS6OROOsC2pWdTE8XzURPqKUnZ9vCM2lR0 8v3fqTEFBPqWhqbeMwimkdqRoxIVKS03+SFvil2BqiAYnmbbl1T4usQIH l7hD71PL6t4tjRhJozge5EC0fhNKAnTLzCXdlwksShdGJdtnEKsvrc4nf /cNKpRkRWLknxnXOf+WWRGqkkCRR9Xoq6rns0plzlCkhDMnUHiCAUcgY1 VqKkgEbln2FZJYQCDgKVw2eQfe5B3xDQ/f3N8YnhASA9eBbv1YXaL2zdG Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="379680795" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="379680795" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2023 03:56:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="782615901" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="782615901" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 22 Sep 2023 03:56:35 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id AF738100513B; Fri, 22 Sep 2023 18:56:31 +0800 (CST) From: Hongyu Wang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, vmakarov@redhat.com, jakub@redhat.com, Kong Lingling , Hongtao Liu Subject: [PATCH 06/13] [APX EGPR] Add backend hook for base_reg_class/index_reg_class. Date: Fri, 22 Sep 2023 18:56:24 +0800 Message-Id: <20230922105631.2298849-7-hongyu.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230922105631.2298849-1-hongyu.wang@intel.com> References: <20230922105631.2298849-1-hongyu.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,GIT_PATCH_0,HEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE,SPF_SOFTFAIL,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Kong Lingling Add backend helper functions to verify if a rtx_insn can adopt EGPR to its base/index reg of memory operand. The verification rule goes like 1. For asm insn, enable/disable EGPR by ix86_apx_inline_asm_use_gpr32. 2. Disable EGPR for unrecognized insn. 3. If which_alternative is not decided, loop through enabled alternatives and check its attr_gpr32. Only enable EGPR when all enabled alternatives has attr_gpr32 = 1. 4. If which_alternative is decided, enable/disable EGPR by its corresponding attr_gpr32. gcc/ChangeLog: * config/i386/i386-protos.h (ix86_insn_base_reg_class): New prototype. (ix86_regno_ok_for_insn_base_p): Likewise. (ix86_insn_index_reg_class): Likewise. * config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p): New helper function to scan the insn. (ix86_insn_base_reg_class): New function to choose BASE_REG_CLASS. (ix86_regno_ok_for_insn_base_p): Likewise for base regno. (ix86_insn_index_reg_class): Likewise for INDEX_REG_CLASS. * config/i386/i386.h (INSN_BASE_REG_CLASS): Define. (REGNO_OK_FOR_INSN_BASE_P): Likewise. (INSN_INDEX_REG_CLASS): Likewise. (enum reg_class): Add INDEX_GPR16. (GENERAL_GPR16_REGNO_P): Define. * config/i386/i386.md (gpr32): New attribute. Co-authored-by: Hongyu Wang Co-authored-by: Hongtao Liu --- gcc/config/i386/i386-protos.h | 3 ++ gcc/config/i386/i386.cc | 89 +++++++++++++++++++++++++++++++++++ gcc/config/i386/i386.h | 17 ++++++- gcc/config/i386/i386.md | 3 ++ 4 files changed, 111 insertions(+), 1 deletion(-) diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index bd4782800c4..a54e3f6b1dc 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -79,6 +79,9 @@ extern bool ix86_expand_set_or_cpymem (rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, rtx, bool); extern bool ix86_expand_cmpstrn_or_cmpmem (rtx, rtx, rtx, rtx, rtx, bool); +extern enum reg_class ix86_insn_base_reg_class (rtx_insn *); +extern bool ix86_regno_ok_for_insn_base_p (int, rtx_insn *); +extern enum reg_class ix86_insn_index_reg_class (rtx_insn *); extern bool constant_address_p (rtx); extern bool legitimate_pic_operand_p (rtx); extern bool legitimate_pic_address_disp_p (rtx); diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index fb1672f0b3d..5af0de4dae7 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -11062,6 +11062,95 @@ ix86_validate_address_register (rtx op) return NULL_RTX; } +/* Return true if insn memory address can use any available reg + in BASE_REG_CLASS or INDEX_REG_CLASS, otherwise false. + For APX, some instruction can't be encoded with gpr32 + which is BASE_REG_CLASS or INDEX_REG_CLASS, for that case + returns false. */ +static bool +ix86_memory_address_use_extended_reg_class_p (rtx_insn* insn) +{ + /* LRA will do some initialization with insn == NULL, + return the maximum reg class for that. + For other cases, real insn will be passed and checked. */ + bool ret = true; + if (TARGET_APX_EGPR && insn) + { + if (asm_noperands (PATTERN (insn)) >= 0 + || GET_CODE (PATTERN (insn)) == ASM_INPUT) + return ix86_apx_inline_asm_use_gpr32; + + if (INSN_CODE (insn) < 0) + return false; + + /* Try recog the insn before calling get_attr_gpr32. Save + the current recog_data first. */ + /* Also save which_alternative for current recog. */ + + struct recog_data_d recog_data_save = recog_data; + int which_alternative_saved = which_alternative; + + /* Update the recog_data for alternative check. */ + if (recog_data.insn != insn) + extract_insn_cached (insn); + + /* If alternative is not set, loop throught each alternative + of insn and get gpr32 attr for all enabled alternatives. + If any enabled alternatives has 0 value for gpr32, disallow + gpr32 for addressing. */ + if (which_alternative_saved == -1) + { + alternative_mask enabled = get_enabled_alternatives (insn); + bool curr_insn_gpr32 = false; + for (int i = 0; i < recog_data.n_alternatives; i++) + { + if (!TEST_BIT (enabled, i)) + continue; + which_alternative = i; + curr_insn_gpr32 = get_attr_gpr32 (insn); + if (!curr_insn_gpr32) + ret = false; + } + } + else + { + which_alternative = which_alternative_saved; + ret = get_attr_gpr32 (insn); + } + + recog_data = recog_data_save; + which_alternative = which_alternative_saved; + } + + return ret; +} + +/* For APX, some instructions can't be encoded with gpr32. */ +enum reg_class +ix86_insn_base_reg_class (rtx_insn* insn) +{ + if (ix86_memory_address_use_extended_reg_class_p (insn)) + return BASE_REG_CLASS; + return GENERAL_GPR16; +} + +bool +ix86_regno_ok_for_insn_base_p (int regno, rtx_insn* insn) +{ + + if (ix86_memory_address_use_extended_reg_class_p (insn)) + return GENERAL_REGNO_P (regno); + return GENERAL_GPR16_REGNO_P (regno); +} + +enum reg_class +ix86_insn_index_reg_class (rtx_insn* insn) +{ + if (ix86_memory_address_use_extended_reg_class_p (insn)) + return INDEX_REG_CLASS; + return INDEX_GPR16; +} + /* Recognizes RTL expressions that are valid memory addresses for an instruction. The MODE argument is the machine mode for the MEM expression that wants to use this address. diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 66b8764e82b..7fa7585e058 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1018,6 +1018,14 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () +#define INSN_BASE_REG_CLASS(INSN) \ + ix86_insn_base_reg_class (INSN) + +#define REGNO_OK_FOR_INSN_BASE_P(NUM, INSN) \ + ix86_regno_ok_for_insn_base_p (NUM, INSN) + +#define INSN_INDEX_REG_CLASS(INSN) \ + ix86_insn_index_reg_class (INSN) #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) @@ -1297,6 +1305,8 @@ enum reg_class %r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */ GENERAL_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ + INDEX_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp + %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ FLOAT_REGS, SSE_FIRST_REG, @@ -1360,6 +1370,7 @@ enum reg_class "LEGACY_REGS", \ "GENERAL_REGS", \ "GENERAL_GPR16", \ + "INDEX_GPR16", \ "FP_TOP_REG", "FP_SECOND_REG", \ "FLOAT_REGS", \ "SSE_FIRST_REG", \ @@ -1395,10 +1406,11 @@ enum reg_class { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \ { 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \ { 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \ - { 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \ + { 0x7f, 0xff0, 0xffff000 }, /* INDEX_REGS */ \ { 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \ { 0x900ff, 0xff0, 0xffff000 }, /* GENERAL_REGS */ \ { 0x900ff, 0xff0, 0x0 }, /* GENERAL_GPR16 */ \ + { 0x0007f, 0xff0, 0x0 }, /* INDEX_GPR16 */ \ { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \ { 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \ { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \ @@ -1456,6 +1468,9 @@ enum reg_class #define INDEX_REGNO_P(N) \ (LEGACY_INDEX_REGNO_P (N) || REX_INT_REGNO_P (N) || REX2_INT_REGNO_P (N)) +#define GENERAL_GPR16_REGNO_P(N) \ + (LEGACY_INT_REGNO_P (N) || REX_INT_REGNO_P (N)) + #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) #define ANY_QI_REGNO_P(N) \ (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index e3270658cb7..b9eaea78f00 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -873,6 +873,9 @@ (define_attr "use_carry" "0,1" (const_string "0")) ;; Define attribute to indicate unaligned ssemov insns (define_attr "movu" "0,1" (const_string "0")) +;; Define attribute to indicate gpr32 insns. +(define_attr "gpr32" "0, 1" (const_string "1")) + ;; Define instruction set of MMX instructions (define_attr "mmx_isa" "base,native,sse,sse_noavx,avx" (const_string "base")) -- 2.31.1