From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by sourceware.org (Postfix) with ESMTPS id 15393385828E for ; Tue, 26 Sep 2023 02:45:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 15393385828E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp89t1695696311tsb4am6y Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 26 Sep 2023 10:45:09 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: mRz6/7wsmIjBLRLqyGd3FBJz4ZDXT2WF1Pa0Mm/HiCCpRN4nXyEpvLYn/lqYv gQ6M2Af+5QPHHo5SzBpk3XM06Z6371FUzT4AhBscxdzA6ZhIcKtqHhYmSwP56BnvbW208RB QrrPVsiJSPQ1+odU5NJB97INRHyL6wtob02p4lvvQDrAuDLICyvqwtfdmxbtwYSgMg/7by+ IeGcFcUBU0vk95fjrPm5LNaVPkxjoyuEg8S5kobt5Trb4vn49TH4MdHG/UvkUX4/6SrkysR iICC2tRoQ0ghIKRpCUVc1AaOB2YcjtQJDf7yD8CPNOrEvQSEJ3xufp/JlnvRE4wHO0eizCa ARNaeZKxg+RJ6ZMbx8URxXWR2bnuhu3S4O22uXyHImg9QHV5T4= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5718098233723483933 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, richard.sandiford@arm.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Add opaque integer modes to fix ICE on DSE[PR111590] Date: Tue, 26 Sep 2023 10:45:07 +0800 Message-Id: <20230926024507.3076723-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP,WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: When doing fortran test with 'V' extension enabled on RISC-V port. I saw multiple ICE: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111590 The root cause is on DSE: internal compiler error: in smallest_mode_for_size, at stor-layout.cc:356 0x1918f70 smallest_mode_for_size(poly_int<2u, unsigned long>, mode_class) ../../../../gcc/gcc/stor-layout.cc:356 0x11f75bb smallest_int_mode_for_size(poly_int<2u, unsigned long>) ../../../../gcc/gcc/machmode.h:916 0x3304141 find_shift_sequence ../../../../gcc/gcc/dse.cc:1738 0x3304f1a get_stored_val ../../../../gcc/gcc/dse.cc:1906 0x3305377 replace_read ../../../../gcc/gcc/dse.cc:2010 0x3306226 check_mem_read_rtx ../../../../gcc/gcc/dse.cc:2310 0x330667b check_mem_read_use ../../../../gcc/gcc/dse.cc:2415 After investigations, DSE is trying to do optimization like this following codes: (insn 86 85 87 9 (set (reg:V4DI 168) (mem/u/c:V4DI (reg/f:DI 171) [0 S32 A128])) "bug.f90":6:18 discrim 6 1167 {*movv4di} (expr_list:REG_EQUAL (const_vector:V4DI [ (const_int 4 [0x4]) (const_int 1 [0x1]) repeated x2 (const_int 3 [0x3]) ]) (nil))) (set (mem) (reg:V4DI 168)) Then it ICE on: auto new_mode = smallest_int_mode_for_size (access_size * BITS_PER_UNIT); The access_size may be 24 or 32. We don't have such integer modes with these size so it ICE. I saw both aarch64 and ARM has EI/OI/CI/XI opaque modes. So I add it to walk around ICE on DCE, it works as all ICE are resolved. CC Richard to review to make sure I am doing the right thing to fix the bug. Hi, Richard, could you help me with this issue ? Thanks. gcc/ChangeLog: * config/riscv/riscv-modes.def (INT_MODE): Add opaque modes --- gcc/config/riscv/riscv-modes.def | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index e3c6ccb2809..ab86032c914 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -393,6 +393,12 @@ VLS_MODES (1024); /* V1024QI V512HI V256SI V128DI V512HF V256SF V128DF */ VLS_MODES (2048); /* V2048QI V1024HI V512SI V256DI V1024HF V512SF V256DF */ VLS_MODES (4096); /* V4096QI V2048HI V1024SI V512DI V2048HF V1024SF V512DF */ +/* Opaque integer modes 3, 4, 6 or 8 general double registers. */ +INT_MODE (EI, 24); +INT_MODE (OI, 32); +INT_MODE (CI, 48); +INT_MODE (XI, 64); + /* TODO: According to RISC-V 'V' ISA spec, the maximun vector length can be 65536 for a single vector register which means the vector mode in GCC can be maximum = 65536 * 8 bits (LMUL=8). -- 2.36.3