From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id CAD5938560B9 for ; Tue, 26 Sep 2023 13:15:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CAD5938560B9 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp75t1695734135t701izk7 Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 26 Sep 2023 21:15:33 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: RrZlkntZBfnoVclz2x131/eOFrPYCGvzmDqPpRR9xkqKpXqDLaY5bJpxX+Mps Xwm55pIOeY2iLs7ao62q//Oo8swj2iV7P8ooRjJFO5AAi1wz32hv/rjMaZByFYr+bceGztq GDIilUfre+NJd/2fZK5voTuTqHVrOJ2gOXFDnKwbOYBLIACEEmNf4Wt36nzZ1mgKCjPSPvE h9RLef2t/IAcSU5oLMiOaU2hUW4wKIqJgMi3iGYK94WuyOEdpGaADlkg0gdjh7PR9KBtOQn m3xhurj+4J2l7z7YCXaNar/H5T6lI+Wtkgt5Vu8s+9Y67QbIt9IToFfiksYb0adwkWGqYza pGP/nPNVD58buEW+DlIxOVaBcRaOMngKR1zb3xXh1LFm209hrrLzPNG9SP9VXnWFUlxkdVr GHz8QN6pL4gYdfM3+VNDFd68LyO2hUhD X-QQ-GoodBg: 2 X-BIZMAIL-ID: 2198191205903069326 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [Committed] RISC-V: Fix mem-to-mem VLS move pattern[PR111566] Date: Tue, 26 Sep 2023 21:15:32 +0800 Message-Id: <20230926131532.1935361-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_PASS,TXREP,T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The mem-to-mem insn pattern is splitted from reg-to-mem/mem-to-reg/reg-to-reg causes ICE in RA since RA prefer they stay together. Now, we split mem-to-mem as a pure pre-RA split pattern and only allow define_insn match mem-to-mem VLS move in pre-RA stage (Forbid mem-to-mem move after RA). Tested no difference. Committed. PR target/111566 gcc/ChangeLog: * config/riscv/vector.md (*mov_mem_to_mem): gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/fortran/pr111566.f90: New test. --- gcc/config/riscv/vector.md | 19 +++++++++--- .../gcc.target/riscv/rvv/fortran/pr111566.f90 | 31 +++++++++++++++++++ 2 files changed, 45 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index d5300a33946..a98242f2fd8 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1222,12 +1222,14 @@ DONE; }) -(define_insn_and_split "*mov_mem_to_mem" +;; Some VLS modes (like V2SImode) have size <= a general purpose +;; register width, we optimize such mem-to-mem move into mem-to-mem +;; scalar move. Otherwise, we always force operands[1] into register +;; so that we will never get mem-to-mem move after RA. +(define_split [(set (match_operand:VLS_AVL_IMM 0 "memory_operand") (match_operand:VLS_AVL_IMM 1 "memory_operand"))] "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" [(const_int 0)] { if (GET_MODE_BITSIZE (mode).to_constant () <= MAX_BITS_PER_WORD) @@ -1256,14 +1258,21 @@ } DONE; } - [(set_attr "type" "vmov")] ) +;; We recognize mem-to-mem move in pre-RA stage so that we won't have +;; ICE (unrecognizable insn: (set (mem) (mem))). Then, the previous +;; mem-to-mem split pattern will force operands[1] into a register so +;; that mem-to-mem move will never happen after RA. +;; +;; We don't allow mem-to-mem move in post-RA stage since we +;; don't have an instruction to split mem-to-mem move after RA. (define_insn_and_split "*mov" [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr") (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))] "TARGET_VECTOR - && (register_operand (operands[0], mode) + && (can_create_pseudo_p () + || register_operand (operands[0], mode) || register_operand (operands[1], mode))" "@ # diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 new file mode 100644 index 00000000000..2e30dc9bfaa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 @@ -0,0 +1,31 @@ +! { dg-do compile } +! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -fallow-argument-mismatch -fmax-stack-var-size=65536 -S -std=legacy -w" } + +module a + integer,parameter :: SHR_KIND_R8 = selected_real_kind(12) +end module a +module b + use a, c => shr_kind_r8 +contains + subroutine d(cg , km, i1, i2) + real (c) ch(i2,km) + real (c) cg(4,i1:i2,km) + real dc(i2,km) + real(c) ci(i2,km) + real(c) cj(i2,km) + do k=2,ck + do i=i1,0 + cl = ci(i,k) *ci(i,1) / cj(i,k)+ch(i,1) + cm = cg(1,i,k) - min(e,cg(1,i,co)) + dc(i,k) = sign(cm, cl) + enddo + enddo + if ( cq == 0 ) then + do i=i1,i2 + if( cr <= cs ) then + cg= sign( min(ct, cg), cg) + endif + enddo + endif + end subroutine d +end module b -- 2.36.3