* [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
@ 2023-09-26 15:26 Juzhe-Zhong
2023-09-27 9:33 ` Kito Cheng
0 siblings, 1 reply; 8+ messages in thread
From: Juzhe-Zhong @ 2023-09-26 15:26 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, kito.cheng, jeffreyalaw, rdapp.gcc, Juzhe-Zhong
PR target/111566
gcc/ChangeLog:
* config/riscv/vector.md (*mov<mode>_mem_to_mem): Remove.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/mov-1.c: Adapt test.
* gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mov-9.c: Ditto.1
* gcc.target/riscv/rvv/autovec/vls/mov-2.c: Removed.
* gcc.target/riscv/rvv/autovec/vls/mov-4.c: Removed.
* gcc.target/riscv/rvv/autovec/vls/mov-6.c: Removed.
* gcc.target/riscv/rvv/fortran/pr111566.f90: New test.
---
gcc/config/riscv/vector.md | 40 +---------------
.../gcc.target/riscv/rvv/autovec/vls/mov-1.c | 48 -------------------
.../gcc.target/riscv/rvv/autovec/vls/mov-10.c | 12 -----
.../gcc.target/riscv/rvv/autovec/vls/mov-2.c | 19 --------
.../gcc.target/riscv/rvv/autovec/vls/mov-3.c | 36 --------------
.../gcc.target/riscv/rvv/autovec/vls/mov-4.c | 19 --------
.../gcc.target/riscv/rvv/autovec/vls/mov-5.c | 24 ----------
.../gcc.target/riscv/rvv/autovec/vls/mov-6.c | 19 --------
.../gcc.target/riscv/rvv/autovec/vls/mov-7.c | 12 -----
.../gcc.target/riscv/rvv/autovec/vls/mov-8.c | 36 --------------
.../gcc.target/riscv/rvv/autovec/vls/mov-9.c | 24 ----------
.../gcc.target/riscv/rvv/fortran/pr111566.f90 | 31 ++++++++++++
12 files changed, 33 insertions(+), 287 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index d5300a33946..57205025ff8 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1222,48 +1222,12 @@
DONE;
})
-(define_insn_and_split "*mov<mode>_mem_to_mem"
- [(set (match_operand:VLS_AVL_IMM 0 "memory_operand")
- (match_operand:VLS_AVL_IMM 1 "memory_operand"))]
- "TARGET_VECTOR && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
- {
- if (GET_MODE_BITSIZE (<MODE>mode).to_constant () <= MAX_BITS_PER_WORD)
- {
- /* Opitmize the following case:
-
- typedef int8_t v2qi __attribute__ ((vector_size (2)));
- v2qi v = *(v2qi*)in;
- *(v2qi*)out = v;
-
- We prefer scalar load/store instead of vle.v/vse.v when
- the VLS modes size is smaller scalar mode. */
- machine_mode mode;
- unsigned size = GET_MODE_BITSIZE (<MODE>mode).to_constant ();
- if (FLOAT_MODE_P (<MODE>mode))
- mode = mode_for_size (size, MODE_FLOAT, 0).require ();
- else
- mode = mode_for_size (size, MODE_INT, 0).require ();
- emit_move_insn (gen_lowpart (mode, operands[0]),
- gen_lowpart (mode, operands[1]));
- }
- else
- {
- operands[1] = force_reg (<MODE>mode, operands[1]);
- emit_move_insn (operands[0], operands[1]);
- }
- DONE;
- }
- [(set_attr "type" "vmov")]
-)
-
(define_insn_and_split "*mov<mode>"
[(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
(match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
"TARGET_VECTOR
- && (register_operand (operands[0], <MODE>mode)
+ && (can_create_pseudo_p ()
+ || register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
"@
#
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
index aedf98819bb..24bb7240db8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
@@ -4,54 +4,6 @@
#include "def.h"
-/*
-** mov0:
-** lbu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sb\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov0 (int8_t *in, int8_t *out)
-{
- v1qi v = *(v1qi*)in;
- *(v1qi*)out = v;
-}
-
-/*
-** mov1:
-** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov1 (int8_t *in, int8_t *out)
-{
- v2qi v = *(v2qi*)in;
- *(v2qi*)out = v;
-}
-
-/*
-** mov2:
-** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov2 (int8_t *in, int8_t *out)
-{
- v4qi v = *(v4qi*)in;
- *(v4qi*)out = v;
-}
-
-/*
-** mov3:
-** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov3 (int8_t *in, int8_t *out)
-{
- v8qi v = *(v8qi*)in;
- *(v8qi*)out = v;
-}
-
/*
** mov4:
** vsetivli\s+zero,\s*16,\s*e8,\s*mf8,\s*t[au],\s*m[au]
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
index 5e9615412b7..cae96b3be3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
@@ -4,18 +4,6 @@
#include "def.h"
-/*
-** mov0:
-** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov0 (double *in, double *out)
-{
- v1df v = *(v1df*)in;
- *(v1df*)out = v;
-}
-
/*
** mov1:
** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
deleted file mode 100644
index 10ae1972db7..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-final { check-function-bodies "**" "" } } */
-
-#include "def.h"
-
-/*
-** mov:
-** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
-** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
-** ret
-*/
-void mov (int8_t *in, int8_t *out)
-{
- v8qi v = *(v8qi*)in;
- *(v8qi*)out = v;
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
index f2880ae5e77..86ce22896c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
@@ -4,42 +4,6 @@
#include "def.h"
-/*
-** mov0:
-** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov0 (int16_t *in, int16_t *out)
-{
- v1hi v = *(v1hi*)in;
- *(v1hi*)out = v;
-}
-
-/*
-** mov1:
-** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov1 (int16_t *in, int16_t *out)
-{
- v2hi v = *(v2hi*)in;
- *(v2hi*)out = v;
-}
-
-/*
-** mov2:
-** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov2 (int16_t *in, int16_t *out)
-{
- v4hi v = *(v4hi*)in;
- *(v4hi*)out = v;
-}
-
/*
** mov3:
** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
deleted file mode 100644
index f81f1697d65..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-final { check-function-bodies "**" "" } } */
-
-#include "def.h"
-
-/*
-** mov:
-** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
-** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
-** ret
-*/
-void mov (int16_t *in, int16_t *out)
-{
- v4hi v = *(v4hi*)in;
- *(v4hi*)out = v;
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
index c30ed8f76f5..04475207966 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
@@ -4,30 +4,6 @@
#include "def.h"
-/*
-** mov0:
-** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov0 (int32_t *in, int32_t *out)
-{
- v1si v = *(v1si*)in;
- *(v1si*)out = v;
-}
-
-/*
-** mov1:
-** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov1 (int32_t *in, int32_t *out)
-{
- v2si v = *(v2si*)in;
- *(v2si*)out = v;
-}
-
/*
** mov2:
** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
deleted file mode 100644
index d6dbff1caa9..00000000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-final { check-function-bodies "**" "" } } */
-
-#include "def.h"
-
-/*
-** mov:
-** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
-** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
-** ret
-*/
-void mov (int32_t *in, int32_t *out)
-{
- v2si v = *(v2si*)in;
- *(v2si*)out = v;
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
index 46509e367c3..d0674a47a14 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
@@ -4,18 +4,6 @@
#include "def.h"
-/*
-** mov0:
-** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov0 (int64_t *in, int64_t *out)
-{
- v1di v = *(v1di*)in;
- *(v1di*)out = v;
-}
-
/*
** mov1:
** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
index 1cba7ddad94..b905c74d43b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
@@ -4,42 +4,6 @@
#include "def.h"
-/*
-** mov0:
-** flh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** fsh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov0 (_Float16 *in, _Float16 *out)
-{
- v1hf v = *(v1hf*)in;
- *(v1hf*)out = v;
-}
-
-/*
-** mov1:
-** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov1 (_Float16 *in, _Float16 *out)
-{
- v2hf v = *(v2hf*)in;
- *(v2hf*)out = v;
-}
-
-/*
-** mov2:
-** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov2 (_Float16 *in, _Float16 *out)
-{
- v4hf v = *(v4hf*)in;
- *(v4hf*)out = v;
-}
-
/*
** mov3:
** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
index 0773f6a70f3..5f9bc052e97 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
@@ -4,30 +4,6 @@
#include "def.h"
-/*
-** mov0:
-** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov0 (float *in, float *out)
-{
- v1sf v = *(v1sf*)in;
- *(v1sf*)out = v;
-}
-
-/*
-** mov1:
-** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
-** ret
-*/
-void mov1 (float *in, float *out)
-{
- v2sf v = *(v2sf*)in;
- *(v2sf*)out = v;
-}
-
/*
** mov2:
** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
new file mode 100644
index 00000000000..2e30dc9bfaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
@@ -0,0 +1,31 @@
+! { dg-do compile }
+! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -fallow-argument-mismatch -fmax-stack-var-size=65536 -S -std=legacy -w" }
+
+module a
+ integer,parameter :: SHR_KIND_R8 = selected_real_kind(12)
+end module a
+module b
+ use a, c => shr_kind_r8
+contains
+ subroutine d(cg , km, i1, i2)
+ real (c) ch(i2,km)
+ real (c) cg(4,i1:i2,km)
+ real dc(i2,km)
+ real(c) ci(i2,km)
+ real(c) cj(i2,km)
+ do k=2,ck
+ do i=i1,0
+ cl = ci(i,k) *ci(i,1) / cj(i,k)+ch(i,1)
+ cm = cg(1,i,k) - min(e,cg(1,i,co))
+ dc(i,k) = sign(cm, cl)
+ enddo
+ enddo
+ if ( cq == 0 ) then
+ do i=i1,i2
+ if( cr <= cs ) then
+ cg= sign( min(ct, cg), cg)
+ endif
+ enddo
+ endif
+ end subroutine d
+end module b
--
2.36.3
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
2023-09-26 15:26 [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566] Juzhe-Zhong
@ 2023-09-27 9:33 ` Kito Cheng
2023-09-27 9:38 ` juzhe.zhong
0 siblings, 1 reply; 8+ messages in thread
From: Kito Cheng @ 2023-09-27 9:33 UTC (permalink / raw)
To: Juzhe-Zhong; +Cc: gcc-patches, kito.cheng, jeffreyalaw, rdapp.gcc
> (define_insn_and_split "*mov<mode>"
> [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
> "TARGET_VECTOR
> - && (register_operand (operands[0], <MODE>mode)
> + && (can_create_pseudo_p ()
Why add `can_create_pseudo_p ()` here? this will split after reload,
but we forbid that pattern between reload and split2?
> + || register_operand (operands[0], <MODE>mode)
> || register_operand (operands[1], <MODE>mode))"
> "@
> #
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> index aedf98819bb..24bb7240db8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> @@ -4,54 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** lbu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sb\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (int8_t *in, int8_t *out)
> -{
> - v1qi v = *(v1qi*)in;
> - *(v1qi*)out = v;
> -}
> -
> -/*
> -** mov1:
> -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov1 (int8_t *in, int8_t *out)
> -{
> - v2qi v = *(v2qi*)in;
> - *(v2qi*)out = v;
> -}
> -
> -/*
> -** mov2:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov2 (int8_t *in, int8_t *out)
> -{
> - v4qi v = *(v4qi*)in;
> - *(v4qi*)out = v;
> -}
> -
> -/*
> -** mov3:
> -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov3 (int8_t *in, int8_t *out)
> -{
> - v8qi v = *(v8qi*)in;
> - *(v8qi*)out = v;
> -}
> -
> /*
> ** mov4:
> ** vsetivli\s+zero,\s*16,\s*e8,\s*mf8,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> index 5e9615412b7..cae96b3be3f 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> @@ -4,18 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (double *in, double *out)
> -{
> - v1df v = *(v1df*)in;
> - *(v1df*)out = v;
> -}
> -
> /*
> ** mov1:
> ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
> deleted file mode 100644
> index 10ae1972db7..00000000000
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -/* { dg-do compile } */
> -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> -/* { dg-final { check-function-bodies "**" "" } } */
> -
> -#include "def.h"
> -
> -/*
> -** mov:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov (int8_t *in, int8_t *out)
> -{
> - v8qi v = *(v8qi*)in;
> - *(v8qi*)out = v;
> -}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> index f2880ae5e77..86ce22896c5 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> @@ -4,42 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (int16_t *in, int16_t *out)
> -{
> - v1hi v = *(v1hi*)in;
> - *(v1hi*)out = v;
> -}
> -
> -/*
> -** mov1:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov1 (int16_t *in, int16_t *out)
> -{
> - v2hi v = *(v2hi*)in;
> - *(v2hi*)out = v;
> -}
> -
> -/*
> -** mov2:
> -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov2 (int16_t *in, int16_t *out)
> -{
> - v4hi v = *(v4hi*)in;
> - *(v4hi*)out = v;
> -}
> -
> /*
> ** mov3:
> ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
> deleted file mode 100644
> index f81f1697d65..00000000000
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -/* { dg-do compile } */
> -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> -/* { dg-final { check-function-bodies "**" "" } } */
> -
> -#include "def.h"
> -
> -/*
> -** mov:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov (int16_t *in, int16_t *out)
> -{
> - v4hi v = *(v4hi*)in;
> - *(v4hi*)out = v;
> -}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> index c30ed8f76f5..04475207966 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> @@ -4,30 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (int32_t *in, int32_t *out)
> -{
> - v1si v = *(v1si*)in;
> - *(v1si*)out = v;
> -}
> -
> -/*
> -** mov1:
> -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov1 (int32_t *in, int32_t *out)
> -{
> - v2si v = *(v2si*)in;
> - *(v2si*)out = v;
> -}
> -
> /*
> ** mov2:
> ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
> deleted file mode 100644
> index d6dbff1caa9..00000000000
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -/* { dg-do compile } */
> -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> -/* { dg-final { check-function-bodies "**" "" } } */
> -
> -#include "def.h"
> -
> -/*
> -** mov:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov (int32_t *in, int32_t *out)
> -{
> - v2si v = *(v2si*)in;
> - *(v2si*)out = v;
> -}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> index 46509e367c3..d0674a47a14 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> @@ -4,18 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (int64_t *in, int64_t *out)
> -{
> - v1di v = *(v1di*)in;
> - *(v1di*)out = v;
> -}
> -
> /*
> ** mov1:
> ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> index 1cba7ddad94..b905c74d43b 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> @@ -4,42 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** flh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (_Float16 *in, _Float16 *out)
> -{
> - v1hf v = *(v1hf*)in;
> - *(v1hf*)out = v;
> -}
> -
> -/*
> -** mov1:
> -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov1 (_Float16 *in, _Float16 *out)
> -{
> - v2hf v = *(v2hf*)in;
> - *(v2hf*)out = v;
> -}
> -
> -/*
> -** mov2:
> -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov2 (_Float16 *in, _Float16 *out)
> -{
> - v4hf v = *(v4hf*)in;
> - *(v4hf*)out = v;
> -}
> -
> /*
> ** mov3:
> ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> index 0773f6a70f3..5f9bc052e97 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> @@ -4,30 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (float *in, float *out)
> -{
> - v1sf v = *(v1sf*)in;
> - *(v1sf*)out = v;
> -}
> -
> -/*
> -** mov1:
> -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov1 (float *in, float *out)
> -{
> - v2sf v = *(v2sf*)in;
> - *(v2sf*)out = v;
> -}
> -
> /*
> ** mov2:
> ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
> new file mode 100644
> index 00000000000..2e30dc9bfaa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
> @@ -0,0 +1,31 @@
> +! { dg-do compile }
> +! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -fallow-argument-mismatch -fmax-stack-var-size=65536 -S -std=legacy -w" }
> +
> +module a
> + integer,parameter :: SHR_KIND_R8 = selected_real_kind(12)
> +end module a
> +module b
> + use a, c => shr_kind_r8
> +contains
> + subroutine d(cg , km, i1, i2)
> + real (c) ch(i2,km)
> + real (c) cg(4,i1:i2,km)
> + real dc(i2,km)
> + real(c) ci(i2,km)
> + real(c) cj(i2,km)
> + do k=2,ck
> + do i=i1,0
> + cl = ci(i,k) *ci(i,1) / cj(i,k)+ch(i,1)
> + cm = cg(1,i,k) - min(e,cg(1,i,co))
> + dc(i,k) = sign(cm, cl)
> + enddo
> + enddo
> + if ( cq == 0 ) then
> + do i=i1,i2
> + if( cr <= cs ) then
> + cg= sign( min(ct, cg), cg)
> + endif
> + enddo
> + endif
> + end subroutine d
> +end module b
> --
> 2.36.3
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
2023-09-27 9:33 ` Kito Cheng
@ 2023-09-27 9:38 ` juzhe.zhong
2023-09-27 10:07 ` Kito Cheng
2023-09-27 17:31 ` Jeff Law
0 siblings, 2 replies; 8+ messages in thread
From: juzhe.zhong @ 2023-09-27 9:38 UTC (permalink / raw)
To: kito.cheng; +Cc: gcc-patches, Kito.cheng, jeffreyalaw, Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 11560 bytes --]
>> Why add `can_create_pseudo_p ()` here? this will split after reload,
>> but we forbid that pattern between reload and split2?
I have no ideal. Some fortran tests just need recognization of mem-to-mem pattern before RA.
I don't know the reason.
juzhe.zhong@rivai.ai
From: Kito Cheng
Date: 2023-09-27 17:33
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
> (define_insn_and_split "*mov<mode>"
> [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
> "TARGET_VECTOR
> - && (register_operand (operands[0], <MODE>mode)
> + && (can_create_pseudo_p ()
Why add `can_create_pseudo_p ()` here? this will split after reload,
but we forbid that pattern between reload and split2?
> + || register_operand (operands[0], <MODE>mode)
> || register_operand (operands[1], <MODE>mode))"
> "@
> #
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> index aedf98819bb..24bb7240db8 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> @@ -4,54 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** lbu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sb\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (int8_t *in, int8_t *out)
> -{
> - v1qi v = *(v1qi*)in;
> - *(v1qi*)out = v;
> -}
> -
> -/*
> -** mov1:
> -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov1 (int8_t *in, int8_t *out)
> -{
> - v2qi v = *(v2qi*)in;
> - *(v2qi*)out = v;
> -}
> -
> -/*
> -** mov2:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov2 (int8_t *in, int8_t *out)
> -{
> - v4qi v = *(v4qi*)in;
> - *(v4qi*)out = v;
> -}
> -
> -/*
> -** mov3:
> -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov3 (int8_t *in, int8_t *out)
> -{
> - v8qi v = *(v8qi*)in;
> - *(v8qi*)out = v;
> -}
> -
> /*
> ** mov4:
> ** vsetivli\s+zero,\s*16,\s*e8,\s*mf8,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> index 5e9615412b7..cae96b3be3f 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> @@ -4,18 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (double *in, double *out)
> -{
> - v1df v = *(v1df*)in;
> - *(v1df*)out = v;
> -}
> -
> /*
> ** mov1:
> ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
> deleted file mode 100644
> index 10ae1972db7..00000000000
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -/* { dg-do compile } */
> -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> -/* { dg-final { check-function-bodies "**" "" } } */
> -
> -#include "def.h"
> -
> -/*
> -** mov:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov (int8_t *in, int8_t *out)
> -{
> - v8qi v = *(v8qi*)in;
> - *(v8qi*)out = v;
> -}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> index f2880ae5e77..86ce22896c5 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> @@ -4,42 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (int16_t *in, int16_t *out)
> -{
> - v1hi v = *(v1hi*)in;
> - *(v1hi*)out = v;
> -}
> -
> -/*
> -** mov1:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov1 (int16_t *in, int16_t *out)
> -{
> - v2hi v = *(v2hi*)in;
> - *(v2hi*)out = v;
> -}
> -
> -/*
> -** mov2:
> -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov2 (int16_t *in, int16_t *out)
> -{
> - v4hi v = *(v4hi*)in;
> - *(v4hi*)out = v;
> -}
> -
> /*
> ** mov3:
> ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
> deleted file mode 100644
> index f81f1697d65..00000000000
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -/* { dg-do compile } */
> -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> -/* { dg-final { check-function-bodies "**" "" } } */
> -
> -#include "def.h"
> -
> -/*
> -** mov:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov (int16_t *in, int16_t *out)
> -{
> - v4hi v = *(v4hi*)in;
> - *(v4hi*)out = v;
> -}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> index c30ed8f76f5..04475207966 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> @@ -4,30 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (int32_t *in, int32_t *out)
> -{
> - v1si v = *(v1si*)in;
> - *(v1si*)out = v;
> -}
> -
> -/*
> -** mov1:
> -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov1 (int32_t *in, int32_t *out)
> -{
> - v2si v = *(v2si*)in;
> - *(v2si*)out = v;
> -}
> -
> /*
> ** mov2:
> ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
> deleted file mode 100644
> index d6dbff1caa9..00000000000
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -/* { dg-do compile } */
> -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> -/* { dg-final { check-function-bodies "**" "" } } */
> -
> -#include "def.h"
> -
> -/*
> -** mov:
> -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov (int32_t *in, int32_t *out)
> -{
> - v2si v = *(v2si*)in;
> - *(v2si*)out = v;
> -}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> index 46509e367c3..d0674a47a14 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> @@ -4,18 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (int64_t *in, int64_t *out)
> -{
> - v1di v = *(v1di*)in;
> - *(v1di*)out = v;
> -}
> -
> /*
> ** mov1:
> ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> index 1cba7ddad94..b905c74d43b 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> @@ -4,42 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** flh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (_Float16 *in, _Float16 *out)
> -{
> - v1hf v = *(v1hf*)in;
> - *(v1hf*)out = v;
> -}
> -
> -/*
> -** mov1:
> -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov1 (_Float16 *in, _Float16 *out)
> -{
> - v2hf v = *(v2hf*)in;
> - *(v2hf*)out = v;
> -}
> -
> -/*
> -** mov2:
> -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov2 (_Float16 *in, _Float16 *out)
> -{
> - v4hf v = *(v4hf*)in;
> - *(v4hf*)out = v;
> -}
> -
> /*
> ** mov3:
> ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> index 0773f6a70f3..5f9bc052e97 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> @@ -4,30 +4,6 @@
>
> #include "def.h"
>
> -/*
> -** mov0:
> -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov0 (float *in, float *out)
> -{
> - v1sf v = *(v1sf*)in;
> - *(v1sf*)out = v;
> -}
> -
> -/*
> -** mov1:
> -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> -** ret
> -*/
> -void mov1 (float *in, float *out)
> -{
> - v2sf v = *(v2sf*)in;
> - *(v2sf*)out = v;
> -}
> -
> /*
> ** mov2:
> ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
> new file mode 100644
> index 00000000000..2e30dc9bfaa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
> @@ -0,0 +1,31 @@
> +! { dg-do compile }
> +! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -fallow-argument-mismatch -fmax-stack-var-size=65536 -S -std=legacy -w" }
> +
> +module a
> + integer,parameter :: SHR_KIND_R8 = selected_real_kind(12)
> +end module a
> +module b
> + use a, c => shr_kind_r8
> +contains
> + subroutine d(cg , km, i1, i2)
> + real (c) ch(i2,km)
> + real (c) cg(4,i1:i2,km)
> + real dc(i2,km)
> + real(c) ci(i2,km)
> + real(c) cj(i2,km)
> + do k=2,ck
> + do i=i1,0
> + cl = ci(i,k) *ci(i,1) / cj(i,k)+ch(i,1)
> + cm = cg(1,i,k) - min(e,cg(1,i,co))
> + dc(i,k) = sign(cm, cl)
> + enddo
> + enddo
> + if ( cq == 0 ) then
> + do i=i1,i2
> + if( cr <= cs ) then
> + cg= sign( min(ct, cg), cg)
> + endif
> + enddo
> + endif
> + end subroutine d
> +end module b
> --
> 2.36.3
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
2023-09-27 9:38 ` juzhe.zhong
@ 2023-09-27 10:07 ` Kito Cheng
2023-09-27 10:14 ` juzhe.zhong
2023-09-27 17:31 ` Jeff Law
1 sibling, 1 reply; 8+ messages in thread
From: Kito Cheng @ 2023-09-27 10:07 UTC (permalink / raw)
To: juzhe.zhong; +Cc: kito.cheng, gcc-patches, jeffreyalaw, Robin Dapp
I can understand why remove mem to mem pattern, but why the normal mov
pattern for VLS_AVL_IMM need to change too?
On Wed, Sep 27, 2023 at 10:39 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> >> Why add `can_create_pseudo_p ()` here? this will split after reload,
> >> but we forbid that pattern between reload and split2?
>
> I have no ideal. Some fortran tests just need recognization of mem-to-mem pattern before RA.
> I don't know the reason.
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-09-27 17:33
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> Subject: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
> > (define_insn_and_split "*mov<mode>"
> > [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> > (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
> > "TARGET_VECTOR
> > - && (register_operand (operands[0], <MODE>mode)
> > + && (can_create_pseudo_p ()
>
> Why add `can_create_pseudo_p ()` here? this will split after reload,
> but we forbid that pattern between reload and split2?
>
> > + || register_operand (operands[0], <MODE>mode)
> > || register_operand (operands[1], <MODE>mode))"
> > "@
> > #
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> > index aedf98819bb..24bb7240db8 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> > @@ -4,54 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** lbu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sb\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int8_t *in, int8_t *out)
> > -{
> > - v1qi v = *(v1qi*)in;
> > - *(v1qi*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (int8_t *in, int8_t *out)
> > -{
> > - v2qi v = *(v2qi*)in;
> > - *(v2qi*)out = v;
> > -}
> > -
> > -/*
> > -** mov2:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov2 (int8_t *in, int8_t *out)
> > -{
> > - v4qi v = *(v4qi*)in;
> > - *(v4qi*)out = v;
> > -}
> > -
> > -/*
> > -** mov3:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov3 (int8_t *in, int8_t *out)
> > -{
> > - v8qi v = *(v8qi*)in;
> > - *(v8qi*)out = v;
> > -}
> > -
> > /*
> > ** mov4:
> > ** vsetivli\s+zero,\s*16,\s*e8,\s*mf8,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> > index 5e9615412b7..cae96b3be3f 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> > @@ -4,18 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (double *in, double *out)
> > -{
> > - v1df v = *(v1df*)in;
> > - *(v1df*)out = v;
> > -}
> > -
> > /*
> > ** mov1:
> > ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
> > deleted file mode 100644
> > index 10ae1972db7..00000000000
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
> > +++ /dev/null
> > @@ -1,19 +0,0 @@
> > -/* { dg-do compile } */
> > -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> > -/* { dg-final { check-function-bodies "**" "" } } */
> > -
> > -#include "def.h"
> > -
> > -/*
> > -** mov:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov (int8_t *in, int8_t *out)
> > -{
> > - v8qi v = *(v8qi*)in;
> > - *(v8qi*)out = v;
> > -}
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> > index f2880ae5e77..86ce22896c5 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> > @@ -4,42 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int16_t *in, int16_t *out)
> > -{
> > - v1hi v = *(v1hi*)in;
> > - *(v1hi*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (int16_t *in, int16_t *out)
> > -{
> > - v2hi v = *(v2hi*)in;
> > - *(v2hi*)out = v;
> > -}
> > -
> > -/*
> > -** mov2:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov2 (int16_t *in, int16_t *out)
> > -{
> > - v4hi v = *(v4hi*)in;
> > - *(v4hi*)out = v;
> > -}
> > -
> > /*
> > ** mov3:
> > ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
> > deleted file mode 100644
> > index f81f1697d65..00000000000
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
> > +++ /dev/null
> > @@ -1,19 +0,0 @@
> > -/* { dg-do compile } */
> > -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> > -/* { dg-final { check-function-bodies "**" "" } } */
> > -
> > -#include "def.h"
> > -
> > -/*
> > -** mov:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov (int16_t *in, int16_t *out)
> > -{
> > - v4hi v = *(v4hi*)in;
> > - *(v4hi*)out = v;
> > -}
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> > index c30ed8f76f5..04475207966 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> > @@ -4,30 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int32_t *in, int32_t *out)
> > -{
> > - v1si v = *(v1si*)in;
> > - *(v1si*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (int32_t *in, int32_t *out)
> > -{
> > - v2si v = *(v2si*)in;
> > - *(v2si*)out = v;
> > -}
> > -
> > /*
> > ** mov2:
> > ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
> > deleted file mode 100644
> > index d6dbff1caa9..00000000000
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
> > +++ /dev/null
> > @@ -1,19 +0,0 @@
> > -/* { dg-do compile } */
> > -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> > -/* { dg-final { check-function-bodies "**" "" } } */
> > -
> > -#include "def.h"
> > -
> > -/*
> > -** mov:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov (int32_t *in, int32_t *out)
> > -{
> > - v2si v = *(v2si*)in;
> > - *(v2si*)out = v;
> > -}
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> > index 46509e367c3..d0674a47a14 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> > @@ -4,18 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int64_t *in, int64_t *out)
> > -{
> > - v1di v = *(v1di*)in;
> > - *(v1di*)out = v;
> > -}
> > -
> > /*
> > ** mov1:
> > ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> > index 1cba7ddad94..b905c74d43b 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> > @@ -4,42 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** flh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (_Float16 *in, _Float16 *out)
> > -{
> > - v1hf v = *(v1hf*)in;
> > - *(v1hf*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (_Float16 *in, _Float16 *out)
> > -{
> > - v2hf v = *(v2hf*)in;
> > - *(v2hf*)out = v;
> > -}
> > -
> > -/*
> > -** mov2:
> > -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov2 (_Float16 *in, _Float16 *out)
> > -{
> > - v4hf v = *(v4hf*)in;
> > - *(v4hf*)out = v;
> > -}
> > -
> > /*
> > ** mov3:
> > ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> > index 0773f6a70f3..5f9bc052e97 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> > @@ -4,30 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (float *in, float *out)
> > -{
> > - v1sf v = *(v1sf*)in;
> > - *(v1sf*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (float *in, float *out)
> > -{
> > - v2sf v = *(v2sf*)in;
> > - *(v2sf*)out = v;
> > -}
> > -
> > /*
> > ** mov2:
> > ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
> > new file mode 100644
> > index 00000000000..2e30dc9bfaa
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
> > @@ -0,0 +1,31 @@
> > +! { dg-do compile }
> > +! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -fallow-argument-mismatch -fmax-stack-var-size=65536 -S -std=legacy -w" }
> > +
> > +module a
> > + integer,parameter :: SHR_KIND_R8 = selected_real_kind(12)
> > +end module a
> > +module b
> > + use a, c => shr_kind_r8
> > +contains
> > + subroutine d(cg , km, i1, i2)
> > + real (c) ch(i2,km)
> > + real (c) cg(4,i1:i2,km)
> > + real dc(i2,km)
> > + real(c) ci(i2,km)
> > + real(c) cj(i2,km)
> > + do k=2,ck
> > + do i=i1,0
> > + cl = ci(i,k) *ci(i,1) / cj(i,k)+ch(i,1)
> > + cm = cg(1,i,k) - min(e,cg(1,i,co))
> > + dc(i,k) = sign(cm, cl)
> > + enddo
> > + enddo
> > + if ( cq == 0 ) then
> > + do i=i1,i2
> > + if( cr <= cs ) then
> > + cg= sign( min(ct, cg), cg)
> > + endif
> > + enddo
> > + endif
> > + end subroutine d
> > +end module b
> > --
> > 2.36.3
> >
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
2023-09-27 10:07 ` Kito Cheng
@ 2023-09-27 10:14 ` juzhe.zhong
2023-09-27 17:31 ` Jeff Law
0 siblings, 1 reply; 8+ messages in thread
From: juzhe.zhong @ 2023-09-27 10:14 UTC (permalink / raw)
To: Kito.cheng; +Cc: kito.cheng, gcc-patches, jeffreyalaw, Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 13174 bytes --]
Since after removing mem-to-mem pattern.
program main
integer, dimension(:,:), allocatable :: a, b
integer, dimension(:), allocatable :: sh
allocate (a(2,2))
allocate (b(2,2))
allocate (sh(3))
a = 1
b = cshift(a,sh)
end program main
This case will failed if we don't change mov pattern.
juzhe.zhong@rivai.ai
From: Kito Cheng
Date: 2023-09-27 18:07
To: juzhe.zhong@rivai.ai
CC: kito.cheng; gcc-patches; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
I can understand why remove mem to mem pattern, but why the normal mov
pattern for VLS_AVL_IMM need to change too?
On Wed, Sep 27, 2023 at 10:39 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> >> Why add `can_create_pseudo_p ()` here? this will split after reload,
> >> but we forbid that pattern between reload and split2?
>
> I have no ideal. Some fortran tests just need recognization of mem-to-mem pattern before RA.
> I don't know the reason.
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-09-27 17:33
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> Subject: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
> > (define_insn_and_split "*mov<mode>"
> > [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> > (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
> > "TARGET_VECTOR
> > - && (register_operand (operands[0], <MODE>mode)
> > + && (can_create_pseudo_p ()
>
> Why add `can_create_pseudo_p ()` here? this will split after reload,
> but we forbid that pattern between reload and split2?
>
> > + || register_operand (operands[0], <MODE>mode)
> > || register_operand (operands[1], <MODE>mode))"
> > "@
> > #
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> > index aedf98819bb..24bb7240db8 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> > @@ -4,54 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** lbu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sb\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int8_t *in, int8_t *out)
> > -{
> > - v1qi v = *(v1qi*)in;
> > - *(v1qi*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (int8_t *in, int8_t *out)
> > -{
> > - v2qi v = *(v2qi*)in;
> > - *(v2qi*)out = v;
> > -}
> > -
> > -/*
> > -** mov2:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov2 (int8_t *in, int8_t *out)
> > -{
> > - v4qi v = *(v4qi*)in;
> > - *(v4qi*)out = v;
> > -}
> > -
> > -/*
> > -** mov3:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov3 (int8_t *in, int8_t *out)
> > -{
> > - v8qi v = *(v8qi*)in;
> > - *(v8qi*)out = v;
> > -}
> > -
> > /*
> > ** mov4:
> > ** vsetivli\s+zero,\s*16,\s*e8,\s*mf8,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> > index 5e9615412b7..cae96b3be3f 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> > @@ -4,18 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (double *in, double *out)
> > -{
> > - v1df v = *(v1df*)in;
> > - *(v1df*)out = v;
> > -}
> > -
> > /*
> > ** mov1:
> > ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
> > deleted file mode 100644
> > index 10ae1972db7..00000000000
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
> > +++ /dev/null
> > @@ -1,19 +0,0 @@
> > -/* { dg-do compile } */
> > -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> > -/* { dg-final { check-function-bodies "**" "" } } */
> > -
> > -#include "def.h"
> > -
> > -/*
> > -** mov:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov (int8_t *in, int8_t *out)
> > -{
> > - v8qi v = *(v8qi*)in;
> > - *(v8qi*)out = v;
> > -}
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> > index f2880ae5e77..86ce22896c5 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> > @@ -4,42 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int16_t *in, int16_t *out)
> > -{
> > - v1hi v = *(v1hi*)in;
> > - *(v1hi*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (int16_t *in, int16_t *out)
> > -{
> > - v2hi v = *(v2hi*)in;
> > - *(v2hi*)out = v;
> > -}
> > -
> > -/*
> > -** mov2:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov2 (int16_t *in, int16_t *out)
> > -{
> > - v4hi v = *(v4hi*)in;
> > - *(v4hi*)out = v;
> > -}
> > -
> > /*
> > ** mov3:
> > ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
> > deleted file mode 100644
> > index f81f1697d65..00000000000
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
> > +++ /dev/null
> > @@ -1,19 +0,0 @@
> > -/* { dg-do compile } */
> > -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> > -/* { dg-final { check-function-bodies "**" "" } } */
> > -
> > -#include "def.h"
> > -
> > -/*
> > -** mov:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov (int16_t *in, int16_t *out)
> > -{
> > - v4hi v = *(v4hi*)in;
> > - *(v4hi*)out = v;
> > -}
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> > index c30ed8f76f5..04475207966 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> > @@ -4,30 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int32_t *in, int32_t *out)
> > -{
> > - v1si v = *(v1si*)in;
> > - *(v1si*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (int32_t *in, int32_t *out)
> > -{
> > - v2si v = *(v2si*)in;
> > - *(v2si*)out = v;
> > -}
> > -
> > /*
> > ** mov2:
> > ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
> > deleted file mode 100644
> > index d6dbff1caa9..00000000000
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
> > +++ /dev/null
> > @@ -1,19 +0,0 @@
> > -/* { dg-do compile } */
> > -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
> > -/* { dg-final { check-function-bodies "**" "" } } */
> > -
> > -#include "def.h"
> > -
> > -/*
> > -** mov:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov (int32_t *in, int32_t *out)
> > -{
> > - v2si v = *(v2si*)in;
> > - *(v2si*)out = v;
> > -}
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> > index 46509e367c3..d0674a47a14 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> > @@ -4,18 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int64_t *in, int64_t *out)
> > -{
> > - v1di v = *(v1di*)in;
> > - *(v1di*)out = v;
> > -}
> > -
> > /*
> > ** mov1:
> > ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> > index 1cba7ddad94..b905c74d43b 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> > @@ -4,42 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** flh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (_Float16 *in, _Float16 *out)
> > -{
> > - v1hf v = *(v1hf*)in;
> > - *(v1hf*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (_Float16 *in, _Float16 *out)
> > -{
> > - v2hf v = *(v2hf*)in;
> > - *(v2hf*)out = v;
> > -}
> > -
> > -/*
> > -** mov2:
> > -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov2 (_Float16 *in, _Float16 *out)
> > -{
> > - v4hf v = *(v4hf*)in;
> > - *(v4hf*)out = v;
> > -}
> > -
> > /*
> > ** mov3:
> > ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> > index 0773f6a70f3..5f9bc052e97 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> > @@ -4,30 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (float *in, float *out)
> > -{
> > - v1sf v = *(v1sf*)in;
> > - *(v1sf*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (float *in, float *out)
> > -{
> > - v2sf v = *(v2sf*)in;
> > - *(v2sf*)out = v;
> > -}
> > -
> > /*
> > ** mov2:
> > ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
> > new file mode 100644
> > index 00000000000..2e30dc9bfaa
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
> > @@ -0,0 +1,31 @@
> > +! { dg-do compile }
> > +! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -fallow-argument-mismatch -fmax-stack-var-size=65536 -S -std=legacy -w" }
> > +
> > +module a
> > + integer,parameter :: SHR_KIND_R8 = selected_real_kind(12)
> > +end module a
> > +module b
> > + use a, c => shr_kind_r8
> > +contains
> > + subroutine d(cg , km, i1, i2)
> > + real (c) ch(i2,km)
> > + real (c) cg(4,i1:i2,km)
> > + real dc(i2,km)
> > + real(c) ci(i2,km)
> > + real(c) cj(i2,km)
> > + do k=2,ck
> > + do i=i1,0
> > + cl = ci(i,k) *ci(i,1) / cj(i,k)+ch(i,1)
> > + cm = cg(1,i,k) - min(e,cg(1,i,co))
> > + dc(i,k) = sign(cm, cl)
> > + enddo
> > + enddo
> > + if ( cq == 0 ) then
> > + do i=i1,i2
> > + if( cr <= cs ) then
> > + cg= sign( min(ct, cg), cg)
> > + endif
> > + enddo
> > + endif
> > + end subroutine d
> > +end module b
> > --
> > 2.36.3
> >
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
2023-09-27 10:14 ` juzhe.zhong
@ 2023-09-27 17:31 ` Jeff Law
2023-09-27 18:08 ` Toon Moene
0 siblings, 1 reply; 8+ messages in thread
From: Jeff Law @ 2023-09-27 17:31 UTC (permalink / raw)
To: juzhe.zhong, Kito.cheng; +Cc: kito.cheng, gcc-patches, Robin Dapp
On 9/27/23 04:14, juzhe.zhong@rivai.ai wrote:
> Since after removing mem-to-mem pattern.
>
> program main
> integer, dimension(:,:), allocatable :: a, b
> integer, dimension(:), allocatable :: sh
> allocate (a(2,2))
> allocate (b(2,2))
> allocate (sh(3))
> a = 1
> b = cshift(a,sh)
> end program main
>
> This case will failed if we don't change mov pattern.
Can you expand on this? You didn't indicate the failure mode or any
analysis behind the failure.
jeff
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
2023-09-27 17:31 ` Jeff Law
@ 2023-09-27 18:08 ` Toon Moene
0 siblings, 0 replies; 8+ messages in thread
From: Toon Moene @ 2023-09-27 18:08 UTC (permalink / raw)
To: Jeff Law, juzhe.zhong, Kito.cheng; +Cc: kito.cheng, gcc-patches, Robin Dapp
On 9/27/23 19:31, Jeff Law wrote:
>
>
> On 9/27/23 04:14, juzhe.zhong@rivai.ai wrote:
>> Since after removing mem-to-mem pattern.
>>
>> program main
>> integer, dimension(:,:), allocatable :: a, b
>> integer, dimension(:), allocatable :: sh
>> allocate (a(2,2))
>> allocate (b(2,2))
>> allocate (sh(3))
>> a = 1
>> b = cshift(a,sh)
>> end program main
>>
>> This case will failed if we don't change mov pattern.
> Can you expand on this? You didn't indicate the failure mode or any
> analysis behind the failure.
>
> jeff
Note that this Fortran code has no defined behavior, because the sh
array isn't given any values ...
Kind regards,
--
Toon Moene - e-mail: toon@moene.org - phone: +31 346 214290
Saturnushof 14, 3738 XG Maartensdijk, The Netherlands
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
2023-09-27 9:38 ` juzhe.zhong
2023-09-27 10:07 ` Kito Cheng
@ 2023-09-27 17:31 ` Jeff Law
1 sibling, 0 replies; 8+ messages in thread
From: Jeff Law @ 2023-09-27 17:31 UTC (permalink / raw)
To: juzhe.zhong, kito.cheng; +Cc: gcc-patches, Kito.cheng, Robin Dapp
On 9/27/23 03:38, juzhe.zhong@rivai.ai wrote:
> >> Why add `can_create_pseudo_p ()` here? this will split after reload,
>>>but we forbid that pattern between reload and split2?
>
> I have no ideal. Some fortran tests just need recognization of
> mem-to-mem pattern before RA
> I don't know the reason.
But isn't that the key to understanding what's going on here?
There is nothing special about Fortran here. Whatever problem this is
working around will almost certainly show up again in other,
non-Fortran, contexts.
There aren't enough details in here to really evaluate what's going on.
jeff
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-09-27 18:08 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-26 15:26 [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566] Juzhe-Zhong
2023-09-27 9:33 ` Kito Cheng
2023-09-27 9:38 ` juzhe.zhong
2023-09-27 10:07 ` Kito Cheng
2023-09-27 10:14 ` juzhe.zhong
2023-09-27 17:31 ` Jeff Law
2023-09-27 18:08 ` Toon Moene
2023-09-27 17:31 ` Jeff Law
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