From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by sourceware.org (Postfix) with ESMTPS id 2B2B93870C35 for ; Wed, 27 Sep 2023 12:26:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2B2B93870C35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-405497850dbso89714795e9.0 for ; Wed, 27 Sep 2023 05:26:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1695817605; x=1696422405; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TU/vbSu+Ofcvc0dcrwW+an/8RYnuUYhjkLvw7JUbFDY=; b=GVre3ZgME61oxlzxSo9mWMwrcLz2edtaldkZyfd1oTdY2xl2bASV7hHQyb4eCuaAtu zpVHcU6XNZSFgu5Z49hzKu/CB/nXROmbmvnTrfFWzn2kw8X5Kk04/NqUYLbEAD3has3n bJC43ScdbuqdxZ/3vfpEAHPKxGCSOlGF7d64LRo2pUOhDnvnip+N4RXMHVTUxvC8R0EC 0QJqqTbhObqTUzTIvFPXPbremYHeCj6ewvZodlrZsuCUlYkRDAB1lHIEDa+6MzERMSOe GToG8qZQua0hAiA3hdmXJ7/fUOHe/yUYBQOp9v7NuuLjK4GESIdcZn+ECTo/vb6s9iDj FU4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695817605; x=1696422405; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TU/vbSu+Ofcvc0dcrwW+an/8RYnuUYhjkLvw7JUbFDY=; b=LEr9mHwSQ+pbnF8b9mYFulAZNgr/8AYRYcoYidXdh8AYyJbT6C1Y+edSb8UPSqMSRK VvZtDcG9rUngu4ly8a/cd1YhS7aOjdEqohE0aEhmAAOZhgQFV7HpWiZ0QUyF6/m+2MXj 7mgJRLYe/4OwoWKr/ZEBh9p1MjDfKpCL9CnVmgPSKMJ9T0uujE/oPmuKGqK+haMY2mti jBV/Qec2z5Tr1Bq5d8iDNeyc1+sAHg9qH99tOuJ/dLE/iI4+rnY47J5U8mxi2HFb+SXx Uh7WePjf94s26PZgp/qnVN1EKo+67KuV1Ri/XKvR5S7MZvm1Z/NgeWKSYeBLgFFX+jgl UXIQ== X-Gm-Message-State: AOJu0YzfteyceI1JnsikCf+5U+mUOoNfyWmpY0xqGNMcK+RFHQZj7C7/ SG5zxNH2ULcnjAGf7C/VrWyko4pggpi/A9mYHWviNQ== X-Google-Smtp-Source: AGHT+IFqJsNxUADM/YX7EELiT35TCQq6Xafzlu7DJlpNcRKSc/33v9VCJjnm6SU9oBaA9VyY5nGkWA== X-Received: by 2002:a7b:c415:0:b0:3fe:1cac:37d5 with SMTP id k21-20020a7bc415000000b003fe1cac37d5mr1848987wmi.4.1695817604668; Wed, 27 Sep 2023 05:26:44 -0700 (PDT) Received: from troughton.sou.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id 20-20020a05600c021400b0040607da271asm5119857wmi.31.2023.09.27.05.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 05:26:44 -0700 (PDT) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com, kito.cheng@gmail.com Subject: [PATCH v2 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Date: Wed, 27 Sep 2023 13:26:24 +0100 Message-Id: <20230927122626.775649-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230919150734.2854664-1-mary.bennett@embecosm.com> References: <20230919150734.2854664-1-mary.bennett@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch series presents the comprehensive implementation of the MAC and ALU extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin RISC-V: Add support for XCValu extension in CV32E40P RISC-V: Add support for XCVmac extension in CV32E40P gcc/common/config/riscv/riscv-common.cc | 6 + gcc/config/riscv/constraints.md | 7 + gcc/config/riscv/corev.def | 43 ++ gcc/config/riscv/corev.md | 693 ++++++++++++++++++ gcc/config/riscv/predicates.md | 5 + gcc/config/riscv/riscv-builtins.cc | 13 + gcc/config/riscv/riscv-ftypes.def | 11 + gcc/config/riscv/riscv-opts.h | 7 + gcc/config/riscv/riscv.cc | 7 + gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/riscv.opt | 3 + gcc/doc/extend.texi | 174 +++++ .../gcc.target/riscv/cv-alu-compile.c | 252 +++++++ .../riscv/cv-alu-fail-compile-addn.c | 11 + .../riscv/cv-alu-fail-compile-addrn.c | 11 + .../riscv/cv-alu-fail-compile-addun.c | 11 + .../riscv/cv-alu-fail-compile-addurn.c | 11 + .../riscv/cv-alu-fail-compile-clip.c | 11 + .../riscv/cv-alu-fail-compile-clipu.c | 11 + .../riscv/cv-alu-fail-compile-subn.c | 11 + .../riscv/cv-alu-fail-compile-subrn.c | 11 + .../riscv/cv-alu-fail-compile-subun.c | 11 + .../riscv/cv-alu-fail-compile-suburn.c | 11 + .../gcc.target/riscv/cv-alu-fail-compile.c | 32 + .../gcc.target/riscv/cv-mac-compile.c | 198 +++++ .../riscv/cv-mac-fail-compile-mac.c | 25 + .../riscv/cv-mac-fail-compile-machhsn.c | 24 + .../riscv/cv-mac-fail-compile-machhsrn.c | 24 + .../riscv/cv-mac-fail-compile-machhun.c | 24 + .../riscv/cv-mac-fail-compile-machhurn.c | 24 + .../riscv/cv-mac-fail-compile-macsn.c | 24 + .../riscv/cv-mac-fail-compile-macsrn.c | 24 + .../riscv/cv-mac-fail-compile-macun.c | 24 + .../riscv/cv-mac-fail-compile-macurn.c | 24 + .../riscv/cv-mac-fail-compile-msu.c | 25 + .../riscv/cv-mac-fail-compile-mulhhsn.c | 24 + .../riscv/cv-mac-fail-compile-mulhhsrn.c | 24 + .../riscv/cv-mac-fail-compile-mulhhun.c | 24 + .../riscv/cv-mac-fail-compile-mulhhurn.c | 24 + .../riscv/cv-mac-fail-compile-mulsn.c | 24 + .../riscv/cv-mac-fail-compile-mulsrn.c | 24 + .../riscv/cv-mac-fail-compile-mulun.c | 24 + .../riscv/cv-mac-fail-compile-mulurn.c | 24 + .../riscv/cv-mac-test-autogeneration.c | 18 + gcc/testsuite/lib/target-supports.exp | 26 + 45 files changed, 2040 insertions(+) create mode 100644 gcc/config/riscv/corev.def create mode 100644 gcc/config/riscv/corev.md create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-msu.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-test-autogeneration.c -- 2.34.1