From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by sourceware.org (Postfix) with ESMTPS id 586533858C39 for ; Sat, 30 Sep 2023 12:01:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 586533858C39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-406618d0992so11175945e9.0 for ; Sat, 30 Sep 2023 05:01:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1696075290; x=1696680090; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ay4o+jAX31G3jAtwAg+Fwq4b+Bho/RkI0G6bIRMTIMk=; b=IJoV/SJ8uxEePj2NFKmiWNYRJ6OyCmJhh3qYJjHW8KUsLXySqzRQKj7oJOcVxbQGhR X26DcvOo/urmWyqde/r9/M2+ycfQy/Ra4d/gFJm1hUFwy2dYYoyxxTpQ6WA2rZ5NgkL+ NDJF0QqB6KDpCHTa+P+UrUHxKM5JBs5ahCp7nCMiXsF6DbyH+AmkLQ1JZBvcv3CdygEH AzGe2wM0lPE5sGwRXfPyHEYFKFHXJTE1DCXA5ud89CzDUMOozDT/4xiPga3vaKjYX2ul zHI+Mc7QrilteJX/tWcjLcrc5RD+U1OGNxCiE4SloyhyMRrT8p9DXFUlEYE65GytDhJH nKlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696075290; x=1696680090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ay4o+jAX31G3jAtwAg+Fwq4b+Bho/RkI0G6bIRMTIMk=; b=RQJQaWZEvvAHFiq8+3Ja8arakHSWsUUo3QQWSK7Zs5iuQaGKk2stitKulAIZgxO/iY OXQ+4+qunf/fC2zVnUD55s0nu2yufK6qZrMlEqtGq4s/U8p4qXTADSLMALIdurto2H+y mlvHOTVGtWNk7dbCpFPVAQtbOi7GlBYd2T41sG+JjRDcdUf/UxPUYhTFp3C/ZfijwLo0 hAz2/otM4b1pacqyZmXrccj93sbeObloJEKcY4nBzioiGcuhXp/xLW81N2xBJ9yDPwzG aB1n793/eJBe0X2Aqw2qlKHd3kTgzBn6tbFTipFHa5lEvqi8hLG2vX91lfo58IGtvlOq m3nw== X-Gm-Message-State: AOJu0YxzWGUSvPVa4ib0ICPeZzLanfQAvyzo8wL4N8R8rONKRTTwW9K7 zm3NbGOu6TFgnppR2bWjql0oXkupUUBKG45AICQ= X-Google-Smtp-Source: AGHT+IGP689BMKIx/KuN68CxE8YkXdEHYdRkA9XXOURb2czFjSCbuNfjN9cRsoW3wOPN31nU0q08UA== X-Received: by 2002:a05:600c:2981:b0:405:4f78:e128 with SMTP id r1-20020a05600c298100b004054f78e128mr6204007wmd.4.1696075290484; Sat, 30 Sep 2023 05:01:30 -0700 (PDT) Received: from troughton.sou.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id z7-20020adfec87000000b0032179c4a46dsm5986874wrn.100.2023.09.30.05.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Sep 2023 05:01:29 -0700 (PDT) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com, rep.dot.nop@gmail.com Subject: [PATCH v3 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Date: Sat, 30 Sep 2023 13:00:36 +0100 Message-Id: <20230930120038.3110583-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230927122626.775649-1-mary.bennett@embecosm.com> References: <20230927122626.775649-1-mary.bennett@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Thank you for reviewing this patch. v1->v2: * Add XCValu RTL. * Change assembly mnemonics from mixed case to lower case. v2->v3: * Change commit message from past tense to present. * Add documentation for new dg-effective-targets. This patch series presents the comprehensive implementation of the MAC and ALU extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin RISC-V: Add support for XCValu extension in CV32E40P RISC-V: Add support for XCVmac extension in CV32E40P gcc/common/config/riscv/riscv-common.cc | 6 + gcc/config/riscv/constraints.md | 7 + gcc/config/riscv/corev.def | 43 ++ gcc/config/riscv/corev.md | 693 ++++++++++++++++++ gcc/config/riscv/predicates.md | 5 + gcc/config/riscv/riscv-builtins.cc | 13 + gcc/config/riscv/riscv-ftypes.def | 11 + gcc/config/riscv/riscv-opts.h | 7 + gcc/config/riscv/riscv.cc | 7 + gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/riscv.opt | 3 + gcc/doc/extend.texi | 174 +++++ gcc/doc/sourcebuild.texi | 12 + .../gcc.target/riscv/cv-alu-compile.c | 252 +++++++ .../riscv/cv-alu-fail-compile-addn.c | 11 + .../riscv/cv-alu-fail-compile-addrn.c | 11 + .../riscv/cv-alu-fail-compile-addun.c | 11 + .../riscv/cv-alu-fail-compile-addurn.c | 11 + .../riscv/cv-alu-fail-compile-clip.c | 11 + .../riscv/cv-alu-fail-compile-clipu.c | 11 + .../riscv/cv-alu-fail-compile-subn.c | 11 + .../riscv/cv-alu-fail-compile-subrn.c | 11 + .../riscv/cv-alu-fail-compile-subun.c | 11 + .../riscv/cv-alu-fail-compile-suburn.c | 11 + .../gcc.target/riscv/cv-alu-fail-compile.c | 32 + .../gcc.target/riscv/cv-mac-compile.c | 198 +++++ .../riscv/cv-mac-fail-compile-mac.c | 25 + .../riscv/cv-mac-fail-compile-machhsn.c | 24 + .../riscv/cv-mac-fail-compile-machhsrn.c | 24 + .../riscv/cv-mac-fail-compile-machhun.c | 24 + .../riscv/cv-mac-fail-compile-machhurn.c | 24 + .../riscv/cv-mac-fail-compile-macsn.c | 24 + .../riscv/cv-mac-fail-compile-macsrn.c | 24 + .../riscv/cv-mac-fail-compile-macun.c | 24 + .../riscv/cv-mac-fail-compile-macurn.c | 24 + .../riscv/cv-mac-fail-compile-msu.c | 25 + .../riscv/cv-mac-fail-compile-mulhhsn.c | 24 + .../riscv/cv-mac-fail-compile-mulhhsrn.c | 24 + .../riscv/cv-mac-fail-compile-mulhhun.c | 24 + .../riscv/cv-mac-fail-compile-mulhhurn.c | 24 + .../riscv/cv-mac-fail-compile-mulsn.c | 24 + .../riscv/cv-mac-fail-compile-mulsrn.c | 24 + .../riscv/cv-mac-fail-compile-mulun.c | 24 + .../riscv/cv-mac-fail-compile-mulurn.c | 24 + .../riscv/cv-mac-test-autogeneration.c | 18 + gcc/testsuite/lib/target-supports.exp | 26 + 46 files changed, 2052 insertions(+) create mode 100644 gcc/config/riscv/corev.def create mode 100644 gcc/config/riscv/corev.md create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-msu.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-test-autogeneration.c -- 2.34.1