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Tue, 3 Oct 2023 15:19:35 +0000 From: Victor Do Nascimento To: CC: , , , Victor Do Nascimento Subject: [PATCH 3/6] aarch64: Implement system register validation tools Date: Tue, 3 Oct 2023 16:18:34 +0100 Message-ID: <20231003151920.1853404-4-victor.donascimento@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231003151920.1853404-1-victor.donascimento@arm.com> References: <20231003151920.1853404-1-victor.donascimento@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT018:EE_|DU0PR08MB8322:EE_|AM7EUR03FT049:EE_|VI1PR08MB5439:EE_ X-MS-Office365-Filtering-Correlation-Id: 060af0ff-077f-41d1-24be-08dbc42432aa x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: oVfOfzXbtZAm95dFLU2ZU4fQPeyLjDxckzc/if92Bb1/+pBxv2E6I0YTyPjnURS1gR0NSl9kAYeISnZbDkMmJRQ9GK92OJsg7qrSAuURzrCi1KTA6QZ/RxGvaNInYt82aG4tNxG/OSuEY5SwuHsj1TikssQGpBLiqEYIIIy4HYK4zthYUNOHMTevRCnBlbpEWoF9gVyLsYa6suAtKvLAXL4v15Eh83VnG/dnBazR4FoyMeBspiLn2lrD93p6wSGrWlWy+njsYtahPVhUDwGfJofsPDjpmnkGXvoIUTv0mf9hWeO1/P5HM//r+p8L/m9UTLdl/B+uInueL/HekbSZzsd6xdPk7lHnuAiuY3xwiILf+M1WuSRoExqKoQOjhrdhru82/QP13V3mrT6PVNzwe7E6hMHS+QjMZLv1AFlV1t4g3X/DYPqmk10G5t0Govn7vzerIfIkRe86GQTZXj/hpOkURaEdQybgbL1RQQvZCdqvxd/yBTRDxxwCh2KJ/0Kj0aLL7lzzBcE8zR7PcONHXoY7XnOAdUG0DXZDWAycjBGXy64fTt7xrZQQpcf4VYOgwNGz2S7nOjf0n4vX8P+U2boYFi6bkqK/PzEL3tiz4GQq7v/M7XzLRpIvfDnzhh/Q7ydfd6Ir4IxRXjGBBu8h7vhmxgvF0STDFmbt3olCbvwLhhAys2xTnuCqVqPpuuSnc8oON/R0KxWekV7hvRM92jcNCYwq7ODaPYHRVC3dKBbQhIV7rCej0FU/NrjdWBDYpNM2PNgLqagCsYB21sgneQ== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(396003)(39860400002)(346002)(230922051799003)(451199024)(1800799009)(186009)(82310400011)(64100799003)(36840700001)(46966006)(40470700004)(2906002)(40460700003)(4326008)(36756003)(41300700001)(8936002)(316002)(5660300002)(40480700001)(7696005)(86362001)(1076003)(83380400001)(2616005)(36860700001)(356005)(82740400003)(426003)(70206006)(81166007)(54906003)(336012)(6916009)(47076005)(70586007)(8676002)(26005)(478600001)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Oct 2023 15:19:55.0153 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 060af0ff-077f-41d1-24be-08dbc42432aa X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT049.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB5439 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Given the implementation of a mechanism of encoding system registers into GCC, this patch provides the mechanism of validating their use by the compiler. In particular, this involves: 1. Ensuring a supplied string corresponds to a known system register name. System registers can be accessed either via their name (e.g. `SPSR_EL1') or their encoding (e.g. `S3_0_C4_C0_0'). Register names are validated using a binary search of the `sysreg_names' structure populated from the `aarch64_system_regs.def' file via `match_reg'. The encoding naming convention is validated via a parser implemented in this patch - `is_implem_def_reg'. 2. Once a given register name is deemed to be valid, it is checked against a further 2 criteria: a. Is the referenced register implemented in the target architecture? This is achieved by comparing the ARCH field in the relevant SYSREG entry from `aarch64_system_regs.def' against `aarch64_feature_flags' flags set at compile-time. b. Is the register being used correctly? Check the requested operation against the FLAGS specified in SYSREG. This prevents operations like writing to a read-only system register. NOTE: For registers specified via their encoding (e.g. `S3_0_C4_C0_0'), once the encoding value is deemed valid (as per step 1) no further checks such as read/write support or architectural feature requirements are done and this second step is skipped, as is done in gas. gcc/ChangeLog: * gcc/config/aarch64/aarch64-protos.h (aarch64_valid_sysreg_name_p): New. (aarch64_retrieve_sysreg): Likewise. * gcc/config/aarch64/aarch64.cc (match_reg): Likewise. (is_implem_def_reg): Likewise. (aarch64_valid_sysreg_name_p): Likewise. (aarch64_retrieve_sysreg): Likewise. (aarch64_sysreg_valid_for_rw_p): Likewise. * gcc/config/aarch64/predicates.md (aarch64_sysreg_string): New. --- gcc/config/aarch64/aarch64-protos.h | 2 + gcc/config/aarch64/aarch64.cc | 121 ++++++++++++++++++++++++++++ gcc/config/aarch64/predicates.md | 4 + 3 files changed, 127 insertions(+) diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 60a55f4bc19..a134e2fcf8e 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -830,6 +830,8 @@ bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool); bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *); bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *, enum simd_immediate_check w = AARCH64_CHECK_MOV); +bool aarch64_valid_sysreg_name_p (const char *); +const char *aarch64_retrieve_sysreg (char *, bool); rtx aarch64_check_zero_based_sve_index_immediate (rtx); bool aarch64_sve_index_immediate_p (rtx); bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool); diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 030b39ded1a..dd5ac1cbc8d 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -28070,6 +28070,127 @@ aarch64_pars_overlap_p (rtx par1, rtx par2) return false; } +/* Binary search of a user-supplied system register name against + a database of known register names. Upon match the index of + hit in database is returned, else return -1. */ +int +match_reg (const char *ref, const char *database[], int db_len) +{ + /* Check for named system registers. */ + int imin = 0, imax = db_len - 1, mid, cmp_res; + while (imin <= imax) + { + mid = (imin + imax) / 2; + + cmp_res = strcmp (ref, database[mid]); + if (cmp_res == 0) + return mid; + else if (cmp_res > 0) + imin = mid+1; + else + imax = mid-1; + } + return -1; +} + +/* Parse an implementation-defined system register name of + the form S[0-3]_[0-7]_C[0-15]_C[0-15]_[1-7]. + Return true if name matched against above pattern, false + otherwise. */ +bool +is_implem_def_reg (const char *regname) +{ + /* Check for implementation-defined system registers. */ + int name_len = strlen (regname); + if (name_len < 12 || name_len > 14) + return false; + + int pos = 0, i = 0, j = 0; + char n[3] = {0}, m[3] = {0}; + if (regname[pos] != 's' && regname[pos] != 'S') + return false; + pos++; + if (regname[pos] < '0' || regname[pos] > '3') + return false; + pos++; + if (regname[pos++] != '_') + return false; + if (regname[pos] < '0' || regname[pos] > '7') + return false; + pos++; + if (regname[pos++] != '_') + return false; + if (regname[pos] != 'c' && regname[pos] != 'C') + return false; + pos++; + while (regname[pos] != '_') + { + if (i > 2) + return false; + if (!ISDIGIT (regname[pos])) + return false; + n[i++] = regname[pos++]; + } + if (atoi (n) > 15) + return false; + if (regname[pos++] != '_') + return false; + if (regname[pos] != 'c' && regname[pos] != 'C') + return false; + pos++; + while (regname[pos] != '_') + { + if (j > 2) + return false; + if (!ISDIGIT (regname[pos])) + return false; + m[j++] = regname[pos++]; + } + if (atoi (m) > 15) + return false; + if (regname[pos++] != '_') + return false; + if (regname[pos] < '0' || regname[pos] > '7') + return false; + return true; +} + +/* Ensure a supplied system register name is implemented in the target + architecture. For use in back-end predicate `aarch64_sysreg_string'. */ +bool +aarch64_valid_sysreg_name_p (const char *regname) +{ + int reg_id = match_reg (regname, sysreg_names, nsysreg); + if (reg_id == -1) + return is_implem_def_reg (regname); + return (aarch64_isa_flags & sysreg_reqs[reg_id]); +} + +/* Ensure a supplied system register name is suitable for the desired use. + This involves checking its suitability for the requested read/write + operation and that it is implemented in the target architecture. + + NOTE: The read/write flags refer to whether a given register is + read/write-only. */ +const char * +aarch64_retrieve_sysreg (char *regname, bool write_p) +{ + int reg_id = match_reg (regname, sysreg_names, nsysreg); + if (reg_id == -1) + { + if (is_implem_def_reg (regname)) + return (const char *) regname; + else + return NULL; + } + if ((write_p && (sysreg_properties[reg_id] & F_REG_READ)) + || (!write_p && (sysreg_properties[reg_id] & F_REG_WRITE))) + return NULL; + if (aarch64_isa_flags & sysreg_reqs[reg_id]) + return sysreg_names_generic[reg_id]; + return NULL; +} + /* Target-specific selftests. */ #if CHECKING_P diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 01de4743974..5f0d242e4a8 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -20,6 +20,10 @@ (include "../arm/common.md") +(define_predicate "aarch64_sysreg_string" + (and (match_code "const_string") + (match_test "aarch64_valid_sysreg_name_p (XSTR (op, 0))"))) + (define_special_predicate "cc_register" (and (match_code "reg") (and (match_test "REGNO (op) == CC_REGNUM") -- 2.41.0