From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 2118B3858D3C; Thu, 5 Oct 2023 04:13:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2118B3858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0353726.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3954CZYi032343; Thu, 5 Oct 2023 04:13:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : content-transfer-encoding : mime-version; s=pp1; bh=CSh/Jf9w66H8wIa0TFUEvG6VjwZ1hMbcY+x16vI4/c4=; b=nIA7mxiZWwPtzKKLPlIt4Q9twGIiGyx9F6+9L5w8oZa4Sgn0kEX8aF1CwM7BPrtoP8T4 ma1LT5vbMsZgU1NPYHAuNCjB7qqPOFtXJCak284Lr11O95EcRVdUbLnngSvV1NrLXy6m lcbHbRSSeIOy3T1SG/niPKcfSfJ9/UpsUWMbEzblyNGfs7z0ojfkl6TpLgumc/PFEvLu mucS9B2/xPs/KffR8IHQRAi+Izg34QxyxIKLbFlPoLWOwFazXpdCWq98Z8jCgWj2JwE7 yifadlWQGqZmoJAtnM1sz6rj8WyFCLBjjhxTBqNeA4QKf9nh+h4DjaI6WGIV4lKDywSw RQ== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3thm1dtnrb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Oct 2023 04:13:56 +0000 Received: from m0353726.ppops.net (m0353726.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3954Dtg0007232; Thu, 5 Oct 2023 04:13:55 GMT Received: from ppma22.wdc07v.mail.ibm.com (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3thm1dtnpm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Oct 2023 04:13:55 +0000 Received: from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1]) by ppma22.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3952JlLI025205; Thu, 5 Oct 2023 04:13:53 GMT Received: from smtprelay07.fra02v.mail.ibm.com ([9.218.2.229]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3texcys5tr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 05 Oct 2023 04:13:53 +0000 Received: from smtpav05.fra02v.mail.ibm.com (smtpav05.fra02v.mail.ibm.com [10.20.54.104]) by smtprelay07.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3954DnKA12911236 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 5 Oct 2023 04:13:50 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D648D20043; Thu, 5 Oct 2023 04:13:49 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A431720040; Thu, 5 Oct 2023 04:13:48 +0000 (GMT) Received: from genoa.aus.stglabs.ibm.com (unknown [9.40.192.157]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 5 Oct 2023 04:13:48 +0000 (GMT) From: Jiufu Guo To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, bergner@linux.ibm.com, guojiufu@linux.ibm.com Subject: [PATCH V5 2/2] rs6000: use mtvsrws to move sf from si p9 Date: Thu, 5 Oct 2023 12:13:46 +0800 Message-Id: <20231005041346.3625108-2-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005041346.3625108-1-guojiufu@linux.ibm.com> References: <20231005041346.3625108-1-guojiufu@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: o9MiRjMbah0tKEMPYQPtjwuEkhfb2yn0 X-Proofpoint-GUID: c7i0IEI7lA2NbaM5lgnazpWUFs1ElbXH Content-Transfer-Encoding: 8bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-05_01,2023-10-02_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 phishscore=0 adultscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 mlxlogscore=955 impostorscore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2309180000 definitions=main-2310050034 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, As mentioned in PR108338, on p9, we could use mtvsrws to implement the bitcast from SI to SF (or lowpart DI to SF). For example: *(long long*)buff = di; float f = *(float*)(buff); "sldi 9,3,32 ; mtvsrd 1,9 ; xscvspdpn 1,1" is generated. A better one would be "mtvsrws 1,3 ; xscvspdpn 1,1". Compare with previous patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628791.html According to review comments, this version refines commit message and words in comments, also updates the test case Pass bootstrap and regtest on ppc64{,le}. Is this ok for trunk? BR, Jeff (Jiufu Guo) PR target/108338 gcc/ChangeLog: * config/rs6000/rs6000.md (movsf_from_si): Update to generate mtvsrws for P9. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr108338.c: Updated to check mtvsrws for p9. --- gcc/config/rs6000/rs6000.md | 25 ++++++++++++++++----- gcc/testsuite/gcc.target/powerpc/pr108338.c | 21 ++++++++++++++--- 2 files changed, 37 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 56bd8bc1147..d6dfb25cea0 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8283,13 +8283,26 @@ (define_insn_and_split "movsf_from_si" { rtx op0 = operands[0]; rtx op1 = operands[1]; - rtx op2 = operands[2]; - rtx op1_di = gen_rtx_REG (DImode, REGNO (op1)); - /* Move SF value to upper 32-bits for xscvspdpn. */ - emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); - emit_insn (gen_p8_mtvsrd_sf (op0, op2)); - emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); + /* Move lowpart 32-bits from register for SFmode. */ + if (TARGET_P9_VECTOR) + { + /* Using mtvsrws;xscvspdpn. */ + rtx op0_v = gen_rtx_REG (V4SImode, REGNO (op0)); + emit_insn (gen_vsx_splat_v4si (op0_v, op1)); + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); + } + else + { + rtx op2 = operands[2]; + rtx op1_di = gen_rtx_REG (DImode, REGNO (op1)); + + /* Using sldi;mtvsrd;xscvspdpn. */ + emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); + emit_insn (gen_p8_mtvsrd_sf (op0, op2)); + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); + } + DONE; } [(set_attr "length" diff --git a/gcc/testsuite/gcc.target/powerpc/pr108338.c b/gcc/testsuite/gcc.target/powerpc/pr108338.c index bd83c0b3ad8..5f2f62866ee 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr108338.c +++ b/gcc/testsuite/gcc.target/powerpc/pr108338.c @@ -3,9 +3,12 @@ /* { dg-options "-O2 -save-temps" } */ /* Under lp64, parameter 'v' is in DI regs, then bitcast sub DI to SF. */ -/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 1 { target { lp64 && has_arch_pwr8 } } } } */ -/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && has_arch_pwr8 } } } } */ +/* { dg-final { scan-assembler-times {\mxscvspdpn\M} 2 { target { lp64 && has_arch_pwr8 } } } } */ +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 2 { target { lp64 && { has_arch_pwr8 && { ! has_arch_pwr9 } } } } } } */ +/* { dg-final { scan-assembler-times {\mmtvsrd\M} 1 { target { lp64 && has_arch_pwr9 } } } } */ +/* { dg-final { scan-assembler-times {\mmtvsrws\M} 1 { target { lp64 && has_arch_pwr9 } } } } */ /* { dg-final { scan-assembler-times {\mrldicr\M} 1 { target { lp64 && has_arch_pwr8 } } } } */ +/* { dg-final { scan-assembler-times {\msldi\M} 1 { target { lp64 && { has_arch_pwr8 && { ! has_arch_pwr9 } } } } } } */ struct di_sf_sf { @@ -22,16 +25,28 @@ sf_from_high32bit_di (struct di_sf_sf v) #endif } +float __attribute__ ((noipa)) +sf_from_low32bit_di (struct di_sf_sf v) +{ +#ifdef __LITTLE_ENDIAN__ + return v.f1; +#else + return v.f2; +#endif +} + int main() { struct di_sf_sf v; v.f1 = v.f2 = 0.0f; #ifdef __LITTLE_ENDIAN__ + v.f1 = 1.0f; v.f2 = 2.0f; #else v.f1 = 2.0f; + v.f2 = 1.0f; #endif - if (sf_from_high32bit_di (v) != 2.0f) + if (sf_from_high32bit_di (v) != 2.0f || sf_from_low32bit_di (v) != 1.0f) __builtin_abort (); return 0; } -- 2.25.1