From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by sourceware.org (Postfix) with ESMTPS id 81CA03858C01 for ; Wed, 11 Oct 2023 12:06:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 81CA03858C01 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-406618d080eso64724905e9.2 for ; Wed, 11 Oct 2023 05:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1697026002; x=1697630802; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jdeFv3GHbTxR50WWivQVn7bdpmKMcni+YbB6QH8WH90=; b=XiIFSJTqbhNeRJ8DlGSM2dUVD1Jz5TzQHVUqU3+q6F8nXH/5VXPU/CKYskh6zqm/2M dbuAWaEyVQqEDJS79/sZyacQdBQMEKsWyyKfhTef7ykMzHvLTvQJfiYUURpC4e/su3K/ 6XVwoujbBgiuM8tF7z02zs5Gae7jGUoedRsePhlZule/biWK3Kv07R+dVbx7K4108TK3 z3rkBr2EKN6ZboquEuynQZfTIuvOTpOAifm1i09w/xiOkACFR0lWF33Hb16rptXTmXtR iqaaDYvcf4gez5FK0wMbcrM5rdMLuwz3oFlkEViz6s+CTXkIW9lk7fKAIYdHg+p2NLVO jM1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697026002; x=1697630802; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jdeFv3GHbTxR50WWivQVn7bdpmKMcni+YbB6QH8WH90=; b=c4MLz2hT9F6gqSjXli20CyLLz2HAOOZD9PXtqMzlZlvEY3d/mcHHAECF93YLYl+X9b C+zIXjVScC0WmeCKXi2lKZ0CuPOpHfz85dXo3KGqEY598H6NKWiCKwGCDEDCObyYjG2m o1aHcYTECdsXKYqoLR1BL3xRwr3/cR54OGm+/H5UcWNF6Zyh3/GxSxuaoD4g+RVzBAAl H9GOy6qZYksXPpXDPaduRMncHLZ/bqlwl9KspsF2GRo9qjW5qKffc5NVRlo5XSq9rtIK Gq9SW1jO9OA3twNlpduCLvrF2htVoorzBUEzfxgaeW6D5QOW/mucdE7KUK1pAeAsEMUm Nrqg== X-Gm-Message-State: AOJu0YwmaDU9UcyQnx1hF8ZvoePXOvW6SAj6nn8AGZfjHP4MHugPLgFQ NhM2LGtW3wSIWXoAYb5SExVWLu5FxQxNnlYGisYqCg== X-Google-Smtp-Source: AGHT+IG0P8Hp1Gv+MWaBwHK33pgogxvHR0d1QtjBTO0beEeEYSzQiRlUGq4QitBD1VZCecuXz1NDXw== X-Received: by 2002:a5d:50c8:0:b0:316:f24b:597a with SMTP id f8-20020a5d50c8000000b00316f24b597amr18179591wrt.46.1697026001608; Wed, 11 Oct 2023 05:06:41 -0700 (PDT) Received: from troughton.sou.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id c5-20020a05600c0ac500b0040586360a36sm18806248wmr.17.2023.10.11.05.06.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 05:06:40 -0700 (PDT) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v4 0/2] RISC-V: Support CORE-V XCVMAC and XCVALU extensions Date: Wed, 11 Oct 2023 13:06:06 +0100 Message-Id: <20231011120608.242927-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230930120038.3110583-1-mary.bennett@embecosm.com> References: <20230930120038.3110583-1-mary.bennett@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch series presents the comprehensive implementation of the MAC and ALU extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin RISC-V: Add support for XCValu extension in CV32E40P RISC-V: Add support for XCVmac extension in CV32E40P gcc/common/config/riscv/riscv-common.cc | 6 + gcc/config/riscv/constraints.md | 7 + gcc/config/riscv/corev.def | 43 ++ gcc/config/riscv/corev.md | 693 ++++++++++++++++++ gcc/config/riscv/predicates.md | 5 + gcc/config/riscv/riscv-builtins.cc | 13 + gcc/config/riscv/riscv-ftypes.def | 11 + gcc/config/riscv/riscv.cc | 7 + gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/riscv.opt | 7 + gcc/doc/extend.texi | 174 +++++ gcc/doc/sourcebuild.texi | 12 + .../gcc.target/riscv/cv-alu-compile.c | 252 +++++++ .../riscv/cv-alu-fail-compile-addn.c | 11 + .../riscv/cv-alu-fail-compile-addrn.c | 11 + .../riscv/cv-alu-fail-compile-addun.c | 11 + .../riscv/cv-alu-fail-compile-addurn.c | 11 + .../riscv/cv-alu-fail-compile-clip.c | 11 + .../riscv/cv-alu-fail-compile-clipu.c | 11 + .../riscv/cv-alu-fail-compile-subn.c | 11 + .../riscv/cv-alu-fail-compile-subrn.c | 11 + .../riscv/cv-alu-fail-compile-subun.c | 11 + .../riscv/cv-alu-fail-compile-suburn.c | 11 + .../gcc.target/riscv/cv-alu-fail-compile.c | 32 + .../gcc.target/riscv/cv-mac-compile.c | 198 +++++ .../riscv/cv-mac-fail-compile-mac.c | 25 + .../riscv/cv-mac-fail-compile-machhsn.c | 24 + .../riscv/cv-mac-fail-compile-machhsrn.c | 24 + .../riscv/cv-mac-fail-compile-machhun.c | 24 + .../riscv/cv-mac-fail-compile-machhurn.c | 24 + .../riscv/cv-mac-fail-compile-macsn.c | 24 + .../riscv/cv-mac-fail-compile-macsrn.c | 24 + .../riscv/cv-mac-fail-compile-macun.c | 24 + .../riscv/cv-mac-fail-compile-macurn.c | 24 + .../riscv/cv-mac-fail-compile-msu.c | 25 + .../riscv/cv-mac-fail-compile-mulhhsn.c | 24 + .../riscv/cv-mac-fail-compile-mulhhsrn.c | 24 + .../riscv/cv-mac-fail-compile-mulhhun.c | 24 + .../riscv/cv-mac-fail-compile-mulhhurn.c | 24 + .../riscv/cv-mac-fail-compile-mulsn.c | 24 + .../riscv/cv-mac-fail-compile-mulsrn.c | 24 + .../riscv/cv-mac-fail-compile-mulun.c | 24 + .../riscv/cv-mac-fail-compile-mulurn.c | 24 + .../riscv/cv-mac-test-autogeneration.c | 18 + gcc/testsuite/lib/target-supports.exp | 26 + 45 files changed, 2049 insertions(+) create mode 100644 gcc/config/riscv/corev.def create mode 100644 gcc/config/riscv/corev.md create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-addurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clip.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-clipu.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-subun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile-suburn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-alu-fail-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-compile.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mac.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-machhurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-macurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-msu.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulhhurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulsrn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulun.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-fail-compile-mulurn.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mac-test-autogeneration.c -- 2.34.1