From: Lehua Ding <lehua.ding@rivai.ai>
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com,
palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai
Subject: [PATCH V3 05/11] RISC-V: P5: Combine phase 1 and 2
Date: Thu, 19 Oct 2023 16:33:27 +0800 [thread overview]
Message-ID: <20231019083333.2052340-6-lehua.ding@rivai.ai> (raw)
In-Reply-To: <20231019083333.2052340-1-lehua.ding@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info): New.
(pass_vsetvl::compute_local_backward_infos): Removed.
(pass_vsetvl::need_vsetvl): Removed.
(pass_vsetvl::transfer_before): Removed.
(pass_vsetvl::transfer_after): Removed.
(pass_vsetvl::emit_local_forward_vsetvls): Removed.
---
gcc/config/riscv/riscv-vsetvl.cc | 270 ++++++++++++++-----------------
1 file changed, 124 insertions(+), 146 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index f8b708c248a..dad3d7c941e 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2722,6 +2722,130 @@ public:
};
+void
+pre_vsetvl::fuse_local_vsetvl_info ()
+{
+ m_reg_def_loc
+ = sbitmap_vector_alloc (last_basic_block_for_fn (cfun), GP_REG_LAST + 1);
+ bitmap_vector_clear (m_reg_def_loc, last_basic_block_for_fn (cfun));
+ bitmap_ones (m_reg_def_loc[ENTRY_BLOCK_PTR_FOR_FN (cfun)->index]);
+
+ for (bb_info *bb : crtl->ssa->bbs ())
+ {
+ auto &block_info = get_block_info (bb);
+ block_info.m_bb = bb;
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ {
+ fprintf (dump_file, " Try fuse basic block %d\n", bb->index ());
+ }
+ auto_vec<vsetvl_info> infos;
+ for (insn_info *insn : bb->real_nondebug_insns ())
+ {
+ vsetvl_info curr_info = vsetvl_info (insn);
+ if (curr_info.valid_p () || curr_info.unknown_p ())
+ infos.safe_push (curr_info);
+
+ /* Collecting GP registers modified by the current bb. */
+ if (insn->is_real ())
+ for (def_info *def : insn->defs ())
+ if (def->is_reg () && GP_REG_P (def->regno ()))
+ bitmap_set_bit (m_reg_def_loc[bb->index ()], def->regno ());
+ }
+
+ vsetvl_info prev_info = vsetvl_info ();
+ prev_info.set_empty ();
+ for (auto &curr_info : infos)
+ {
+ if (prev_info.empty_p ())
+ prev_info = curr_info;
+ else if ((curr_info.unknown_p () && prev_info.valid_p ())
+ || (curr_info.valid_p () && prev_info.unknown_p ()))
+ {
+ block_info.infos.safe_push (prev_info);
+ prev_info = curr_info;
+ }
+ else if (curr_info.valid_p () && prev_info.valid_p ())
+ {
+ if (m_dem.available_p (prev_info, curr_info))
+ {
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ {
+ fprintf (dump_file,
+ " Ignore curr info since prev info "
+ "available with it:\n");
+ fprintf (dump_file, " prev_info: ");
+ prev_info.dump (dump_file, " ");
+ fprintf (dump_file, " curr_info: ");
+ curr_info.dump (dump_file, " ");
+ fprintf (dump_file, "\n");
+ }
+ if (!curr_info.vl_use_by_non_rvv_insn_p ()
+ && vsetvl_insn_p (curr_info.get_insn ()->rtl ()))
+ m_delete_list.safe_push (curr_info);
+
+ if (curr_info.get_read_vl_insn ())
+ prev_info.set_read_vl_insn (curr_info.get_read_vl_insn ());
+ }
+ else if (m_dem.compatible_p (prev_info, curr_info))
+ {
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ {
+ fprintf (dump_file, " Fuse curr info since prev info "
+ "compatible with it:\n");
+ fprintf (dump_file, " prev_info: ");
+ prev_info.dump (dump_file, " ");
+ fprintf (dump_file, " curr_info: ");
+ curr_info.dump (dump_file, " ");
+ }
+ m_dem.merge (prev_info, curr_info);
+ if (curr_info.get_read_vl_insn ())
+ prev_info.set_read_vl_insn (curr_info.get_read_vl_insn ());
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ {
+ fprintf (dump_file, " prev_info after fused: ");
+ prev_info.dump (dump_file, " ");
+ fprintf (dump_file, "\n");
+ }
+ }
+ else
+ {
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ {
+ fprintf (dump_file,
+ " Cannot fuse uncompatible infos:\n");
+ fprintf (dump_file, " prev_info: ");
+ prev_info.dump (dump_file, " ");
+ fprintf (dump_file, " curr_info: ");
+ curr_info.dump (dump_file, " ");
+ }
+ block_info.infos.safe_push (prev_info);
+ prev_info = curr_info;
+ }
+ }
+ }
+
+ if (prev_info.valid_p () || prev_info.unknown_p ())
+ block_info.infos.safe_push (prev_info);
+ }
+
+ m_avl_regs = sbitmap_alloc (GP_REG_LAST + 1);
+ bitmap_clear (m_avl_regs);
+ for (const bb_info *bb : crtl->ssa->bbs ())
+ {
+ vsetvl_block_info &block_info = get_block_info (bb);
+ if (block_info.empty_p ())
+ continue;
+
+ vsetvl_info &header_info = block_info.get_entry_info ();
+ if (header_info.valid_p () && header_info.has_nonvlmax_reg_avl ())
+ {
+ gcc_assert (GP_REG_P (REGNO (header_info.get_avl ())));
+ bitmap_set_bit (m_avl_regs, REGNO (header_info.get_avl ()));
+ }
+ }
+}
+
+
const pass_data pass_data_vsetvl = {
RTL_PASS, /* type */
"vsetvl", /* name */
@@ -2860,152 +2984,6 @@ make_pass_vsetvl (gcc::context *ctxt)
return new pass_vsetvl (ctxt);
}
-/* Compute demanded information by backward data-flow analysis. */
-void
-pass_vsetvl::compute_local_backward_infos (const bb_info *bb)
-{
- vector_insn_info change;
- change.set_empty ();
-
- auto &block_info = m_vector_manager->vector_block_infos[bb->index ()];
- block_info.reaching_out = change;
-
- for (insn_info *insn : bb->reverse_real_nondebug_insns ())
- {
- auto &info = get_vector_info (insn);
-
- if (info.uninit_p ())
- /* If it is uninitialized, propagate it directly. */
- update_vector_info (insn, change);
- else if (info.unknown_p ())
- change = info;
- else
- {
- gcc_assert (info.valid_p () && "Unexpected Invalid demanded info");
- if (change.valid_p ())
- {
- if (!(propagate_avl_across_demands_p (change, info)
- && !reg_available_p (insn, change))
- && change.compatible_p (info))
- {
- update_vector_info (insn, change.local_merge (info));
- /* Fix PR109399, we should update user vsetvl instruction
- if there is a change in demand fusion. */
- if (vsetvl_insn_p (insn->rtl ()))
- change_vsetvl_insn (insn, info);
- }
- }
- change = info;
- }
- }
-
- block_info.local_dem = change;
- if (block_info.local_dem.empty_p ())
- block_info.reaching_out = block_info.local_dem;
-}
-
-/* Return true if a dem_info is required to transition from curr_info to
- require before INSN. */
-bool
-pass_vsetvl::need_vsetvl (const vector_insn_info &require,
- const vector_insn_info &curr_info) const
-{
- if (!curr_info.valid_p () || curr_info.unknown_p () || curr_info.uninit_p ())
- return true;
-
- if (require.compatible_p (static_cast<const vl_vtype_info &> (curr_info)))
- return false;
-
- return true;
-}
-
-/* Given an incoming state reaching INSN, modifies that state so that it is
- minimally compatible with INSN. The resulting state is guaranteed to be
- semantically legal for INSN, but may not be the state requested by INSN. */
-void
-pass_vsetvl::transfer_before (vector_insn_info &info, insn_info *insn) const
-{
- if (!has_vtype_op (insn->rtl ()))
- return;
-
- const vector_insn_info require = get_vector_info (insn);
- if (info.valid_p () && !need_vsetvl (require, info))
- return;
- info = require;
-}
-
-/* Given a state with which we evaluated insn (see transfer_before above for why
- this might be different that the state insn requested), modify the state to
- reflect the changes insn might make. */
-void
-pass_vsetvl::transfer_after (vector_insn_info &info, insn_info *insn) const
-{
- if (vector_config_insn_p (insn->rtl ()))
- {
- info = get_vector_info (insn);
- return;
- }
-
- if (fault_first_load_p (insn->rtl ())
- && info.update_fault_first_load_avl (insn))
- return;
-
- /* If this is something that updates VL/VTYPE that we don't know about, set
- the state to unknown. */
- if (insn->is_call () || insn->is_asm ()
- || find_access (insn->defs (), VL_REGNUM)
- || find_access (insn->defs (), VTYPE_REGNUM))
- info = vector_insn_info::get_unknown ();
-}
-
-/* Emit vsetvl within each block by forward data-flow analysis. */
-void
-pass_vsetvl::emit_local_forward_vsetvls (const bb_info *bb)
-{
- auto &block_info = m_vector_manager->vector_block_infos[bb->index ()];
- if (block_info.local_dem.empty_p ())
- return;
-
- vector_insn_info curr_info;
- for (insn_info *insn : bb->real_nondebug_insns ())
- {
- const vector_insn_info prev_info = curr_info;
- enum vsetvl_type type = NUM_VSETVL_TYPE;
- transfer_before (curr_info, insn);
-
- if (has_vtype_op (insn->rtl ()))
- {
- if (static_cast<const vl_vtype_info &> (prev_info)
- != static_cast<const vl_vtype_info &> (curr_info))
- {
- const auto require = get_vector_info (insn);
- if (!require.compatible_p (
- static_cast<const vl_vtype_info &> (prev_info)))
- type = insert_vsetvl (EMIT_BEFORE, insn->rtl (), require,
- prev_info);
- }
- }
-
- /* Fix the issue of following sequence:
- vsetivli zero, 5
- ....
- vsetvli zero, zero
- vmv.x.s (demand AVL = 8).
- ....
- incorrect: vsetvli zero, zero ===> Since the curr_info is AVL = 8.
- correct: vsetivli zero, 8
- vadd (demand AVL = 8). */
- if (type == VSETVL_VTYPE_CHANGE_ONLY)
- {
- /* Update the curr_info to be real correct AVL. */
- curr_info.set_avl_info (prev_info.get_avl_info ());
- }
- transfer_after (curr_info, insn);
- }
-
- block_info.reaching_out = curr_info;
-}
-
/* Assemble the candidates expressions for LCM. */
void
pass_vsetvl::prune_expressions (void)
--
2.36.3
next prev parent reply other threads:[~2023-10-19 8:33 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-19 8:33 [PATCH V3 00/11] Refactor and cleanup vsetvl pass Lehua Ding
2023-10-19 8:33 ` [PATCH V3 01/11] RISC-V: P1: Refactor avl_info/vl_vtype_info/vector_insn_info/vector_block_info Lehua Ding
2023-10-19 8:33 ` [PATCH V3 02/11] RISC-V: P2: Refactor and cleanup demand system Lehua Ding
2023-10-19 8:33 ` [PATCH V3 03/11] RISC-V: P3: Refactor vector_infos_manager Lehua Ding
2023-10-19 8:33 ` [PATCH V3 04/11] RISC-V: P4: move method from pass_vsetvl to pre_vsetvl Lehua Ding
2023-10-19 8:33 ` Lehua Ding [this message]
2023-10-19 8:33 ` [PATCH V3 06/11] RISC-V: P6: Add computing reaching definition data flow Lehua Ding
2023-10-19 8:33 ` [PATCH V3 07/11] RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class Lehua Ding
2023-10-19 8:33 ` [PATCH V3 08/11] RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization Lehua Ding
2023-10-19 8:33 ` [PATCH V3 09/11] RISC-V: P9: Cleanup and reorganize helper functions Lehua Ding
2023-10-19 8:33 ` [PATCH V3 10/11] RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def Lehua Ding
2023-10-19 8:33 ` [PATCH V3 11/11] RISC-V: P11: Adjust and add testcases Lehua Ding
2023-10-19 8:38 ` [PATCH V3 00/11] Refactor and cleanup vsetvl pass Robin Dapp
2023-10-19 8:43 ` Lehua Ding
2023-10-19 8:50 ` 钟居哲
2023-10-19 18:04 ` Patrick O'Neill
2023-10-20 2:20 ` Lehua Ding
2023-10-20 3:58 ` Lehua Ding
2023-10-23 18:30 ` Patrick O'Neill
2023-10-23 21:41 ` 钟居哲
2023-10-23 22:46 ` Patrick O'Neill
2023-10-23 22:50 ` 钟居哲
2023-10-23 23:42 ` Patrick O'Neill
2023-10-24 0:51 ` juzhe.zhong
2023-10-24 1:01 ` Patrick O'Neill
2023-10-24 2:27 ` juzhe.zhong
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