From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by sourceware.org (Postfix) with ESMTPS id 046A03858D37 for ; Sun, 22 Oct 2023 22:32:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 046A03858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 046A03858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::42d ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698013931; cv=none; b=bppETAYuy+rxPUO5bLNVQ9Nf8QMXVlHFClG+osQh7dNtla3fMQ/ujY+hAraz9YgnD7pHZeWsi8wokpn5HXOPuMJ8OgiCPokmHhHL3LSz8Pw6l+TIHQd+YvQJGNG5pYgbDXN1PcfuDyAmvKjCzQLtggckplAOYSSeCySF5Q6s19Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698013931; c=relaxed/simple; bh=bar4tVhZIY9fB6/vOUrNgPq4HqOZPXUlqtvIyKiwi8M=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=jB/3pCgm3Hs/mevDxF19GFgvv1O7OcFVapwQuYhAFL/xVEUC1YlPkibOSSPH18TbxVC7x5+XVNPSMJT9zVnzyN2W/G1c4jX5bJHk+70tTRU3GR4G4KZKrEDpTj6indHsh+AvmBDYzNXNr/1u9zyNs5iZSFrccZaGuXy0OpJCpmQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-6b2018a11efso2623816b3a.0 for ; Sun, 22 Oct 2023 15:32:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1698013929; x=1698618729; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=gd62ACv5tQvrl5Pk5NMeivESW0NOAVehp0w/OkYfzoM=; b=TuMb4rqt7xuzMHk/MTjmF1EfDo1ob/E18wz9dXMXS/6ynHRVpzdLZk+o707lBOlns5 hIErDOXP5eDp7s67dhC98ntHMZBVrci1XrxldCwAFrBmBszLnUpF62dXeqdDvnTWrC4t A8Jo/JVUkWk5IZGE8W/+FaDa1RhmpYFQrYFiqNZ+4z6dYPVIeTXlQ1FBSPOaYr+7HAtx 5UUkGLt9ujISQr4C5Wfyns7ehAUpSyuSw8sHCd4I+JG3e4V1dTRuO5bGuXtRxma+aknG X8q5p2Bw/ViXZUY6+EmDvaJ1v2PiLEv/PvRAiU8lxBv5Hk4T5LDOcqJgi4y1m/3ky8eJ Nubg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698013929; x=1698618729; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=gd62ACv5tQvrl5Pk5NMeivESW0NOAVehp0w/OkYfzoM=; b=Vr0rHolxlz6mZiDJuDJeB0aHXIpxYWvtCmrZSZUnDhm1PpGhDrFihRfmZM0KxJve+q 4/vUtum2LDBKFvtKs6+2hWfMTiwzUj3KV0/WZqSnF4ruKtoFts4rF2xzwEFKDHLrBIAs 1IbV72QXwCdTR7dEy34w3bY7OWU5D4O8QlpzQaECfbdoHpzeiT8qHywCGajOUsPPHphE 5pbGX3lsCikq88ZEbPHMnQRIsOXwe0CN5koYZMgmL9rM3tuZ01gnp4QjT+04dIK+dL2q G8HMQp9Evns1r2XaEXmC49JRk4fwx+J0p8gT2fvYIWboIUbvqGY2zODULpmPn/YBdI2D 7QNg== X-Gm-Message-State: AOJu0YyoAocATu2h601TxJCFksag5FjlqZtl2pfUZAKXVnVN/PJ9MYoJ Wgvq3DtrdQNgWh2I4wgsoJI7RthMUkVjDA== X-Google-Smtp-Source: AGHT+IHgFZr0eE6z9H/iVRhE0OoE40Ea+3WIzM3QHltpXvqC26vVh5VjCyWZ61bCkLvAogeEQMID1Q== X-Received: by 2002:a05:6a20:7293:b0:15e:7323:5c0f with SMTP id o19-20020a056a20729300b0015e73235c0fmr8378772pzk.16.1698013928593; Sun, 22 Oct 2023 15:32:08 -0700 (PDT) Received: from xeond2.wrightpinski.org ([98.97.114.173]) by smtp.gmail.com with ESMTPSA id r25-20020aa79639000000b00694f14a784bsm4959548pfg.52.2023.10.22.15.32.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Oct 2023 15:32:08 -0700 (PDT) From: Andrew Pinski To: gcc-patches@gcc.gnu.org Cc: Andrew Pinski Subject: [Committedv2] aarch64: [PR110986] Emit csinv again for `a ? ~b : b` Date: Sun, 22 Oct 2023 15:32:05 -0700 Message-Id: <20231022223205.1646902-1-pinskia@gmail.com> X-Mailer: git-send-email 2.39.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: After r14-3110-g7fb65f10285, the canonical form for `a ? ~b : b` changed to be `-(a) ^ b` that means for aarch64 we need to add a few new insn patterns to be able to catch this and change it to be what is the canonical form for the aarch64 backend. A secondary pattern was needed to support a zero_extended form too; this adds a testcase for all 3 cases. Bootstrapped and tested on aarch64-linux-gnu with no regressions. Committed as approved. PR target/110986 gcc/ChangeLog: * config/aarch64/aarch64.md (*cmov_insn_insv): New pattern. (*cmov_uxtw_insn_insv): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/cond_op-1.c: New test. --- gcc/config/aarch64/aarch64.md | 47 ++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/cond_op-1.c | 20 +++++++++ 2 files changed, 67 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/cond_op-1.c diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index e6af09c2e8b..5bb8c772be8 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4413,6 +4413,53 @@ (define_insn "*csinv3_uxtw_insn3" [(set_attr "type" "csel")] ) +;; There are two canonical forms for `cmp ? ~a : a`. +;; This is the second form and is here to help combine. +;; Support `-(cmp) ^ a` into `cmp ? ~a : a` +;; The second pattern is to support the zero extend'ed version. + +(define_insn_and_split "*cmov_insn_insv" + [(set (match_operand:GPI 0 "register_operand" "=r") + (xor:GPI + (neg:GPI + (match_operator:GPI 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)])) + (match_operand:GPI 3 "general_operand" "r")))] + "" + "#" + "&& true" + [(set (match_dup 0) + (if_then_else:GPI (match_dup 1) + (not:GPI (match_dup 3)) + (match_dup 3)))] + { + /* After reload this will be a nop due to the constraint. */ + operands[3] = force_reg (mode, operands[3]); + } + [(set_attr "type" "csel")] +) + +(define_insn_and_split "*cmov_uxtw_insn_insv" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (xor:SI + (neg:SI + (match_operator:SI 1 "aarch64_comparison_operator" + [(match_operand 2 "cc_register" "") (const_int 0)])) + (match_operand:SI 3 "general_operand" "r"))))] + "can_create_pseudo_p ()" + "#" + "&& true" + [(set (match_dup 0) + (if_then_else:DI (match_dup 1) + (zero_extend:DI (not:SI (match_dup 3))) + (zero_extend:DI (match_dup 3))))] + { + operands[3] = force_reg (SImode, operands[3]); + } + [(set_attr "type" "csel")] +) + ;; If X can be loaded by a single CNT[BHWD] instruction, ;; ;; A = UMAX (B, X) diff --git a/gcc/testsuite/gcc.target/aarch64/cond_op-1.c b/gcc/testsuite/gcc.target/aarch64/cond_op-1.c new file mode 100644 index 00000000000..e6c7821127e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cond_op-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +/* PR target/110986 */ + + +long long full(unsigned a, unsigned b) +{ + return a ? ~b : b; +} +unsigned fuu(unsigned a, unsigned b) +{ + return a ? ~b : b; +} +long long fllll(unsigned long long a, unsigned long long b) +{ + return a ? ~b : b; +} + +/* { dg-final { scan-assembler-times "csinv\tw\[0-9\]*" 2 } } */ +/* { dg-final { scan-assembler-times "csinv\tx\[0-9\]*" 1 } } */ -- 2.39.3