From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [52.237.72.81]) by sourceware.org (Postfix) with ESMTP id 266623858D1E for ; Mon, 30 Oct 2023 07:25:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 266623858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 266623858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=52.237.72.81 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698650755; cv=none; b=HxLd3vKqP8D6PR2T5QVjTxHzV57RPJqQfyX6TYv23D8jCN31iVxak5P+Cf1CRlLSlwXNYnIQ66rqKxJsV0lPdNElGjqrGbOvkrcmmy9Na0GYMs+5BhfNMNKKARETe898XufLiwFLF/fllEMCiA7k9shB851T2zFDB+XnAfMnFb4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698650755; c=relaxed/simple; bh=rkLa/CO3US5kaTXhgEqGzr+EDSTF0SkC750lY6m90z4=; h=From:To:Subject:Date:Message-Id; b=XEh3JjSd0lwvC6ZNxqjtvR4izSgxbJUW3ePiZol4GsLoC4ulTLebv/lcXXVU2IM6upQ7D0WWnAAQWoFgHongN50a0K7Tk1/Bi1tI8oM3Dy0PETSA7HgslEpEPtB8klVJyNE2WSG6EvUY6/9IJNhW2A0mlBZJDZXYs53mKsJWTSA= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id TAJkCgBHukZwWj9lI2cBAA--.13279S4; Mon, 30 Oct 2023 15:25:37 +0800 (CST) From: Fei Gao To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Fei Gao Subject: [PATCH 0/4] add support for conditional zero operation Date: Mon, 30 Oct 2023 07:25:19 +0000 Message-Id: <20231030072523.26818-1-gaofei@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID:TAJkCgBHukZwWj9lI2cBAA--.13279S4 X-Coremail-Antispam: 1UD129KBjvJXoW7ur1xWw17uw43CF1xAr15twb_yoW8GrW7pF yakrW3ZF1DJrZ3Aa1fJF48Ja1fuFn2g3y2yw1xG34jyr17trWkZFWUK3Za9r43Jr1ktr1j 9FWj9ry3uF4qyF7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: xjdrwv3l6h245lqf0zpsxwx03jof0z/ X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: RISC-V defines Zicond extentsion: czero.eqz rd, rs1, rs2: moves zero to a register rd, if the condition rs2 is equal to zero, otherwise moves rs1 to rd. czero.nez rd, rs1, rs2: moves zero to a register rd, if the condition rs2 is nonzero, otherwise moves rs1 to rd. With this series, the following optimizations can be achieved. opcode=[add, sub, or, xor] case: Conditional op, if zero rd = (rc == 0) ? (rs1 op rs2) : rs1 --> czero.nez rd, rs2, rc opcode rd, rs1, rd Conditional op, if non-zero rd = (rc != 0) ? (rs1 op rs2) : rs1 --> czero.eqz rd, rs2, rc opcode rd, rs1, rd case for and: Conditional and, if zero rd = (rc == 0) ? (rs1 & rs2) : rs1 --> and rd, rs1, rs2 czero.eqz rtmp, rs1, rc or rd, rd, rtmp Conditional and, if non-zero rd = (rc != 0) ? (rs1 & rs2) : rs1 --> and rd, rs1, rs2 czero.nez rtmp, rs1, rc or rd, rd, rtmp Fei Gao (4): [RISC-V]add hook to control Zicond based ifcvt opt [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns [ifcvt] if convert x=c ? y op z : y by RISC-V Zicond like insns [ifcvt] if convert x=c ? y&z : y by RISC-V Zicond like insns gcc/config/riscv/riscv.cc | 10 + gcc/doc/tm.texi | 4 + gcc/doc/tm.texi.in | 2 + gcc/ifcvt.cc | 149 ++++ gcc/target.def | 7 + .../gcc.target/riscv/zicond_ifcvt_opt.c | 642 ++++++++++++++++++ 6 files changed, 814 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c -- 2.17.1