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bh=/R7imQoUYGRhqh/FnfJ/fWX67HpgYzBABrv9hup62BQ=; h=From:To:Subject:Date:Message-Id; b=FDnjM4TciywlDVBrgMhcsh8O2gPEEbGCrf1vYPjnp7YN6EfJJZBha+e1yMWp0tm19gpglns3XRqLzkC0xvuYQLzC+iER7B2NNv0UcHU6HLrwxKjTEcvaQns264H5T9VgrgwUGyYZWbHaIT1Mz2vvpk+rskyt4e6sA2tMnC07xWY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgCnZEKa8UFlJa4BAA--.18145S4; Wed, 01 Nov 2023 14:35:07 +0800 (CST) From: Li Xu To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, juzhe.zhong@rivai.ai, xuli Subject: [PATCH] RISC-V: Support vundefine intrinsics for tuple types Date: Wed, 1 Nov 2023 06:35:19 +0000 Message-Id: <20231101063519.33245-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID:TQJkCgCnZEKa8UFlJa4BAA--.18145S4 X-Coremail-Antispam: 1UD129KBjvJXoW3Wr1rWry8tr1furyktFyrZwb_yoW7Gw13pa 98JrW2vry8XFZxWwn3KFW8Wr43Ar4xGa15Ary5Zws8Ca17Wws2y3Wqgw4ftF4DuFsY9w12 9ay5Ca15ua45ArJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: xuli https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/288 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (vundefined): Add vundefine intrinsics for tuple types. * config/riscv/riscv-vector-builtins.cc: Ditto. * config/riscv/vector.md (@vundefined): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/tuple_vundefined.c: New test. --- .../riscv/riscv-vector-builtins-functions.def | 1 + gcc/config/riscv/riscv-vector-builtins.cc | 8 ++ gcc/config/riscv/vector.md | 7 ++ .../riscv/rvv/base/tuple_vundefined.c | 73 +++++++++++++++++++ 4 files changed, 89 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 18ed2c2b8f6..911fd520195 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -622,6 +622,7 @@ DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_lmul4_x2_ops) DEF_RVV_FUNCTION (vset, vset, none_preds, all_v_vset_tuple_ops) DEF_RVV_FUNCTION (vget, vget, none_preds, all_v_vget_tuple_ops) DEF_RVV_FUNCTION (vcreate, vcreate, none_preds, all_v_vcreate_tuple_ops) +DEF_RVV_FUNCTION (vundefined, vundefined, none_preds, all_none_void_tuple_ops) DEF_RVV_FUNCTION (vlseg, seg_loadstore, full_preds, tuple_v_scalar_const_ptr_ops) DEF_RVV_FUNCTION (vsseg, seg_loadstore, none_m_preds, tuple_v_scalar_ptr_ops) DEF_RVV_FUNCTION (vlsseg, seg_loadstore, full_preds, tuple_v_scalar_const_ptr_ptrdiff_ops) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 5d4dc264fa6..2e33bf73549 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -2509,6 +2509,14 @@ static CONSTEXPR const rvv_op_info all_v_vcreate_tuple_ops rvv_arg_type_info (RVV_BASE_vector), /* Return type */ tuple_vcreate_args /* Args */}; +/* A static operand information for vector_type func () function registration. + */ +static CONSTEXPR const rvv_op_info all_none_void_tuple_ops + = {tuple_ops, /* Types */ + OP_TYPE_none, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + void_args /* Args */}; + /* A list of all RVV base function types. */ static CONSTEXPR const function_type_info function_types[] = { #define DEF_RVV_TYPE_INDEX( \ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0297e4f0227..35bb6c3dc58 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -880,6 +880,13 @@ "" [(set_attr "type" "vector")]) +(define_insn "@vundefined" + [(set (match_operand:VT 0 "register_operand" "=vr") + (unspec:VT [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))] + "TARGET_VECTOR" + "" + [(set_attr "type" "vector")]) + (define_expand "@vreinterpret" [(set (match_operand:V 0 "register_operand") (match_operand 1 "vector_any_register_operand"))] diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c new file mode 100644 index 00000000000..174860de559 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c @@ -0,0 +1,73 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat16mf4x2_t +test_vundefined_f16mf4x2 () +{ + return __riscv_vundefined_f16mf4x2 (); +} + +vfloat32m1x3_t +test_vundefined_f32m1x3 () +{ + return __riscv_vundefined_f32m1x3 (); +} + +vfloat64m1x5_t +test_vundefined_f64m1x5 () +{ + return __riscv_vundefined_f64m1x5 (); +} + +vint8mf4x2_t +test_vundefined_i8mf4x2 () +{ + return __riscv_vundefined_i8mf4x2 (); +} + +vint16mf4x8_t +test_vundefined_i16mf4x8 () +{ + return __riscv_vundefined_i16mf4x8 (); +} + +vint32m1x7_t +test_vundefined_i32m1x7 () +{ + return __riscv_vundefined_i32m1x7 (); +} + +vint64m1x4_t +test_vundefined_i64m1x4 () +{ + return __riscv_vundefined_i64m1x4 (); +} + +vuint8mf8x2_t +test_vundefined_u8mf8x2 () +{ + return __riscv_vundefined_u8mf8x2 (); +} + +vuint16mf4x4_t +test_vundefined_u16mf4x4 () +{ + return __riscv_vundefined_u16mf4x4 (); +} + +vuint32m1x7_t +test_vundefined_u32m1x7 () +{ + return __riscv_vundefined_u32m1x7 (); +} + +vuint64m4x2_t +test_vundefined_u64m4x2 () +{ + return __riscv_vundefined_u64m4x2 (); +} + +/* { dg-final { scan-assembler-times {vse[0-9]+\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 18 } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 28 } } */ -- 2.17.1