From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2077.outbound.protection.outlook.com [40.107.7.77]) by sourceware.org (Postfix) with ESMTPS id 8A38D3858C00 for ; Thu, 2 Nov 2023 16:39:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8A38D3858C00 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8A38D3858C00 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.7.77 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1698943166; cv=pass; b=dMTQhtXGRgaFxhja0UkgJWcR86zwioTZPqcPV9nNozq6w8jJd05kBTn+v1ZA559gk50o9lexXZ96vuZ/34hvwwTWNjcOx2HoOUWtJIPSovqbLNblTz+w0X/ciuQ46gcKvRi3ySdmeLaoZtZ0GrmH5lrCotaV2yGGG1FgdW8l7tk= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1698943166; c=relaxed/simple; bh=9kODRG/eFEN0bAFBG9L++pHz0EHHnHF5J+4D32yNzpw=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID: MIME-Version; b=TDjglBRmhiiHU6P1DDt5A5oN6RpNLp+D2xYV+gt/gayNTaQ/zY9cdJwEnppvFv2TBBlx9zerp5CBFjg93eSMjST2DSahMea3PY3CNNlFAnw+d2vR9JDJ2XagnvVCEcX8p0rI9AEA7rwSmFAOE6Qj12JEp4KnXtysl24dZD9kJr4= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=Ld5qkP32hEyIOoeG6FRhQPMnIFmCvpN4gr6hdusr1K0e57kTr+2j756KVrZHhykO/E5BfX4w3PsNDuguIXJZ27i95H6f9tSrYnUMbXrEKLMK9j6A6cISZN/Qxp2zsc4wQTDDEj8PO/eJp5UAzzePWMTJqF3+VuTwJy+wa5nxX0LV/6AP3EuKUy/QIKodDHtw2prGwbciKTCtmjPr1EyK4LCYnQRuKWCBnLLPJfzH2LUex28oCfDyxa+Bs1fh/mRQReuZBp2NecKxlPiHVojl0ORdBbOiJgor9IFWJzXO+kNqNVHUvNVpV7SCV8GKZaLBJQT1B63PxQBjHnonu3pruA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IWbr9YN1PU5l8Xww497zoUuM/l/KNtJh8KG/M8Cc8KU=; b=QLNpMq6KvDHNDUnAgCwsO/Aod6FpEXRxCygYtOkrUiEDhQcLyGcS4Zx8vign/6+fXH1EDS7xTAypU7V7nNiHUwCxNVNIghO/x/QbvUv6hkYGmpMjqcD6+pEEeC8kCBHrjLc6Z1oB5BtOLP8Iu+wWipYeOnpqOZaLHhO1BbPT2+x2IydZHLmRPeZaFgIQI++cXFqBpMO3ko8JKyhtH7QUqTs4ww9PKlI0mTKKoq61Dr6ZyIQ5wH6kblLaCHcR7jpK9sO599F3ddwDYZIC5P1DaIWc9lIsjuDFVl38FKilY7NMnFDJ+jM3kznp5ZBgVQQo6bbBZ4Dlz44eclIswjEJrg== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IWbr9YN1PU5l8Xww497zoUuM/l/KNtJh8KG/M8Cc8KU=; b=oF7nRm3W0O0gYBUTGBKP0nVHh68GemPzikqOfWLz5Ohe+snphy8jNmcai0f+y03Baj0Pr3crhZx/ruSZtTfaFagki8mioPux995ulvT5p5FmyVamehxUbNqeLdw4amFHyS7v0bqSmhh8b8iJxdPZhLUiAeSDGXGmQHC2DELhCAs= Received: from DU6P191CA0051.EURP191.PROD.OUTLOOK.COM (2603:10a6:10:53e::7) by PAXPR08MB6573.eurprd08.prod.outlook.com (2603:10a6:102:dc::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.21; Thu, 2 Nov 2023 16:39:17 +0000 Received: from DU6PEPF0000B61F.eurprd02.prod.outlook.com (2603:10a6:10:53e:cafe::bf) by DU6P191CA0051.outlook.office365.com (2603:10a6:10:53e::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.21 via Frontend Transport; Thu, 2 Nov 2023 16:39:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DU6PEPF0000B61F.mail.protection.outlook.com (10.167.8.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.19 via Frontend Transport; Thu, 2 Nov 2023 16:39:17 +0000 Received: ("Tessian outbound e243565b0037:v228"); Thu, 02 Nov 2023 16:39:16 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: e9f7c00aeee8011d X-CR-MTA-TID: 64aa7808 Received: from d3512255a22f.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 8CF716AE-3F64-492F-A5F7-977D44D5CFAB.1; Thu, 02 Nov 2023 16:39:10 +0000 Received: from EUR05-AM6-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id d3512255a22f.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 02 Nov 2023 16:39:10 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=MDVV4ckJxRfe+/vKv5KP6g69WqBv6LajuD0tnmxTMtqeCTn0kuITJC4pPyjKVzDY3NKmqsAMGEkkMrhTVe8B7YmU+1Am1GbsZMfRd3DAd+fOak5dMZ9s5c3la5E6GfJKKDFZmDbChYLTzetOChVeXkq6JRx9PEKCsnsdPSQijwnLXZKZfbFYef5RDw9xXGWfrJailM2PG6wnnhuKWyBQwboSbuQbPcV2bk3xSW7vZel5YyvHuxFHz+GxLdA0jdozFL0Y/so7tqSuXMfUrmdvK06nyJo/lWrZp+4QdrszTwMHs6ODNIYjpaPOQidwj+z0ZZTtg86agXO5B8oLUUTvag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IWbr9YN1PU5l8Xww497zoUuM/l/KNtJh8KG/M8Cc8KU=; b=ASVjhd1wDCHSFlt+a3LcGWC5ndz36zf+1BRJOeNPJj0gzp+huo0q+R4F2YckSeJe3AgZ4hGs/EMFNsCOrgaDJiAfNoHUgRSXNJjvev2e6GLpR7nk64EpJ4AKnflqj4njcVv2imTnzlLghKveYxE6/9ALvRRHaNTFMJe3e78fTgv0W8eNEUM4RMbmh59DitL1qQVqay9RpmaSoGs2WQiPPD9//BrISKKGPiV3qzkuerBdYTv95DW0HIqYHnNSQU1+IpYkZZEaVIgIc78PnMOK6o/IUCwdAnDaEu33KZNTAeWAuh/+Pv8f/2hQgw8m6qz52+xKnUYKOCUDm0eym/i2tQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IWbr9YN1PU5l8Xww497zoUuM/l/KNtJh8KG/M8Cc8KU=; b=oF7nRm3W0O0gYBUTGBKP0nVHh68GemPzikqOfWLz5Ohe+snphy8jNmcai0f+y03Baj0Pr3crhZx/ruSZtTfaFagki8mioPux995ulvT5p5FmyVamehxUbNqeLdw4amFHyS7v0bqSmhh8b8iJxdPZhLUiAeSDGXGmQHC2DELhCAs= Received: from AS8PR04CA0192.eurprd04.prod.outlook.com (2603:10a6:20b:2f3::17) by VE1PR08MB5678.eurprd08.prod.outlook.com (2603:10a6:800:1a0::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.21; Thu, 2 Nov 2023 16:39:04 +0000 Received: from AMS0EPF00000195.eurprd05.prod.outlook.com (2603:10a6:20b:2f3:cafe::a5) by AS8PR04CA0192.outlook.office365.com (2603:10a6:20b:2f3::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.21 via Frontend Transport; Thu, 2 Nov 2023 16:39:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AMS0EPF00000195.mail.protection.outlook.com (10.167.16.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6954.19 via Frontend Transport; Thu, 2 Nov 2023 16:39:04 +0000 Received: from AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Thu, 2 Nov 2023 16:38:59 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Thu, 2 Nov 2023 16:38:59 +0000 Received: from e125768.cambridge.arm.com (10.2.78.50) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Thu, 2 Nov 2023 16:38:59 +0000 From: Victor Do Nascimento To: CC: , , , Victor Do Nascimento Subject: [PATCH V3 4/6] aarch64: Implement system register r/w arm ACLE intrinsic functions Date: Thu, 2 Nov 2023 16:38:32 +0000 Message-ID: <20231102163852.1860658-5-victor.donascimento@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231102163852.1860658-1-victor.donascimento@arm.com> References: <20231102163852.1860658-1-victor.donascimento@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AMS0EPF00000195:EE_|VE1PR08MB5678:EE_|DU6PEPF0000B61F:EE_|PAXPR08MB6573:EE_ X-MS-Office365-Filtering-Correlation-Id: 19490324-b3e6-4fdd-2007-08dbdbc24167 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: iAuwODjwf2S24zfZQZQIehxEiqXoqnm2padkxXA7oCvKCa5QVtFY2eyvzimXELNdvO3HJZyw9fk2fpj/xhEtOQFdeDYjP8Q89KZe3ckI94IQB8sB6xHVHezZ7BjVnP3qJgDOqGviJYfE+HA3cJkvkeb0NQJ0dY4kMu4ychiq5m/ssqBPf0iACqvN8B+MBE8Tb7TqZpINwBgaTLc9RQiraLPq7phkDoXrn2iUcAlaHy6qUMP7HEo+JPI9vKajKSxwCaVLl/TPfPZl3CxKmCMZxqWcC562t1zXkN5kQR/oh2uw/kc6upWRwB78xZ67rFQUREe4FY6avnzsF/M7bLoUWfLDSmafJp/9Q99io3jrbV/Opijta0d6z+y4HAx0xukGK0njNtFLM2DMVfAqMaCt6vF2B4jAC3SYyz3e+Ysp83WU2EF7DpJWX4tHFJW+u/Rne005TIOS7zEiLDAkOWEKC9L+YpwKyJFXaDSgrffestaeqlHJE8+I2K0p4727wMsOeJo+eX+mPKi0z1PzfY05TXwGBo7PdgeObIgdPK3ZSDxHXftoPBeXdLn21LYFacibXiYMywQ9q63EuKiaB2d4gwBOrD1FS40CdLskG1lykZiSr8gsVb3DiFUoW2A/q5tBu6x1DqTGLhpjZL9I5Itaiiid/Ermwrmhru1XCSTAhITJLgsVAQ+PEvCzNesd4LbVIaiiFkdd3J6Kwf0sKf7QmPa+vOOuvlyZGbQmZz39/8Bsh/ADEiUFv219QBqAzNw107AS+akeeimst48m3sjuuv0kweU3818qdG2KUGkCUD0= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(396003)(376002)(346002)(39850400004)(230922051799003)(451199024)(82310400011)(1800799009)(186009)(64100799003)(46966006)(36840700001)(40470700004)(478600001)(2906002)(30864003)(36756003)(40460700003)(54906003)(86362001)(70586007)(70206006)(5660300002)(26005)(41300700001)(1076003)(2616005)(47076005)(36860700001)(84970400001)(83380400001)(8936002)(336012)(8676002)(4326008)(7696005)(426003)(82740400003)(6916009)(316002)(6666004)(40480700001)(356005)(81166007)(36900700001);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5678 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DU6PEPF0000B61F.eurprd02.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 1bc4093e-543a-4f1c-b09b-08dbdbc239b6 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: M//ClxdVZBYbQ5bJ7QU6emO6HLGk8wnHFgVcE76PpY35oQaln48oUCSKmPv4QYYO2IIwu4uOKKQVmumyAHq1APDIQXAZ7zGQjbz+2iecuDkKijgAZgT2ABxMAzImYofEHTZVXxTeVhrJAEr/I6SMD9cS5aed4mXB0SWkdeKdiTYMtO/KZsR2bIlEXjXUQTEtoKkMQPy+fEnGp9HxdCU7Goh+PF9F3m6Nvix5/8UICqnfnXwyVrD6zMWZXkKTXaoeYWalBCxCdPhKbKAV5PObc3c7exVKcdRM4DxK7/DqIBcRrPhEgt4PH8Jp2+lM5PjNC1hdRqsjP4PMNwL36sUn/8fnjVI+tgL0rC1grhAQy+L+Y7A1ppaCKqc64UA5LQgAzmtm/hTERz7paohGh0VG/14KFcpgxwfqX7pv5kPXShGVOrLZGRTOJrJs+eAgKOZf4hGpJRMFRrO90s7M5Ssreoi8OyVoiR3gmAFgWvslTDPAWntcBerczKhq4QV0KVs8PbadHoCIPYCUmw3t7jKu2WRQc0xi0rzS0+i+Rr6svJ7eYp1pgVmww4Lsar32cE+auUxgo8Y6DSjmYAVwZ2ZsvBuHEEUe3YdjexrAspSOuytush5zsUy4yNQwSxHkjkHYwInV4Jq48N7X+82nccgEy4Hw8F54KRSm2a4CAdbJOVi3E1FfVhif5EUdCLsgnCf+WL5j/4SExJ8Ym7TPWsxUB3kQiZaPpju650CZklI2VyAqvb3cFGlccJLWXRqvD4x+MCyRkT8ortN3Mxb+0HbkgQ== X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(39850400004)(346002)(376002)(396003)(230922051799003)(186009)(82310400011)(1800799009)(64100799003)(451199024)(40470700004)(36840700001)(46966006)(84970400001)(26005)(2616005)(40460700003)(40480700001)(36756003)(86362001)(81166007)(82740400003)(426003)(336012)(2906002)(30864003)(83380400001)(478600001)(7696005)(1076003)(6666004)(36860700001)(47076005)(8676002)(316002)(6916009)(8936002)(4326008)(41300700001)(5660300002)(54906003)(70206006)(70586007);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2023 16:39:17.0472 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 19490324-b3e6-4fdd-2007-08dbdbc24167 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF0000B61F.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6573 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Implement the aarch64 intrinsics for reading and writing system registers with the following signatures: uint32_t __arm_rsr(const char *special_register); uint64_t __arm_rsr64(const char *special_register); void* __arm_rsrp(const char *special_register); float __arm_rsrf(const char *special_register); double __arm_rsrf64(const char *special_register); void __arm_wsr(const char *special_register, uint32_t value); void __arm_wsr64(const char *special_register, uint64_t value); void __arm_wsrp(const char *special_register, const void *value); void __arm_wsrf(const char *special_register, float value); void __arm_wsrf64(const char *special_register, double value); gcc/ChangeLog: * config/aarch64/aarch64-builtins.cc (enum aarch64_builtins): Add enums for new builtins. (aarch64_init_rwsr_builtins): New. (aarch64_general_init_builtins): Call aarch64_init_rwsr_builtins. (aarch64_expand_rwsr_builtin): New. (aarch64_general_expand_builtin): Call aarch64_general_expand_builtin. * config/aarch64/aarch64.md (read_sysregdi): New insn_and_split. (write_sysregdi): Likewise. * config/aarch64/arm_acle.h (__arm_rsr): New. (__arm_rsrp): Likewise. (__arm_rsr64): Likewise. (__arm_rsrf): Likewise. (__arm_rsrf64): Likewise. (__arm_wsr): Likewise. (__arm_wsrp): Likewise. (__arm_wsr64): Likewise. (__arm_wsrf): Likewise. (__arm_wsrf64): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/acle/rwsr.c: New. * gcc.target/aarch64/acle/rwsr-1.c: Likewise. * gcc.target/aarch64/acle/rwsr-2.c: Likewise. * gcc.dg/pch/rwsr-pch.c: Likewise. * gcc.dg/pch/rwsr-pch.hs: Likewise. --- gcc/config/aarch64/aarch64-builtins.cc | 191 ++++++++++++++++++ gcc/config/aarch64/aarch64.md | 18 ++ gcc/config/aarch64/arm_acle.h | 30 +++ gcc/testsuite/gcc.dg/pch/rwsr-pch.c | 7 + gcc/testsuite/gcc.dg/pch/rwsr-pch.hs | 10 + .../gcc.target/aarch64/acle/rwsr-1.c | 29 +++ .../gcc.target/aarch64/acle/rwsr-2.c | 25 +++ gcc/testsuite/gcc.target/aarch64/acle/rwsr.c | 144 +++++++++++++ 8 files changed, 454 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/pch/rwsr-pch.c create mode 100644 gcc/testsuite/gcc.dg/pch/rwsr-pch.hs create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/rwsr-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/rwsr-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/rwsr.c diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 04f59fd9a54..dd76cca611b 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -47,6 +47,7 @@ #include "stringpool.h" #include "attribs.h" #include "gimple-fold.h" +#include "builtins.h" #define v8qi_UP E_V8QImode #define v8di_UP E_V8DImode @@ -808,6 +809,17 @@ enum aarch64_builtins AARCH64_RBIT, AARCH64_RBITL, AARCH64_RBITLL, + /* System register builtins. */ + AARCH64_RSR, + AARCH64_RSRP, + AARCH64_RSR64, + AARCH64_RSRF, + AARCH64_RSRF64, + AARCH64_WSR, + AARCH64_WSRP, + AARCH64_WSR64, + AARCH64_WSRF, + AARCH64_WSRF64, AARCH64_BUILTIN_MAX }; @@ -1798,6 +1810,65 @@ aarch64_init_rng_builtins (void) AARCH64_BUILTIN_RNG_RNDRRS); } +/* Add builtins for reading system register. */ +static void +aarch64_init_rwsr_builtins (void) +{ + tree fntype = NULL; + tree const_char_ptr_type + = build_pointer_type (build_type_variant (char_type_node, true, false)); + +#define AARCH64_INIT_RWSR_BUILTINS_DECL(F, N, T) \ + aarch64_builtin_decls[AARCH64_##F] \ + = aarch64_general_add_builtin ("__builtin_aarch64_"#N, T, AARCH64_##F); + + fntype + = build_function_type_list (uint32_type_node, const_char_ptr_type, NULL); + AARCH64_INIT_RWSR_BUILTINS_DECL (RSR, rsr, fntype); + + fntype + = build_function_type_list (ptr_type_node, const_char_ptr_type, NULL); + AARCH64_INIT_RWSR_BUILTINS_DECL (RSRP, rsrp, fntype); + + fntype + = build_function_type_list (uint64_type_node, const_char_ptr_type, NULL); + AARCH64_INIT_RWSR_BUILTINS_DECL (RSR64, rsr64, fntype); + + fntype + = build_function_type_list (float_type_node, const_char_ptr_type, NULL); + AARCH64_INIT_RWSR_BUILTINS_DECL (RSRF, rsrf, fntype); + + fntype + = build_function_type_list (double_type_node, const_char_ptr_type, NULL); + AARCH64_INIT_RWSR_BUILTINS_DECL (RSRF64, rsrf64, fntype); + + fntype + = build_function_type_list (void_type_node, const_char_ptr_type, + uint32_type_node, NULL); + + AARCH64_INIT_RWSR_BUILTINS_DECL (WSR, wsr, fntype); + + fntype + = build_function_type_list (void_type_node, const_char_ptr_type, + const_ptr_type_node, NULL); + AARCH64_INIT_RWSR_BUILTINS_DECL (WSRP, wsrp, fntype); + + fntype + = build_function_type_list (void_type_node, const_char_ptr_type, + uint64_type_node, NULL); + AARCH64_INIT_RWSR_BUILTINS_DECL (WSR64, wsr64, fntype); + + fntype + = build_function_type_list (void_type_node, const_char_ptr_type, + float_type_node, NULL); + AARCH64_INIT_RWSR_BUILTINS_DECL (WSRF, wsrf, fntype); + + fntype + = build_function_type_list (void_type_node, const_char_ptr_type, + double_type_node, NULL); + AARCH64_INIT_RWSR_BUILTINS_DECL (WSRF64, wsrf64, fntype); +} + /* Initialize the memory tagging extension (MTE) builtins. */ struct { @@ -2019,6 +2090,8 @@ aarch64_general_init_builtins (void) aarch64_init_rng_builtins (); aarch64_init_data_intrinsics (); + aarch64_init_rwsr_builtins (); + tree ftype_jcvt = build_function_type_list (intSI_type_node, double_type_node, NULL); aarch64_builtin_decls[AARCH64_JSCVT] @@ -2599,6 +2672,113 @@ aarch64_expand_rng_builtin (tree exp, rtx target, int fcode, int ignore) return target; } +/* Expand the read/write system register builtin EXPs. */ +rtx +aarch64_expand_rwsr_builtin (tree exp, rtx target, int fcode) +{ + tree arg0, arg1; + rtx const_str, input_val, subreg; + enum machine_mode mode; + class expand_operand ops[2]; + + arg0 = CALL_EXPR_ARG (exp, 0); + + bool write_op = (fcode == AARCH64_WSR + || fcode == AARCH64_WSRP + || fcode == AARCH64_WSR64 + || fcode == AARCH64_WSRF + || fcode == AARCH64_WSRF64); + + /* Argument 0 (system register name) must be a string literal. */ + gcc_assert (TREE_CODE (arg0) == ADDR_EXPR + && TREE_CODE (TREE_TYPE (arg0)) == POINTER_TYPE + && TREE_CODE (TREE_OPERAND (arg0, 0)) == STRING_CST); + + const char *name_input = TREE_STRING_POINTER (TREE_OPERAND (arg0, 0)); + + tree len_tree = c_strlen (arg0, 1); + if (len_tree == NULL_TREE) + { + error_at (EXPR_LOCATION (exp), "invalid system register name provided"); + return const0_rtx; + } + + size_t len = TREE_INT_CST_LOW (len_tree); + char *sysreg_name = xstrdup (name_input); + + for (unsigned pos = 0; pos <= len; pos++) + sysreg_name[pos] = TOLOWER (sysreg_name[pos]); + + const char* name_output = aarch64_retrieve_sysreg ((const char *) sysreg_name, + write_op); + if (name_output == NULL) + { + error_at (EXPR_LOCATION (exp), "invalid system register name provided"); + return const0_rtx; + } + + /* Assign the string corresponding to the system register name to an RTX. */ + const_str = rtx_alloc (CONST_STRING); + PUT_CODE (const_str, CONST_STRING); + XSTR (const_str, 0) = ggc_strdup (name_output); + + /* Set up expander operands and call instruction expansion. */ + if (write_op) + { + arg1 = CALL_EXPR_ARG (exp, 1); + mode = TYPE_MODE (TREE_TYPE (arg1)); + input_val = copy_to_mode_reg (mode, expand_normal (arg1)); + + switch (fcode) + { + case AARCH64_WSR: + case AARCH64_WSRP: + case AARCH64_WSR64: + case AARCH64_WSRF64: + subreg = lowpart_subreg (DImode, input_val, mode); + break; + case AARCH64_WSRF: + subreg = gen_lowpart_SUBREG (SImode, input_val); + subreg = gen_lowpart_SUBREG (DImode, subreg); + break; + } + + create_fixed_operand (&ops[0], const_str); + create_input_operand (&ops[1], subreg, DImode); + expand_insn (CODE_FOR_aarch64_write_sysregdi, 2, ops); + + return target; + } + + /* Read operations are implied by !write_op. */ + gcc_assert (call_expr_nargs (exp) == 1); + + /* Emit the initial read_sysregdi rtx. */ + create_output_operand (&ops[0], target, DImode); + create_fixed_operand (&ops[1], const_str); + expand_insn (CODE_FOR_aarch64_read_sysregdi, 2, ops); + target = ops[0].value; + + /* Do any necessary post-processing on the result. */ + switch (fcode) + { + case AARCH64_RSR: + case AARCH64_RSRP: + case AARCH64_RSR64: + case AARCH64_RSRF64: + return lowpart_subreg (TYPE_MODE (TREE_TYPE (exp)), target, DImode); + case AARCH64_RSRF: + subreg = gen_lowpart_SUBREG (SImode, target); + return gen_lowpart_SUBREG (SFmode, subreg); + default: + gcc_unreachable (); + } + + error_at (EXPR_LOCATION (exp), + "Malformed call to read/write system register builtin"); + return target; +} + /* Expand an expression EXP that calls a MEMTAG built-in FCODE with result going to TARGET. */ static rtx @@ -2832,6 +3012,17 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target, case AARCH64_BUILTIN_RNG_RNDR: case AARCH64_BUILTIN_RNG_RNDRRS: return aarch64_expand_rng_builtin (exp, target, fcode, ignore); + case AARCH64_RSR: + case AARCH64_RSRP: + case AARCH64_RSR64: + case AARCH64_RSRF: + case AARCH64_RSRF64: + case AARCH64_WSR: + case AARCH64_WSRP: + case AARCH64_WSR64: + case AARCH64_WSRF: + case AARCH64_WSRF64: + return aarch64_expand_rwsr_builtin (exp, target, fcode); } if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5bb8c772be8..aee8f8ad65a 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -281,6 +281,8 @@ UNSPEC_UPDATE_FFRT UNSPEC_RDFFR UNSPEC_WRFFR + UNSPEC_SYSREG_RDI + UNSPEC_SYSREG_WDI ;; Represents an SVE-style lane index, in which the indexing applies ;; within the containing 128-bit block. UNSPEC_SVE_LANE_SELECT @@ -476,6 +478,22 @@ ;; Jumps and other miscellaneous insns ;; ------------------------------------------------------------------- +(define_insn "aarch64_read_sysregdi" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec_volatile:DI [(match_operand 1 "aarch64_sysreg_string" "")] + UNSPEC_SYSREG_RDI))] + "" + "mrs\t%x0, %1" +) + +(define_insn "aarch64_write_sysregdi" + [(unspec_volatile:DI [(match_operand 0 "aarch64_sysreg_string" "") + (match_operand:DI 1 "register_operand" "rZ")] + UNSPEC_SYSREG_WDI)] + "" + "msr\t%0, %x1" +) + (define_insn "indirect_jump" [(set (pc) (match_operand:DI 0 "register_operand" "r"))] "" diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h index 7599a32301d..71ada878299 100644 --- a/gcc/config/aarch64/arm_acle.h +++ b/gcc/config/aarch64/arm_acle.h @@ -314,6 +314,36 @@ __rndrrs (uint64_t *__res) #pragma GCC pop_options +#define __arm_rsr(__regname) \ + __builtin_aarch64_rsr (__regname) + +#define __arm_rsrp(__regname) \ + __builtin_aarch64_rsrp (__regname) + +#define __arm_rsr64(__regname) \ + __builtin_aarch64_rsr64 (__regname) + +#define __arm_rsrf(__regname) \ + __builtin_aarch64_rsrf (__regname) + +#define __arm_rsrf64(__regname) \ + __builtin_aarch64_rsrf64 (__regname) + +#define __arm_wsr(__regname, __value) \ + __builtin_aarch64_wsr (__regname, __value) + +#define __arm_wsrp(__regname, __value) \ + __builtin_aarch64_wsrp (__regname, __value) + +#define __arm_wsr64(__regname, __value) \ + __builtin_aarch64_wsr64 (__regname, __value) + +#define __arm_wsrf(__regname, __value) \ + __builtin_aarch64_wsrf (__regname, __value) + +#define __arm_wsrf64(__regname, __value) \ + __builtin_aarch64_wsrf64 (__regname, __value) + #ifdef __cplusplus } #endif diff --git a/gcc/testsuite/gcc.dg/pch/rwsr-pch.c b/gcc/testsuite/gcc.dg/pch/rwsr-pch.c new file mode 100644 index 00000000000..f49d276ee9a --- /dev/null +++ b/gcc/testsuite/gcc.dg/pch/rwsr-pch.c @@ -0,0 +1,7 @@ +#include "rwsr-pch.h" +extern int printf (const char *, ...); +int main (void) { + long long val = rwsr (); + printf ("%lld\n", val); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pch/rwsr-pch.hs b/gcc/testsuite/gcc.dg/pch/rwsr-pch.hs new file mode 100644 index 00000000000..79b375448c5 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pch/rwsr-pch.hs @@ -0,0 +1,10 @@ +/* { dg-skip-if "" { ! aarch64*-*-* } } */ +static inline long long +rwsr (void) +{ + long long a = __builtin_aarch64_rsr64 ("trcseqstr"); + __builtin_aarch64_wsr64 ("trcseqstr", a + 1); + a = __builtin_aarch64_rsr64 ("trcseqstr"); + return a; +} + diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr-1.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-1.c new file mode 100644 index 00000000000..a4e1e76634b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-1.c @@ -0,0 +1,29 @@ +/* Test the __arm_[r,w]sr ACLE intrinsics family. */ +/* Ensure that illegal behavior is rejected by the compiler. */ + +/* { dg-do compile } */ +/* { dg-options "-O3 -march=armv8.4-a" } */ + +#include + +/* Ensure that read/write-only register attributes are respected by the compiler. */ +void +test_rwsr_read_write_only () +{ + /* Attempt to write to read-only registers. */ + long long a = __arm_rsr64 ("aidr_el1"); /* Read ok. */ + __arm_wsr64 ("aidr_el1", a); /* { dg-error {invalid system register name provided} } */ + + /* Attempt to read from write-only registers. */ + __arm_wsr64("icc_asgi1r_el1", a); /* Write ok. */ + long long b = __arm_rsr64("icc_asgi1r_el1"); /* { dg-error {invalid system register name provided} } */ +} + +/* Ensure that empty strings are rejected. */ +void +test_empty_string () +{ + long long c = __arm_rsr64(""); /* { dg-error "invalid system register name provided" } */ + __arm_wsr64("", c); /* { dg-error "invalid system register name provided" } */ +} + diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr-2.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-2.c new file mode 100644 index 00000000000..3cccfa5dc70 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr-2.c @@ -0,0 +1,25 @@ +/* Test the __arm_[r,w]sr ACLE intrinsics family. */ +/* Ensure correctness of the system register encoding parser. */ + +/* { dg-do compile } */ +/* { dg-options "-std=c2x -O3 -march=armv8.4-a" } */ + +#include + +void +test_leading_zeros () +{ + __uint64_t b = __arm_rsr64("S1_2_C03_C04_5"); /* { dg-error "invalid system register name provided" } */ + __arm_wsr64("S1_2_C03_C04_5", b); /* { dg-error "invalid system register name provided" } */ +} + +void +test_bounds () +{ + __uint64_t b; + b = __arm_rsr64("S4_2_C3_C4_5"); /* { dg-error "invalid system register name provided" } */ + b = __arm_rsr64("S1_8_C3_C4_5"); /* { dg-error "invalid system register name provided" } */ + b = __arm_rsr64("S1_2_C16_C4_5"); /* { dg-error "invalid system register name provided" } */ + b = __arm_rsr64("S1_2_C3_C16_5"); /* { dg-error "invalid system register name provided" } */ + b = __arm_rsr64("S1_2_C3_C4_8"); /* { dg-error "invalid system register name provided" } */ +} diff --git a/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c new file mode 100644 index 00000000000..3af4b960306 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/rwsr.c @@ -0,0 +1,144 @@ +/* Test the __arm_[r,w]sr ACLE intrinsics family. */ +/* Check that function variants for different data types handle types correctly. */ +/* { dg-do compile } */ +/* { dg-options "-O1 -march=armv8.4-a" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include + +/* +** get_rsr: +** ... +** mrs x([0-9]+), s2_1_c0_c7_4 +** add w\1, w\1, 1 +** ... +*/ +int +get_rsr () +{ + int a = __arm_rsr("trcseqstr"); + return a+1; +} + +/* +** get_rsrf: +** mrs x([0-9]+), s2_1_c0_c7_4 +** fmov s[0-9]+, w\1 +** ... +*/ +float +get_rsrf () +{ + return __arm_rsrf("trcseqstr"); +} + +/* +** get_rsrp: +** mrs x0, s2_1_c0_c7_4 +** ret +*/ +void * +get_rsrp () +{ + return __arm_rsrp("trcseqstr"); +} + +/* +** get_rsr64: +** mrs x0, s2_1_c0_c7_4 +** ret +*/ +long long +get_rsr64 () +{ + return __arm_rsr64("trcseqstr"); +} + +/* +** get_rsrf64: +** mrs x([0-9]+), s2_1_c0_c7_4 +** fmov d[0-9]+, x\1 +** ... +*/ +double +get_rsrf64 () +{ + return __arm_rsrf64("trcseqstr"); +} + +/* +** set_wsr32: +** ... +** add w([0-9]+), w\1, 1 +** msr s2_1_c0_c7_4, x\1 +** ... +*/ +void +set_wsr32 (int a) +{ + __arm_wsr("trcseqstr", a+1); +} + +/* +** set_wsrp: +** ... +** msr s2_1_c0_c7_4, x[0-9]+ +** ... +*/ +void +set_wsrp (void *a) +{ + __arm_wsrp("trcseqstr", a); +} + +/* +** set_wsr64: +** ... +** msr s2_1_c0_c7_4, x[0-9]+ +** ... +*/ +void +set_wsr64 (long long a) +{ + __arm_wsr64("trcseqstr", a); +} + +/* +** set_wsrf32: +** ... +** fmov w([0-9]+), s[0-9]+ +** msr s2_1_c0_c7_4, x\1 +** ... +*/ +void +set_wsrf32 (float a) +{ + __arm_wsrf("trcseqstr", a); +} + +/* +** set_wsrf64: +** ... +** fmov x([0-9]+), d[0-9]+ +** msr s2_1_c0_c7_4, x\1 +** ... +*/ +void +set_wsrf64(double a) +{ + __arm_wsrf64("trcseqstr", a); +} + +/* +** set_custom: +** ... +** mrs x0, s1_2_c3_c4_5 +** ... +** msr s1_2_c3_c4_5, x0 +** ... +*/ +void set_custom() +{ + __uint64_t b = __arm_rsr64("S1_2_C3_C4_5"); + __arm_wsr64("S1_2_C3_C4_5", b); +} -- 2.41.0