From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by sourceware.org (Postfix) with ESMTPS id 4AE013858D3C for ; Wed, 8 Nov 2023 11:09:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4AE013858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4AE013858D3C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::232 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699441779; cv=none; b=oz7EV/gu6mYncrwk6/8TEFKIl4UGRYucP5oHEYkaStUSf0lzXXAQ293oscIqU6j08aI9F9Tq+6wWWLU0P8F3efP6EszEfmd+tsd6wEUG0NngfjE3APS/vdkli3JE1r3SVjptjH50dK2nkY+IDUt9V0ZcKilL15v3cR/1o73OYhA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699441779; c=relaxed/simple; bh=OWCuDmA5lKn4f1v+Y0PiC5DP+Dq59WFQbSTbTUucQj8=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=mKNhjc9ziuFl+TnWkWIZZmwCDqIP8dZN3kBW7/PG4O5uhwuqtgv5om4aILeBxVkX6ckGCQDFyoPRmY74n8O6I/bBI9g7f1OsdJNuDQlMuD4IbQ2ZNFMK+PfulSwu6zvjWJFyOKwJusNMti7yOTX4kpGjHs35HJnWf33P1SSdl9E= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2c6b30aca06so88759491fa.3 for ; Wed, 08 Nov 2023 03:09:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1699441775; x=1700046575; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pnTctBQe+C91dJSpFcaZX61wy8ziDziud3AdbvexBXs=; b=gKs4fxpu9B2lIZRZkWTUah8K/BBOknz9Jc2aNNNOO2IiYAUEYURcXm7b37dY6EIpPD Bgf6LfIUkZDJx9lR9EeoQn1sAtG20Ny5XxQ+rHCtyIfYjzPRExj++nplZr3R/AkYrf5H lGSbzcH+kej3tSc91qJF7VGa4Sdv645wHnjnDy5XWmE5JrGUPkkJ9FSahF2QkJKVI/je xe6LaCqjvRZb6KfJmo+9e3nUH3+pOWFoMBsDP3BhTkHHbEjeep/ArpGiOG3uiQn4N9bo P+2YN2QOcm6uMBDs+yGpnl8hQO6GqV7N0Lm3WWXK+01u7vei0XjXMvOcY2P2GJJ2bPGo /cYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699441775; x=1700046575; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pnTctBQe+C91dJSpFcaZX61wy8ziDziud3AdbvexBXs=; b=B9DoWTkHi0suqtqZkQvUcXxwh1jwidP7QSWXOtZy7ZF4AZ3PK3UuVN+IqTQ5CC8yvc IVC9Xs1PYwuNHBn+fiGQmIPxkyotMej6wtzncoRF2vdfZZpzQNgZDY9rlCXQb7XXwc/V z92KCJq1jyitSOk3q4CTRO4mFf8tfIdYR22xlpPLnyjAOQnEzHIUx0baDnRIcPibhM60 NRopeVCU2353TtKKuT1XHNgTZC/7DG7GGzWJEr8QRxTgibT2iP+of1Mw4AtKORl2XcJK sORFSqi54/YI3FTP38Tpt1FMr+kCAKT4k7wMH+K1ft0hcGvE7wzTJxheWZgr4LKiUk50 lblg== X-Gm-Message-State: AOJu0YyukFLRu0RA4+k5ci9jxr12g8O4iKtcgY95FAt0cjtnb2w8lbY1 eWQx6VdH88IKZATJqkAty9XIt8Z9TdfEIsmfeSLFJg== X-Google-Smtp-Source: AGHT+IF74Tpdt2a2BVUBQ3VoFcGCRI/6ZvPu74tMi6ZoRT/zCj8vxKGMjTHGRzmb/7hhyK7ePnk0ag== X-Received: by 2002:a05:651c:154c:b0:2c5:1eb6:bd1e with SMTP id y12-20020a05651c154c00b002c51eb6bd1emr2057447ljp.43.1699441774892; Wed, 08 Nov 2023 03:09:34 -0800 (PST) Received: from troughton.sou.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id g4-20020a05600c310400b004068e09a70bsm18903289wmo.31.2023.11.08.03.09.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Nov 2023 03:09:34 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors Date: Wed, 8 Nov 2023 11:09:13 +0000 Message-Id: <20231108110914.2710021-3-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231108110914.2710021-1-mary.bennett@embecosm.com> References: <20231108110914.2710021-1-mary.bennett@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gcc/ChangeLog: * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. * config/riscv/corev.md: Likewise. --- gcc/config/riscv/constraints.md | 15 ++++++++------- gcc/config/riscv/corev.md | 4 ++-- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 68be4515c04..2711efe68c5 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -151,13 +151,6 @@ (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS" "An integer register for ZFA or XTheadFmv.") -;; CORE-V Constraints -(define_constraint "CVP2" - "Checking for CORE-V ALU clip if ival plus 1 is a power of 2" - (and (match_code "const_int") - (and (match_test "IN_RANGE (ival, 0, 1073741823)") - (match_test "exact_log2 (ival + 1) != -1")))) - ;; Vector constraints. (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" @@ -246,3 +239,11 @@ A MEM with a valid address for th.[l|s]*ur* instructions." (and (match_code "mem") (match_test "th_memidx_legitimate_index_p (op, true)"))) + +;; CORE-V Constraints +(define_constraint "CV_alu_pow2" + "@internal + Checking for CORE-V ALU clip if ival plus 1 is a power of 2" + (and (match_code "const_int") + (and (match_test "IN_RANGE (ival, 0, 1073741823)") + (match_test "exact_log2 (ival + 1) != -1")))) diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index be66b1428a7..0109e1836cf 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -516,7 +516,7 @@ (define_insn "riscv_cv_alu_clip" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIP))] "TARGET_XCVALU && !TARGET_64BIT" @@ -529,7 +529,7 @@ (define_insn "riscv_cv_alu_clipu" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIPU))] "TARGET_XCVALU && !TARGET_64BIT" -- 2.34.1