From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by sourceware.org (Postfix) with ESMTPS id 676363858D38 for ; Wed, 8 Nov 2023 11:33:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 676363858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 676363858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.254.200.128 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699443204; cv=none; b=gK4Qj6XNKEuHudNU7Ky6RmCcLNOT6i6BtOug+rIR/7l0Gc3+Y7sMnK0ThVr/zGzLUCQl5/vHF9CiX7R+G7x4KqMhXXhnFb5CxocgLBWUT75a1Ie2OjqtITLwXFURc2ijh0a6ROpL4Z1tdVGvlCB0D8HBRu2IeW7bnODqpQgxYeE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699443204; c=relaxed/simple; bh=c45oWuAVmuaiOGJdtp1xWu9oChPlh9B2MzvdhypAncA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=c4jfVC1Ezf7SzhLJbFqxij763VQgsMeueG/cXeL4PZHJ4ivcA8pbSxUXgnyRqTmrxdIVrYdLJ5V9IoA1fH8WiRuTgg+n1JXlagEGQkKU0ORyuz8HGb3f8VdAlNC4T6ClUYb2TII1egHm7oObI8gYGfBCW7btrctyf/qOdAoSjbw= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp73t1699443188t0d7656r Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 08 Nov 2023 19:33:07 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 7YFKcddXaghfvTLHSVn9gir0q90J+cyKpEIIyb9CakQiF84Jk5U6y5Kr1mknG dKMTzhJGhixPCRCsOQcdnuE5CNDxfZsbIhIwA4AMlkQ85MRJNA8QaO0iSOwzt0kmmqPOXy1 fFGmMF16L9yLA7GIwSpRVC1BRSxRLaZvb8x0m/zTQTccrQwLiSMUhSz9wheDKCo2FhBN6AY kl75nhfvUGjDGgOKmazqG+75mk4crycT81IUH1vqgV/aBNFAYIcyIaBoSY6P/3tVV+fXV4o QYXBdBi2NgcyJzdq66T0lbiOMuIZtoj4AxPhMzGSQZBTnKqoXnqiOUBK8ECWSCch1gHF62L FNwBSmnqm5fC3qYliIG+Cy+JtPwFyFvFwCBKcyRB2YTCeqPIVe9lcWUQ+5nG9O73JZtITu1 0EgY2LuPoO2RSTiN5HsPqw== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 18426568505018931965 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: Juzhe-Zhong Subject: [Committed] RISC-V: Fix VSETVL VL check condition bug Date: Wed, 8 Nov 2023 19:33:06 +0800 Message-Id: <20231108113306.1820431-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: When fixing the induction variable vectorization bug, notice there is a ICE bug in VSETVL PASS: 0x178015b rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*) ../../../../gcc/gcc/rtl.cc:770 0x1079cdd rhs_regno(rtx_def const*) ../../../../gcc/gcc/rtl.h:1934 0x1dab360 vsetvl_info::parse_insn(rtl_ssa::insn_info*) ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:1070 0x1daa272 vsetvl_info::vsetvl_info(rtl_ssa::insn_info*) ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:746 0x1da5d98 pre_vsetvl::fuse_local_vsetvl_info() ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:2708 0x1da94d9 pass_vsetvl::lazy_vsetvl() ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3444 0x1da977c pass_vsetvl::execute(function*) ../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3504 Committed as it is obvious. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc: Fix ICE. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vl-use-ice.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vl-use-ice.c | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vl-use-ice.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 77dbf159d41..3fa25a6404d 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1067,7 +1067,7 @@ public: break; } rtx avl = ::get_avl (rinsn); - if (!avl || REGNO (get_vl ()) != REGNO (avl)) + if (!avl || !REG_P (avl) || REGNO (get_vl ()) != REGNO (avl)) { m_vl_used_by_non_rvv_insn = true; break; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vl-use-ice.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vl-use-ice.c new file mode 100644 index 00000000000..715c7e0cad2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vl-use-ice.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +void foo(void *in1, void *out, size_t avl) { + + size_t vl = __riscv_vsetvl_e32m1(avl); + vint32m1_t v = __riscv_vmv_v_x_i32m1 (vl, 16); + __riscv_vse32_v_i32m1 (out, v, 16); +} -- 2.36.3