From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by sourceware.org (Postfix) with ESMTPS id 314513858D1E for ; Wed, 8 Nov 2023 13:27:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 314513858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 314513858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=18.132.163.193 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699450056; cv=none; b=UFkLBauFhG+5gZA8LG+FVLSjx9oJBvN2CN4UfnU27KBX4T1wCiwxqQblNsKLG6H396SmezUQLp806gbrRxmMB8766pOnpTUu9PuayMa+/0D01jxWqOofW0eHmXkZ/cedptxmVy47nVOtzagE97cn2Einio1kSInAEi6oDu4riJ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699450056; c=relaxed/simple; bh=8dxgvGpRo3l9aVFbQhk90Rrd/Xn/3spj4dhNNRFeBE4=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=laIUw5OxbZAstX02IjB5RUYPlGj8+SymOOX06UGtRgkzIo8e60AO6jgLL+ycTjp2ByK7m2Sf7Ssp64BfF6uG4awYhuvFV+kDl75gTORdDJc2Mh17SsmErJ0RuiWJdpzPgtjgH6UtpQjyiZrdT2m1Rkjz2eErdqI8/A3YWXlj40s= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp62t1699450046tefbvffw Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 08 Nov 2023 21:27:25 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: 90EFqYDyPxCEeNQ2nEe1wKk6hnNlKazoxH5xUoUNGIkGf7EMkAR9/A6ReBb6Q S4uflTKqyC1v+/zx7e5LE15ZoWpua4km96DkQbDhDHwYcWxWiKUIxSd8Q5WsnQiTiQDM687 cqLmZDLwegasPdJxmR8YTpajY4fSv+RKifrzIJ9Y1aY0EKazXTTUo1+E8daLBoczZe2V/H1 YrAg4JTIcYPxKGVQL6vlR5WLXMC3FUbIDB0Hb26iQT1JBZd30k/HgqxMJHZiCZ9KtZwsLHY NIO/m7g3292CfLHnG0xDpbUD0k18hfRDmIS35iE41Z/DImuXNAe4UAgquYPVdWa4C1Cf/W/ uzy+TUwzr/mNSPbYXiQkl6T1rfj1RbwNX0BPvV2GJlGRPsu1/IOWg83uz9geL4d4Nl/4+np 5ZuFlSfZCtf82O7xrO3BIg== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 4170487914281288583 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH] RISC-V: Removed unnecessary sign-extend for vsetvl Date: Wed, 8 Nov 2023 21:27:25 +0800 Message-Id: <20231108132725.1331224-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, This patch try to combine bellow two insns and then further remove unnecessary sign_extend operations. This optimization is borrowed from LLVM (https://godbolt.org/z/4f6v56xej): (set (reg:DI 134 [ _1 ]) (unspec:DI [ (const_int 19 [0x13]) (const_int 8 [0x8]) (const_int 5 [0x5]) (const_int 2 [0x2]) repeated x2 ] UNSPEC_VSETVL)) (set (reg/v:DI 135 [ ]) (sign_extend:DI (subreg:SI (reg:DI 134 [ _1 ]) 0))) The reason we can remove signe_extend is because currently the vl value returned by the vsetvl instruction ranges from 0 to 65536 (uint16_t), and bits 17 to 63 (including 31) are always 0, so there is no change after sign_extend. Note that for HI and QI modes we cannot do this. Of course, if the range of instructions returned by vsetvl later expands to 32bits, then this combine pattern needs to be removed. But that could be a long time from now. gcc/ChangeLog: * config/riscv/vector.md (*vsetvldi_no_side_effects_si_extend): New combine pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/vsetvl_int.c: New test. --- gcc/config/riscv/vector.md | 41 +++++++++++++++++++ .../gcc.target/riscv/rvv/vsetvl/vsetvl_int.c | 31 ++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index e23f64938b7..d1499d330ff 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1604,6 +1604,47 @@ [(set_attr "type" "vsetvl") (set_attr "mode" "SI")]) +;; This pattern use to combine bellow two insns and then further remove +;; unnecessary sign_extend operations: +;; (set (reg:DI 134 [ _1 ]) +;; (unspec:DI [ +;; (const_int 19 [0x13]) +;; (const_int 8 [0x8]) +;; (const_int 5 [0x5]) +;; (const_int 2 [0x2]) repeated x2 +;; ] UNSPEC_VSETVL)) +;; (set (reg/v:DI 135 [ ]) +;; (sign_extend:DI (subreg:SI (reg:DI 134 [ _1 ]) 0))) +;; +;; The reason we can remove signe_extend is because currently the vl value +;; returned by the vsetvl instruction ranges from 0 to 65536 (uint16_t), and +;; bits 17 to 63 (including 31) are always 0, so there is no change after +;; sign_extend. Note that for HI and QI modes we cannot do this. +;; Of course, if the range of instructions returned by vsetvl later expands +;; to 32bits, then this combine pattern needs to be removed. But that could be +;; a long time from now. +(define_insn_and_split "*vsetvldi_no_side_effects_si_extend" + [(set (match_operand:DI 0 "register_operand") + (sign_extend:DI + (subreg:SI + (unspec:DI [(match_operand:P 1 "csr_operand") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand") + (match_operand 4 "const_int_operand") + (match_operand 5 "const_int_operand")] UNSPEC_VSETVL) 0)))] + "TARGET_VECTOR && TARGET_64BIT" + "#" + "&& 1" + [(set (match_dup 0) + (unspec:DI [(match_dup 1) + (match_dup 2) + (match_dup 3) + (match_dup 4) + (match_dup 5)] UNSPEC_VSETVL))] + "" + [(set_attr "type" "vsetvl") + (set_attr "mode" "SI")]) + ;; RVV machine description matching format ;; (define_insn "" ;; [(set (match_operand:MODE 0) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c new file mode 100644 index 00000000000..4cdd5877742 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_int.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "riscv_vector.h" + +void bar1 (int32_t a); + +int32_t +foo1 () +{ + int32_t a = __riscv_vsetvl_e8mf8(19); + bar1 (a); + return a; +} + +void bar2 (uint32_t a); + +uint32_t +foo2 () +{ + uint32_t a = __riscv_vsetvl_e8mf8(19); + bar2 (a); + return a; +} + +int32_t foo3 () +{ + return __riscv_vsetvl_e8mf8(19); +} + +/* { dg-final { scan-assembler-not {sext\.w} { target { no-opts "-O0" "-g" } } } } */ -- 2.36.3