From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id E772F3858D33 for ; Thu, 9 Nov 2023 02:39:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E772F3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E772F3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.207.22.56 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699497570; cv=none; b=aIbrMn49goUdiTW1FSLV7Z2ZfvOJMEosjP51yeQhtFWTkiwjCI+uA/DdOD9MNvNdpOIs7kke2NGktLWilDbp3rCAvfiL7Rh70vOs0i+XPiYIjBTr1yZ3s0NdXRegc7PAQRTbpq49mSg8A6cQ+HJ1GFpPkHVs2bKynnqvM0mBJLA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699497570; c=relaxed/simple; bh=ILYduG/og0Gufm+jyKlZYR37/NqmPiHHiM93bppCOLM=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=ogi5oMlRgpthvqKFWy9S7EHtalmQrS+hfyKohlH50E3LNp2N6TwmJQl6L7sgoZwah6SomoPc2RWT0yAgY/twkO7mYvtV6tC1RPuvrdA6vGtnTQ6b6iBvQfAPEzVx3PtneyUrF8KQvZyvjHwj83s7rd7FeljglR70BXuiA3/UHrk= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp90t1699497559tyrfj11z Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 09 Nov 2023 10:39:18 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: RrZlkntZBfnrg5J2mh2WuBaewuD0O8w6byv3apBbKwjZ8Q6/fL7s9AtjG6B+h yGfwzkIdEDjkrE2RlXkdfIB+26GCMy96+CnikRFy+ofBzgYlOK1BRU+d9e7b1B4jjHlM22w sZaPePfa0/CwP2Eye2VUcLjO0hET5/kAxaOpXrXkqZI4CuITWXsh8qEHjOrZKABRn3AZFJ1 loGfzcA2Lz955jrJ5/dmmEUpCb+YkR5PuLHkAqP3iS3i/Ny/DB7lFl4khaBlPhIioFWQkPG JY6o68wjp6W5pNDq7T8C1V1vebDhFp1qwzSVdnB08q+Z7Bg07qfvPHSqdMnLL+oR5ntAioP JsBkIhq1ZU2xuT+RjL5VzmH0FEsQh7jAiHpPR3A1kkQjGyMfP4ACP/ymSIR0Tyi+CBrtani o13i+4I6vnM= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 7014531374703527461 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix dynamic LMUL cost model ICE Date: Thu, 9 Nov 2023 10:39:17 +0800 Message-Id: <20231109023917.3985192-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: When trying to use dynamic LMUL to compile benchmark. Notice there is a bunch ICEs. This patch fixes those ICEs and append tests. gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (costs::preferred_new_lmul_p): Fix ICE. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c: New test. * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c: New test. --- gcc/config/riscv/riscv-vector-costs.cc | 11 +++++--- .../costmodel/riscv/rvv/dynamic-lmul-ice-1.c | 25 +++++++++++++++++++ .../costmodel/riscv/rvv/dynamic-lmul-ice-2.c | 22 ++++++++++++++++ .../costmodel/riscv/rvv/dynamic-lmul-ice-3.c | 14 +++++++++++ 4 files changed, 69 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c diff --git a/gcc/config/riscv/riscv-vector-costs.cc b/gcc/config/riscv/riscv-vector-costs.cc index af87388a1e4..8036c9c40d7 100644 --- a/gcc/config/riscv/riscv-vector-costs.cc +++ b/gcc/config/riscv/riscv-vector-costs.cc @@ -231,7 +231,9 @@ compute_local_live_ranges ( TODO: We may elide the cases that the unnecessary IMM in the future. */ - if (is_gimple_val (var) && !POINTER_TYPE_P (TREE_TYPE (var))) + if (poly_int_tree_p (var) + || (is_gimple_val (var) + && !POINTER_TYPE_P (TREE_TYPE (var)))) { biggest_mode = get_biggest_mode (biggest_mode, @@ -416,7 +418,8 @@ static void update_local_live_ranges ( vec_info *vinfo, hash_map> &program_points_per_bb, - hash_map> &live_ranges_per_bb) + hash_map> &live_ranges_per_bb, + machine_mode *biggest_mode) { loop_vec_info loop_vinfo = dyn_cast (vinfo); if (!loop_vinfo) @@ -501,6 +504,8 @@ update_local_live_ranges ( : get_store_value (gsi_stmt (si)); tree sel_type = build_nonstandard_integer_type ( TYPE_PRECISION (TREE_TYPE (var)), 1); + *biggest_mode + = get_biggest_mode (*biggest_mode, TYPE_MODE (sel_type)); tree sel = build_decl (UNKNOWN_LOCATION, VAR_DECL, get_identifier ("vect_perm"), sel_type); pair &live_range = live_ranges->get_or_insert (sel, &existed_p); @@ -572,7 +577,7 @@ costs::preferred_new_lmul_p (const vector_costs *uncast_other) const /* Update live ranges according to PHI. */ update_local_live_ranges (other->m_vinfo, program_points_per_bb, - live_ranges_per_bb); + live_ranges_per_bb, &biggest_mode); /* TODO: We calculate the maximum live vars base on current STMTS sequence. We can support live range shrink if it can give us diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c new file mode 100644 index 00000000000..4f019ccae6b --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-1.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic" } */ + +int a, *b[9], c, d, e; + +static int +fn1 () +{ + for (c = 6; c >= 0; c--) + for (d = 0; d < 2; d++) + { + b[d * 2 + c] = 0; + e = a > 1 ? : 0; + if (e == 2) + return 0; + } + return 0; +} + +int +main () +{ + fn1 (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c new file mode 100644 index 00000000000..6fc8062f23b --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-2.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -Ofast -ftree-vectorize --param riscv-autovec-lmul=dynamic" } */ + +typedef struct rtx_def *rtx; +struct replacement { + rtx *where; + rtx *subreg_loc; + int mode; +}; +static struct replacement replacements[150]; +void move_replacements (rtx *x, rtx *y, int n_replacements) +{ + int i; + for (i = 0; i < n_replacements; i++) + if (replacements[i].subreg_loc == x) + replacements[i].subreg_loc = y; + else if (replacements[i].where == x) + { + replacements[i].where = y; + replacements[i].subreg_loc = 0; + } +} diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c new file mode 100644 index 00000000000..c1f698b9a68 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O2 -ftree-vectorize -flto -fno-use-linker-plugin -flto-partition=none --param riscv-autovec-lmul=dynamic" } */ + +void (*foo[6][6]) (int); +void bar (hdR) + int hdR; +{ } +void xxx () +{ + unsigned int i, j; + for (i = 0; i < 6; ++i) + for (j = 0; j < 6; ++j) + foo [i][j] = bar; +} -- 2.36.3