From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 373E13858D37 for ; Thu, 9 Nov 2023 06:51:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 373E13858D37 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 373E13858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.93 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699512665; cv=none; b=fvRk40kDZMsPdqhd0SvqVvnqjzTt+MUOb3DdJ9e3BbFvcPRR488EdOFnapBwm2d37i4LmmpWfm/J7vyOeCQWlDTYOKGFI5zyx6spCH9vGUJNp/FVuUKRDUOz4e8XtV4gbKYQKCq2ZuAesqjdpivk/OBUeQmx8KBbF5c82QSU9lI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699512665; c=relaxed/simple; bh=UCaabpvGs1nEP1Cx599W41qDDLKAoCENAi0bxx88KKw=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=vfWAfKcdcRpL9f9rQuL9Rt3aOk0Waz7uLN0k0SS/+cT9IOJ1cfl2Xv8Q7jcJqNCoiZwfqQD/fmkVps/4jPr1mYQuDhhZ7SXPwJSomMW5tRYAYdoZNKK+PUMY+C4SSZRnkJp1WwHCM4C1JeYWnjxYy0QrLDE+hVRQgMqSdCMaugY= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699512663; x=1731048663; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=UCaabpvGs1nEP1Cx599W41qDDLKAoCENAi0bxx88KKw=; b=C0i49je2Yfex9HOnrATp8J1GUr+M95Qv9L23b7b2Baxf3uT6j4PJTOtx G9nlfB838vQZzEZBs/FlJ7t1CuXzqtUD54kX5VrF69fl9XjkTClhQoZDs 5EWZUBqu1rr8HFjCtenqO7xO4ipuTfIdCW22r24loWuQACS3rgogObg0I 86smP5rwUdYdB2PE7K5SlaBk6OF/2V5+b7nHy2oK80h5G9QcZdew/bnsn ZkJq1/MfNtz7/+ACKa4rDmQ0rUYDZQbZHQgwCg5CKEACeaMrYthHRxO/T LmtSKnoYAoshenin170cECFE8ATjctb7d74zU5rJIcG7rhAaCptxSnci4 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="387094167" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="387094167" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2023 22:51:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="880491620" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="880491620" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 08 Nov 2023 22:51:00 -0800 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 5CF9310056F2; Thu, 9 Nov 2023 14:50:59 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Refine frm emit after bb end in succ edges Date: Thu, 9 Nov 2023 14:50:57 +0800 Message-Id: <20231109065057.3179104-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Pan Li This patch would like to fine the frm insn emit when we meet abnormal edge in the loop. Conceptually, we only need to emit once when abnormal instead of every iteration in the loop. This patch would like to fix this defect and only perform insert_insn_end_basic_block when at least one succ edge is abnormal. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_frm_emit_after_bb_end): Only perform once emit when at least one succ edge is abnormal. Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 08ff05dcc3f..e25692b86fc 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -9348,20 +9348,33 @@ static void riscv_frm_emit_after_bb_end (rtx_insn *cur_insn) { edge eg; + bool abnormal_edge_p = false; edge_iterator eg_iterator; basic_block bb = BLOCK_FOR_INSN (cur_insn); FOR_EACH_EDGE (eg, eg_iterator, bb->succs) + { + if (eg->flags & EDGE_ABNORMAL) + abnormal_edge_p = true; + else + { + start_sequence (); + emit_insn (gen_frrmsi (DYNAMIC_FRM_RTL (cfun))); + rtx_insn *backup_insn = get_insns (); + end_sequence (); + + insert_insn_on_edge (backup_insn, eg); + } + } + + if (abnormal_edge_p) { start_sequence (); emit_insn (gen_frrmsi (DYNAMIC_FRM_RTL (cfun))); rtx_insn *backup_insn = get_insns (); end_sequence (); - if (eg->flags & EDGE_ABNORMAL) - insert_insn_end_basic_block (backup_insn, bb); - else - insert_insn_on_edge (backup_insn, eg); + insert_insn_end_basic_block (backup_insn, bb); } commit_edge_insertions (); -- 2.34.1