From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-113.freemail.mail.aliyun.com (out30-113.freemail.mail.aliyun.com [115.124.30.113]) by sourceware.org (Postfix) with ESMTPS id 378723858D1E for ; Thu, 9 Nov 2023 07:40:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 378723858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 378723858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.113 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699515636; cv=none; b=lNP+V14yCwihjfzlrEO8x8Hp4IyIPrRxHsiCw1XOoPitvmxP/hyr265atkmWyABu1ue3WPesTkCR+egwh/o0nEMdMVGjm7RMYKFRfC3QBNaC6qMJk67o1sosHmqfb+zj+tPMxr9rVkmvB+icgS8zEdMQt1QmKyaCg3uYCLx9EG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699515636; c=relaxed/simple; bh=mOWEqFAb1k3dwKafAA2q7F6c2DSg5ikbMt1/u7T6RPQ=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Lt+3O6W7EuP2P7ZvdvJ8QNYKO98Emxbq/piJUdXbGIebLr90HgkW2w0DGudthIPpCe0H7r7YJ02M795Z0nHb/C3qsSjTSDgvJmDRQ8nOHcGxigQ60aub3/eV+Iz0XfVabrCkw9RpCcFxnH4Q59PB7t6/37TZ9UMnhi4bd+ABkfQ= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R431e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046060;MF=jinma@linux.alibaba.com;NM=1;PH=DS;RN=4;SR=0;TI=SMTPD_---0Vw.l0ez_1699515621; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw.l0ez_1699515621) by smtp.aliyun-inc.com; Thu, 09 Nov 2023 15:40:24 +0800 From: Jin Ma To: gcc-patches@gcc.gnu.org Cc: christoph.muellner@vrull.eu, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH] RISC-V: Fix the illegal operands for the XTheadMemidx extension. Date: Thu, 9 Nov 2023 15:40:08 +0800 Message-Id: <20231109074008.580-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-20.2 required=5.0 tests=BAYES_00,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The pattern "*extend2_bitmanip" and "*zero_extendhi2_bitmanip" in bitmanip.md are similar to the pattern "*th_memidx_bb_extendqi2" and "*th_memidx_bb_zero_extendhi2" in thead.md, which will cause the wrong instruction to be generated and report the following error in binutils: Assembler messages: Error: illegal operands `lb a5,(a0),1,0' In fact, the correct instruction is "th.lbia a5,(a0),1,0". gcc/ChangeLog: * config/riscv/bitmanip.md: Avoid the conflict between zbb and xtheadmemidx in patterns. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadfmemidx-uindex-zbb.c: New test. --- gcc/config/riscv/bitmanip.md | 4 +-- .../riscv/xtheadfmemidx-uindex-zbb.c | 30 +++++++++++++++++++ 2 files changed, 32 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-zbb.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index a9c8275fca7..878395c3ffa 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -290,7 +290,7 @@ (define_insn "*di2" (define_insn "*zero_extendhi2_bitmanip" [(set (match_operand:GPR 0 "register_operand" "=r,r") (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))] - "TARGET_ZBB" + "TARGET_ZBB && !TARGET_XTHEADMEMIDX" "@ zext.h\t%0,%1 lhu\t%0,%1" @@ -301,7 +301,7 @@ (define_insn "*extend2_bitmanip" [(set (match_operand:SUPERQI 0 "register_operand" "=r,r") (sign_extend:SUPERQI (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))] - "TARGET_ZBB" + "TARGET_ZBB && !TARGET_XTHEADMEMIDX" "@ sext.\t%0,%1 l\t%0,%1" diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-zbb.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-zbb.c new file mode 100644 index 00000000000..a05bc220cba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-zbb.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ +/* { dg-options "-march=rv64gc_zbb_xtheadmemidx -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32imafc_zbb_xtheadmemidx -mabi=ilp32f" { target { rv32 } } } */ + +const unsigned char * +read_uleb128(const unsigned char *p, unsigned long *val) +{ + unsigned int shift = 0; + unsigned char byte; + unsigned long result; + + result = 0; + do + { + byte = *p++; + result |= ((unsigned long)byte & 0x7f) << shift; + shift += 7; + } while (byte & 0x80); + + *val = result; + return p; +} + +void test(const unsigned char *p, unsigned long utmp) +{ + p = read_uleb128(p, &utmp); +} + +/* { dg-final { scan-assembler-not {\mlb\ta[0-9],\(a[0-9]\),1,0\M} } } */ base-commit: 04d8a47608dcae7f61805e3566e3a1571b574405 -- 2.17.1