From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id EED723861839 for ; Thu, 9 Nov 2023 08:21:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EED723861839 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org EED723861839 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.20 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699518096; cv=none; b=XGt7VH2IdedDUqnRkHHK7ZVuYFtGPmfKGcomQvmc6YhCM3a3xsd648c7nAnEwtS3iO3VMrkoB2Se9gwvf/6iWSTiF9q0aeiudkFpHbpHJ6gSQu6F1ByW2306uTX2MsYObgbBusaa2HpK515XksAvuEMstWO+cf3qI//MxlPTXHU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699518096; c=relaxed/simple; bh=yZ/LLSbIOvs49PuSCA0rmpp64vh0c+f1ecM1p39dc4g=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=qpvPCbByWC5+Dz/+iW7Gq9GfSEVdgGpylFgVyKlJHLG/tZmlwjTt/nJoxGNA0iReIX7v6wDE3gaolIrlwqgGtrT0/oyldksBQf6xvxL4e1O7LNYB2qnhVut9Hm41i9Xqvl9WCyjQ8hhqNARAMG1ZisCkFJPQ9aD6+2rWTCzyRx8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699518094; x=1731054094; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=yZ/LLSbIOvs49PuSCA0rmpp64vh0c+f1ecM1p39dc4g=; b=m9UnxudY8IMS+GFkiOp2vmTJmi4fAemheF2DjSPxa2urjJ2oi6XbNYws 7HE0eWYR1NAouliK2Y1SRKp4sTli/bXq5Vu6ulP6EbBkqSnC0HAx4XCfj HgAfKZ6AuQnsyQBAyavEYTzrMbbOkzDJV38TJu+g691l/adoon73Z9EDT 64pDz0DBW2xN5Nhk45QAP8fiHLY/7ScLkyc+NVEdQH8153rAkXd1QhgmE yh1vmzZJlPDpHsSH6EOlIIz/kJqQy3hOlRuOw0Y6sJleCLxIRf0j/PfZh 3REIDND9VASWdeluucc2Mgc69V33toE6QGzV5g59LiZN6pthBgxI6bV5n Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="380334375" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="380334375" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2023 00:21:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="792466694" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="792466694" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga008.jf.intel.com with ESMTP; 09 Nov 2023 00:21:24 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 6082D10056F3; Thu, 9 Nov 2023 16:21:23 +0800 (CST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH] Fix wrong code due to vec_merge + pcmp to blendvb splitter. Date: Thu, 9 Nov 2023 16:21:23 +0800 Message-Id: <20231109082123.3120267-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Boostrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready push to trunk. Will test and backport to GCC13/GCC12 release branch. gcc/ChangeLog: PR target/112443 * config/i386/sse.md (*avx2_pcmp3_4): Fix swap condition from LT to GE since there's not in the pattern. (*avx2_pcmp3_5): Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/pr112443.C: New test. --- gcc/config/i386/sse.md | 4 +- gcc/testsuite/g++.target/i386/pr112443.C | 108 +++++++++++++++++++++++ 2 files changed, 110 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/g++.target/i386/pr112443.C diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 33198756bb0..9eefe9ed45b 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17082,7 +17082,7 @@ (define_insn_and_split "*avx2_pcmp3_4" (match_dup 4))] UNSPEC_BLENDV))] { - if (INTVAL (operands[5]) == 1) + if (INTVAL (operands[5]) == 5) std::swap (operands[1], operands[2]); operands[3] = gen_lowpart (mode, operands[3]); }) @@ -17112,7 +17112,7 @@ (define_insn_and_split "*avx2_pcmp3_5" (match_dup 4))] UNSPEC_BLENDV))] { - if (INTVAL (operands[5]) == 1) + if (INTVAL (operands[5]) == 5) std::swap (operands[1], operands[2]); }) diff --git a/gcc/testsuite/g++.target/i386/pr112443.C b/gcc/testsuite/g++.target/i386/pr112443.C new file mode 100644 index 00000000000..ebfa9b4a753 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/pr112443.C @@ -0,0 +1,108 @@ +/* { dg-do run } */ +/* { dg-require-effective-target avx512bw } */ +/* { dg-require-effective-target avx512vl } */ +/* { dg-options "-O2 -std=c++17 -mavx512bw -mavx512vl" } */ + +#include +#include +#include +#include + +#define AVX512BW +#define AVX512VL + +#include "avx512f-helper.h" + +struct TensorIteratorBase{ + char* in; + char* out; + + void for_each(std::function loop){ + loop(out, in, 32); + } +}; + +class Vectorized { +protected: + __m256i values; + + static inline __m256i invert(const __m256i& v) { + const auto ones = _mm256_set1_epi64x(-1); + return _mm256_xor_si256(ones, v); + } +public: + operator __m256i() const { + return values; + } + + static constexpr int size() { + return 32; + } + + Vectorized() {} + Vectorized(__m256i v) : values(v) {} + Vectorized(uint8_t v) { values = _mm256_set1_epi8(v); } + static Vectorized blendv(const Vectorized& a, const Vectorized& b, + const Vectorized& mask) { + return _mm256_blendv_epi8(a, b, mask); + } + static Vectorized loadu(const void* ptr) { + return _mm256_loadu_si256(reinterpret_cast(ptr)); + } + void store(void* ptr) const { + _mm256_storeu_si256(reinterpret_cast<__m256i*>(ptr), values); + } + + Vectorized operator<(const Vectorized& other) const { + __m256i max = _mm256_max_epu8(values, other); + return invert(_mm256_cmpeq_epi8(max, values)); + } + Vectorized operator-(const Vectorized& b) { + return _mm256_sub_epi8(values, b); + } +}; + +std::ostream& operator<<(std::ostream& stream, const Vectorized& vec) { + uint8_t buf[Vectorized::size()]; + vec.store(buf); + stream << "vec["; + for (int i = 0; i != Vectorized::size(); i++) { + if (i != 0) + stream << ", "; + stream << buf[i]*1; + } + stream << "]"; + return stream; +} + +void run(TensorIteratorBase iter){ + Vectorized zero_vec(0); + Vectorized one_vec(1); + + iter.for_each([=](char* out, char* in, int64_t size) { + for (int64_t i = 0; i <= size - Vectorized::size(); i += Vectorized::size()) { + auto self_vec = Vectorized::loadu(in + i); + auto left = Vectorized::blendv(zero_vec, one_vec, zero_vec < self_vec); + auto right = Vectorized::blendv(zero_vec, one_vec, self_vec < zero_vec); + auto outv = left - right; + outv.store(out + i); + } + }); +} + +void +test_256 (){ + char in[32]; + char out[32]; + for(auto& x: in) x = 1; + run(TensorIteratorBase{in, out}); + Vectorized::loadu (out); + for (int i = 0; i != 32; i++) + if (out[i] != 1) + __builtin_abort (); +} + +void +test_128 () +{ +} -- 2.31.1