From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by sourceware.org (Postfix) with ESMTPS id 95D1F3858D33 for ; Thu, 9 Nov 2023 12:42:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 95D1F3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 95D1F3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::329 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699533754; cv=none; b=dBbgEfK+6m/OEsZGF3FT6Nt0xGYjjEiMyaoJj3beuOqdI8shRZ/3t4etlZlZRBnOi0tOHjcDXIUqQo5u5m4ebGIhAqFYuXtGiKnAAqI+o4DkrRn6RUdbhNW7rRw8B/c0c6kQI/foXAZSjMF4ToDgtBJviq+ZKe+5oJZkP1CodA8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699533754; c=relaxed/simple; bh=dOxiiisgCcxDB9awtz2gjj9lp2WXHd4mcxF41q/9zs4=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=qYN1R5tA177hJGhsJYznnXJXeFnma5QEtLNShJNWfZWeS6GHcUaM4NEoP9bDBHJ83VgX8p3K5TZs0rujOxcZh5FqDZMIF8/gzZOzc+kDC0x0sAE+PsXkyUxvJN0o95DeFolumFhe9toKRf2HRZKXYDKMqlUw42PGOrbH13w+Xr4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4083f613272so5952385e9.1 for ; Thu, 09 Nov 2023 04:42:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1699533751; x=1700138551; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=9JzqyfujLyqY1B4/dqYPnQF1fE3yxjWdtZSbQfcmMEI=; b=agpKIc63SmzDxf7Zh2ifmdIs4gdLl96ugv6ikkJ8n4ueT8R2RsPdO5lrP9+VOfRS40 qa0uvc2+M/qUgLMNfnCaYx9u0NCHPtEaUixLfABOseMYw79rn4zcQl/AsbzrEiDZkZKn NdhV2Cfs0FdXIzUAU1ncgPhX1F+ffnbZ7PunRLbTDKD3E6+yDrDA3uKz9c9PPb8TIzcH tzO07uA7WQ+SDLoQduUjmgkK0pMBclOmgq9Ccau8Sc4bJr1By0GJ66vf2eDmJX4hM2X7 fSjCziRZ8RlD3n8ozOepQuuLdTEjup4gCLOuoBvCI7YbCsD312R9xLnyVjTbG29upljo 2hHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699533751; x=1700138551; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9JzqyfujLyqY1B4/dqYPnQF1fE3yxjWdtZSbQfcmMEI=; b=O0s8taRZYRgDPv33OL+TSLoyfcSd1xUquP17dwayQsMelwjzuI7QzfesdGpJJWaD9R Qwhll/+u1TjA5waUHVYfpCBV8iKjCrzxMzJ+up8eVcaEiNS0fAFHC8SLq6x0kvpj9/o8 Nz0/PmEAWRH45JFP6S5yIu/EwVmg2yMjaylHGOaQiokYMDQkrhI/Jb2xs5BmAoEw2u7Y FiUnTGH6coi/l+vctQYwBQdfycxNSnuWASLL9WZGHKbqmwchgvYb2f91Pw7cWUr6WD35 JunVuzNmee8FVhpZw9ksbVCfSsGwutKK9ifBA/wqBVaxKEaHEDo5aIzj2l07qTI1GDH5 9DUQ== X-Gm-Message-State: AOJu0YwBrTBvOV+qw1o5ZvirRHYC3eZQ6C6xIkNoP0Et8CHsFn0ek75r jwHn2zlqV1UF4Y3+3GX5EsiAjmRrkRlEg/BrfbyOhg== X-Google-Smtp-Source: AGHT+IHt6+WQVboJ51RAiyUBmNyevDhIR0epsADEwkxVzN5P4cCrUmxIRXAiqZnLTtwVplltLBZCqA== X-Received: by 2002:a05:600c:4449:b0:409:6e0e:e948 with SMTP id v9-20020a05600c444900b004096e0ee948mr4330956wmn.1.1699533750800; Thu, 09 Nov 2023 04:42:30 -0800 (PST) Received: from troughton.sou.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id o7-20020a05600c4fc700b004064ac107cfsm2004578wmq.39.2023.11.09.04.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 04:42:30 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH 0/1] RISC-V: Support CORE-V XCVMEM extension Date: Thu, 9 Nov 2023 12:42:18 +0000 Message-Id: <20231109124219.966619-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch series presents the comprehensive implementation of the MEM extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin RISC-V: Add support for XCVmem extension in CV32E40P gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 28 +++ gcc/config/riscv/corev.md | 227 ++++++++++++++++++ gcc/config/riscv/predicates.md | 20 +- gcc/config/riscv/riscv-protos.h | 12 +- gcc/config/riscv/riscv.cc | 48 +++- gcc/config/riscv/riscv.h | 6 +- gcc/config/riscv/riscv.md | 46 ++-- gcc/config/riscv/riscv.opt | 2 + gcc/doc/sourcebuild.texi | 3 + .../gcc.target/riscv/cv-mem-lb-compile-1.c | 23 ++ .../gcc.target/riscv/cv-mem-lb-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lb-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lbu-compile-1.c | 23 ++ .../gcc.target/riscv/cv-mem-lbu-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lbu-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lh-compile-1.c | 23 ++ .../gcc.target/riscv/cv-mem-lh-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lh-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lhu-compile-1.c | 23 ++ .../gcc.target/riscv/cv-mem-lhu-compile-2.c | 24 ++ .../gcc.target/riscv/cv-mem-lhu-compile-3.c | 16 ++ .../gcc.target/riscv/cv-mem-lw-compile-1.c | 38 +++ .../gcc.target/riscv/cv-mem-lw-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-lw-compile-3.c | 22 ++ .../riscv/cv-mem-operand-compile-1.c | 19 ++ .../riscv/cv-mem-operand-compile-2.c | 20 ++ .../riscv/cv-mem-operand-compile-3.c | 28 +++ .../riscv/cv-mem-operand-compile-4.c | 21 ++ .../riscv/cv-mem-operand-compile-5.c | 25 ++ .../riscv/cv-mem-operand-compile-6.c | 21 ++ .../riscv/cv-mem-operand-compile-7.c | 24 ++ .../riscv/cv-mem-operand-compile-8.c | 18 ++ .../gcc.target/riscv/cv-mem-sb-compile-1.c | 36 +++ .../gcc.target/riscv/cv-mem-sb-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-sb-compile-3.c | 30 +++ .../gcc.target/riscv/cv-mem-sh-compile-1.c | 36 +++ .../gcc.target/riscv/cv-mem-sh-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-sh-compile-3.c | 30 +++ .../gcc.target/riscv/cv-mem-sw-compile-1.c | 36 +++ .../gcc.target/riscv/cv-mem-sw-compile-2.c | 38 +++ .../gcc.target/riscv/cv-mem-sw-compile-3.c | 30 +++ gcc/testsuite/lib/target-supports.exp | 14 ++ 43 files changed, 1216 insertions(+), 30 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lb-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lbu-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lh-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lhu-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-lw-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-operand-compile-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sb-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sh-compile-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cv-mem-sw-compile-3.c -- 2.34.1