From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id E30F03858D38 for ; Fri, 10 Nov 2023 01:42:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E30F03858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E30F03858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.151 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699580525; cv=none; b=F5ViMw2N8YEr4EVFMsvzvcuQTfGyUDZzYdVNeen3yzC91D+ezoWr2OvSeGTCiJreAyUWzS1FTm25do3mYt343lUXAZpVKqdgoB12QX3QPHCdBJUgcwTplFGH9Inc6gaBHNhaKEYKphV0x8ZUDewGP+Wa6+IcHXYHXq0T2BUaWQI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699580525; c=relaxed/simple; bh=7DhNn7adVYfb0Nv8QwezKR7CIFMKbDIRYh8VYidwomo=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=ko6BR0ak8A6uUlLX8RWzR2Cu7NqwMA6sugR2GwzGO0wadEUO6sxyPCJs0srngTC1O4xQBnXOzoW3WbTKRbYKq7VLKeBg/3uLxqg3VQLsSn1UHQti6lL3tB2nEfWOTG6R+YFwEuH7KY00zUbXpoe7DLFi81ayQZyMsCBUrkMyRuA= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699580523; x=1731116523; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=7DhNn7adVYfb0Nv8QwezKR7CIFMKbDIRYh8VYidwomo=; b=CH4x4WQBY8mR5bYeuBRhd1/9xGhMybDJqDFlmO3O07BbFdi4zNPgAipI ucQuTmSf+dXOItbNK0bu2pClrqDOoY1vAmq0N1W+zoUqQGxPaOFtmZ/8b 6VSgLuujiN7z186uDHwJozpjp7GrtSyMOKySyL9g5U2SW+ZotloIp2iV4 YauMHPLtkoXFfPLln2UyhRgVuTOt4DXazNfdXN/KaRcoWSCwjOooD3h0t wHISgsGHyoKWIBIDYcg6lXBbtr31LurDYWc1TId+me/dwLiKtO46GEW7P NE2bIbifDgtq66CY0dJ9lFjuWFQfBZApApr09drytWD9LiZnrqEmBM9j/ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10889"; a="370320485" X-IronPort-AV: E=Sophos;i="6.03,291,1694761200"; d="scan'208";a="370320485" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2023 17:42:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,291,1694761200"; d="scan'208";a="4895894" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa002.fm.intel.com with ESMTP; 09 Nov 2023 17:42:01 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 7438610056EF; Fri, 10 Nov 2023 09:42:00 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [RFC] Intel AVX10.1 Compiler Design and Support Date: Fri, 10 Nov 2023 09:41:57 +0800 Message-Id: <20231110014158.371690-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi all, This RFC patch aims to add AVX10.1 options. After we added -m[no-]evex512 support, it makes a lot easier to add them comparing to the August version. Detail for AVX10 is shown below: Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification It describes the Intel Advanced Vector Extensions 10 Instruction Set Architecture. https://cdrdv2.intel.com/v1/dl/getContent/784267 The Converged Vector ISA: Intel Advanced Vector Extensions 10 Technical Paper It provides introductory information regarding the converged vector ISA: Intel Advanced Vector Extensions 10. https://cdrdv2.intel.com/v1/dl/getContent/784343 Our proposal is to take AVX10.1-256 and AVX10.1-512 as two "virtual" ISAs in the compiler. AVX10.1-512 will imply AVX10.1-256. They will not enable anything at first. At the end of the option handling, we will check whether the two bits are set. If AVX10.1-256 is set, we will set the AVX512 related ISA bits. AVX10.1-512 will further set EVEX512 ISA bit. It means that AVX10 options will be separated from the existing AVX512 and the newly added -m[no-]evex512 options. AVX10 and AVX512 options will control (enable/disable/set vector size) the AVX512 features underneath independently. If there’s potential overlap or conflict between AVX10 and AVX512 options, some rules are provided to define the behavior, which will be described below. avx10.1 option will be provided as an alias of avx10.1-256. In the future, the AVX10 options will imply like this: AVX10.1-256 <---- AVX10.1-512 ^ ^ | | AVX10.2-256 <---- AVX10.2-512 ^ ^ | | AVX10.3-256 <---- AVX10.3-512 ^ ^ | | Each of them will have its own option to enable/disabled corresponding features. The alias avx10.x will also be provided. As mentioned in August version RFC, since we lean towards the adoption of AVX10 instead of AVX512 from now on, we don’t recommend users to combine the AVX10 and legacy AVX512 options. However, we would like to introduce some simple rules for user when it comes to combination. 1. Enabling AVX10 and AVX512 at the same command line with different vector size will lead to a warning message. The behavior of the compiler will be enabling AVX10 with longer, i.e., 512 bit vector size. If the vector sizes are the same (e.g. -mavx10.1-256 -mavx512f -mno-evex512, -mavx10.1-512 -mavx512f), it will be valid with the corresponding vector size. 2. -mno-avx10.1 option can’t disable any features enabled by AVX512 options or impact the vector size, and vice versa. The compiler will emit warnings if necessary. For the auto dispatch support including function multi versioning, function attribute usage, the behavior will be identical to compiler options. If you have any questions, feel free to ask in this thread. Thx, Haochen