From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 614B63858D28 for ; Sun, 12 Nov 2023 09:59:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 614B63858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 614B63858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=13.245.218.24 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699783170; cv=none; b=SS5XtKShew3KxQLwA+VFyR8p5jpEFt9W9UehiInzzXgd8HXtqhG6fLv6cmZBaY7og5tUhoZ+ceC107gPFlIkMHLegZmWZKIysX9kzRsGJ/9bNnB2QvoOkv/Y5rslqQP4g9d61QzltpNbL+wqLY36qGrJzlr8XgXxj0Hdy04hQlE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699783170; c=relaxed/simple; bh=iye3d0n9sW9N+o9/WQbNWrWNkyaFoca8WiFpbabmWZE=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=urjiul1WJfdUqFkDTiCaoe3cX+68Ypl3D/s8QAUtTYgwI241kHU1n4/c+hauKjJYcG825jtG8snbZyUBnbYXhVwzK51FePUyv2I/yBVwbLfKVTEczFR7B9yRiAZh2fM62Up2+rdgN19KHkq2QHO3SS7hx/1vYrQH7EEXtY5bzLw= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp83t1699783156tdlimkeu Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 12 Nov 2023 17:59:15 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: cvpDInk2tjWH+HZrQGrGWPhCmqHuRMhaC3f7+jT10whSajMYGeev1JYwW1a5Z dkfb1/0VZpGlhUveCppIGNRxn6Xo+3zT/bzkErDdWf6bDRMG5Kx21HRCpNgfKiwde5cO13d ERzsw3uenuxtZBotKtIwZRDORPLOI8EFYn6zh5Flm3DXKpp8G4sb0mPVnIT9PPhRyf9wHnf hOMqnRQhKBMMcEG3tUQQlhT+RNTeWc/Wra/eAnmuQ6aY1Y9eZpwMtTqxR3Fr89z62ARZKAA JHsq0OIRIUxyaUqeXujRBVMQqjy6qj1g5XJGbke1yUBGttM9BDsqXwByLdrvsBNs5JDKJgB m9IaO7d9z1/QSddQ/wgFmDScnjGdEEMx3WfnEuIAM4T5dUEtq+KdfFLVUPQ+t74PkqXDq+D X-QQ-GoodBg: 2 X-BIZMAIL-ID: 10247378412573133933 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: vmakarov@redhat.com, richard.sandiford@arm.com, juzhe.zhong@rivai.ai, lehua.ding@rivai.ai Subject: [PATCH V2 5/7] ira: Add all nregs >= 2 pseudos to tracke subreg list Date: Sun, 12 Nov 2023 17:58:56 +0800 Message-Id: <20231112095858.3669003-6-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20231112095858.3669003-1-lehua.ding@rivai.ai> References: <20231112095858.3669003-1-lehua.ding@rivai.ai> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch relax the subreg track capability to all subreg registers. gcc/ChangeLog: * ira-build.cc (get_reg_unit_size): New. (has_same_nregs): New. (ira_set_allocno_class): Adjust. --- gcc/ira-build.cc | 41 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 5 deletions(-) diff --git a/gcc/ira-build.cc b/gcc/ira-build.cc index 13f0f7336ed..f88aeeeeaef 100644 --- a/gcc/ira-build.cc +++ b/gcc/ira-build.cc @@ -607,6 +607,37 @@ ira_create_allocno (int regno, bool cap_p, return a; } +/* Return single register size of allocno A. */ +static poly_int64 +get_reg_unit_size (ira_allocno_t a) +{ + enum reg_class aclass = ALLOCNO_CLASS (a); + gcc_assert (aclass != NO_REGS); + machine_mode mode = ALLOCNO_MODE (a); + int nregs = ALLOCNO_NREGS (a); + poly_int64 block_size = REGMODE_NATURAL_SIZE (mode); + int nblocks = get_nblocks (mode); + gcc_assert (nblocks % nregs == 0); + return block_size * (nblocks / nregs); +} + +/* Return true if TARGET_CLASS_MAX_NREGS and TARGET_HARD_REGNO_NREGS results is + same. It should be noted that some targets may not implement these two very + uniformly, and need to be debugged step by step. For example, in V3x1DI mode + in AArch64, TARGET_CLASS_MAX_NREGS returns 2 but TARGET_HARD_REGNO_NREGS + returns 3. They are in conflict and need to be repaired in the Hook of + AArch64. */ +static bool +has_same_nregs (ira_allocno_t a) +{ + for (int i = 0; i < FIRST_PSEUDO_REGISTER; i++) + if (REGNO_REG_CLASS (i) != NO_REGS + && reg_class_subset_p (REGNO_REG_CLASS (i), ALLOCNO_CLASS (a)) + && ALLOCNO_NREGS (a) != hard_regno_nregs (i, ALLOCNO_MODE (a))) + return false; + return true; +} + /* Set up register class for A and update its conflict hard registers. */ void @@ -624,12 +655,12 @@ ira_set_allocno_class (ira_allocno_t a, enum reg_class aclass) if (aclass == NO_REGS) return; - /* SET the unit_size of one register. */ - machine_mode mode = ALLOCNO_MODE (a); - int nregs = ira_reg_class_max_nregs[aclass][mode]; - if (nregs == 2 && maybe_eq (GET_MODE_SIZE (mode), nregs * UNITS_PER_WORD)) + gcc_assert (!ALLOCNO_TRACK_SUBREG_P (a)); + /* Set unit size and track_subreg_p flag for pseudo which need occupied multi + hard regs. */ + if (ALLOCNO_NREGS (a) > 1 && has_same_nregs (a)) { - ALLOCNO_UNIT_SIZE (a) = UNITS_PER_WORD; + ALLOCNO_UNIT_SIZE (a) = get_reg_unit_size (a); ALLOCNO_TRACK_SUBREG_P (a) = true; return; } -- 2.36.3