From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by sourceware.org (Postfix) with ESMTPS id E5D80385559E for ; Mon, 13 Nov 2023 13:35:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E5D80385559E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E5D80385559E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::132 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699882551; cv=none; b=Q6AwUDPkzX1i2PMvVZ/VrlNb6lXj8BWj6zHhG3Xdht5U5Lg2fHRole38MNeFZ0ytcWtSng3Z7Gt8Z0ytP4NUoEGfVBTrIHBotUWXNI3KQ36cL849gSbvX4Ni49GxIbWQ13MXhBU0QnVR9Z1DFREd0ZYkSnX5KkxAGxiP69rj2Eo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699882551; c=relaxed/simple; bh=c4g4L1HVhcEx4voUgNdEp7OXmXsxQctK1+PTGIAwy0I=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=BVB77fVQGCrzjWlX4XeklYknloylK1tgJ8gG9ihmChyOBskB3020aGRtyUOTKG42Rw4oQh8IcJrso8cIjTcPt6nh4C1vuVWa+fOvrJKctZNpAFfANpPuLM1namsfLgNFKVuhAqCWKXiYYXTmfozMJn3XF6baAMgc6LIyTPb0uMs= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-50930f126b1so5802679e87.3 for ; Mon, 13 Nov 2023 05:35:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1699882547; x=1700487347; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gdagdi7iMIzKnwsj7w7AjThQJGs4qjfnY9NtezQreuc=; b=DJ4smvZVojUMHfPIz9OHFgd9sljnusCTJvAFG6hICDEriE2DlRopZi1GmvU8JXfI5b VZVs4QYn4gAPL29bxY974+pKJ8hI58gxjUXznYEVAJ33PBbPIR1ERVoVi4wiFccSBm/F C+HGVQjS6HJFuYmBUmkS1l8+Wo19u9FOvLO6tIEaCnDese+u7+TFL9vnTp+Nz6IohxcN IQ+cXAWIw8b80+n6O3vVUXWbP3CHpgXiiyj0OZNo9Z7tSfBF7gbQPkXG3uzK33MxQ/iE XnIBKH428JUPmcRDvvFvXE1xeEQQOf44mk8wDX/R248UMQGPGmLYaiN02LXdkNifN7Fy T0tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699882547; x=1700487347; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gdagdi7iMIzKnwsj7w7AjThQJGs4qjfnY9NtezQreuc=; b=N+kLxUOFRDZfTcHNvL8E1ZAGKg2VgpqGtkIfoACzRL+oBp6xV1rOxzxdOfe49uh7gC 6oXPqPUqEFSap7xRpfK3CcJn1h7TwoGmfClNaKNPtNr26QYXmnJCvvJ0vezT5vdxx6i4 0FOQDcBznMaSkp+XytAX5LAEpZB3dlAzFb4uELJIaawtToGMVxe1y8IpcbX7GIRtIWfs sD2EoST5sBTtZE+ICp9PgDA0JlMbK4ILLUVz4f2akhlDArQRJTfBGy2z9/3OIKFKjxZH hPaUvCQzuOr3UeU97AAtLrTQXr/H8HKlSxN+y3xKWDfq8D1S1TvVllF2KazAYaPkrTgF pMWQ== X-Gm-Message-State: AOJu0YwCJ3+SYzWZR2DRQBj/+cDd9tnJrq/7tdjHS0Su1pdO4oUJHh1E jMS0hqKTwI/kyRjkFCx3UTsd6Jdo8ZGFVxt7QMbS0w== X-Google-Smtp-Source: AGHT+IH5oguTCJDl+YUW0qD/XHZAJpX6jL28z4r0u0y5JxFSqz7WigcC9cI25McMIGoOKrVjbrbsWg== X-Received: by 2002:a05:6512:3a8c:b0:50a:6fbe:fec4 with SMTP id q12-20020a0565123a8c00b0050a6fbefec4mr5595258lfu.33.1699882547361; Mon, 13 Nov 2023 05:35:47 -0800 (PST) Received: from troughton.sou.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id d13-20020a056000114d00b003140f47224csm5420493wrx.15.2023.11.13.05.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 05:35:46 -0800 (PST) From: Mary Bennett To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors Date: Mon, 13 Nov 2023 13:35:29 +0000 Message-Id: <20231113133530.1727444-3-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231113133530.1727444-1-mary.bennett@embecosm.com> References: <20231108110914.2710021-1-mary.bennett@embecosm.com> <20231113133530.1727444-1-mary.bennett@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gcc/ChangeLog: * config/riscv/constraints.md: CVP2 -> CV_alu_pow2. * config/riscv/corev.md: Likewise. --- gcc/config/riscv/constraints.md | 15 ++++++++------- gcc/config/riscv/corev.md | 4 ++-- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 68be4515c04..2711efe68c5 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -151,13 +151,6 @@ (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS" "An integer register for ZFA or XTheadFmv.") -;; CORE-V Constraints -(define_constraint "CVP2" - "Checking for CORE-V ALU clip if ival plus 1 is a power of 2" - (and (match_code "const_int") - (and (match_test "IN_RANGE (ival, 0, 1073741823)") - (match_test "exact_log2 (ival + 1) != -1")))) - ;; Vector constraints. (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS" @@ -246,3 +239,11 @@ A MEM with a valid address for th.[l|s]*ur* instructions." (and (match_code "mem") (match_test "th_memidx_legitimate_index_p (op, true)"))) + +;; CORE-V Constraints +(define_constraint "CV_alu_pow2" + "@internal + Checking for CORE-V ALU clip if ival plus 1 is a power of 2" + (and (match_code "const_int") + (and (match_test "IN_RANGE (ival, 0, 1073741823)") + (match_test "exact_log2 (ival + 1) != -1")))) diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md index c7a2ba07bcc..92bf0b5d6a6 100644 --- a/gcc/config/riscv/corev.md +++ b/gcc/config/riscv/corev.md @@ -516,7 +516,7 @@ (define_insn "riscv_cv_alu_clip" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIP))] "TARGET_XCVALU && !TARGET_64BIT" @@ -529,7 +529,7 @@ (define_insn "riscv_cv_alu_clipu" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")] + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")] UNSPEC_CV_ALU_CLIPU))] "TARGET_XCVALU && !TARGET_64BIT" -- 2.34.1