From: Hongyu Wang <hongyu.wang@intel.com>
To: gcc-patches@gcc.gnu.org
Cc: ubizjak@gmail.com, hongtao.liu@intel.com,
Kong Lingling <lingling.kong@intel.com>
Subject: [PATCH 09/16] [APX NDD] Support APX NDD for not insn
Date: Wed, 15 Nov 2023 17:46:58 +0800 [thread overview]
Message-ID: <20231115094705.3976553-10-hongyu.wang@intel.com> (raw)
In-Reply-To: <20231115094705.3976553-1-hongyu.wang@intel.com>
From: Kong Lingling <lingling.kong@intel.com>
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_can_use_ndd_p): Add NOT
support.
* config/i386/i386.md (one_cmpl<mode>2): Add NDD constraints, adjust
output template.
(*one_cmpl<mode>2_1): Likewise.
(*one_cmplqi2_1): Likewise.
(*one_cmpl<dwi>2_doubleword): Likewise.
(*one_cmplsi2_1_zext): Likewise.
(*one_cmpl<mode>2_2): Likewise.
(*one_cmplsi2_2_zext): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-ndd.c: Add not test.
---
gcc/config/i386/i386-expand.cc | 1 +
gcc/config/i386/i386.md | 73 +++++++++++++++----------
gcc/testsuite/gcc.target/i386/apx-ndd.c | 11 ++++
3 files changed, 55 insertions(+), 30 deletions(-)
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 995cc792c5f..be77ba4a476 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -1272,6 +1272,7 @@ bool ix86_can_use_ndd_p (enum rtx_code code)
case PLUS:
case MINUS:
case NEG:
+ case NOT:
return true;
default:
return false;
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 8ba524e9e44..9758e4e5144 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -13673,64 +13673,73 @@ (define_expand "one_cmpl<mode>2"
[(set (match_operand:SDWIM 0 "nonimmediate_operand")
(not:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")))]
""
- "ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;")
+ "ix86_expand_unary_operator (NOT, <MODE>mode, operands,
+ ix86_can_use_ndd_p (NOT)); DONE;")
(define_insn_and_split "*one_cmpl<dwi>2_doubleword"
- [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro")
- (not:<DWI> (match_operand:<DWI> 1 "nonimmediate_operand" "0")))]
- "ix86_unary_operator_ok (NOT, <DWI>mode, operands)"
+ [(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r")
+ (not:<DWI> (match_operand:<DWI> 1 "nonimmediate_operand" "0,ro")))]
+ "ix86_unary_operator_ok (NOT, <DWI>mode, operands,
+ ix86_can_use_ndd_p (NOT))"
"#"
"&& reload_completed"
[(set (match_dup 0)
(not:DWIH (match_dup 1)))
(set (match_dup 2)
(not:DWIH (match_dup 3)))]
- "split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[2]);")
+ "split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[2]);"
+ [(set_attr "isa" "*,apx_ndd")])
(define_insn "*one_cmpl<mode>2_1"
- [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,?k")
- (not:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "0,k")))]
- "ix86_unary_operator_ok (NOT, <MODE>mode, operands)"
+ [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,r,?k")
+ (not:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "0,rm,k")))]
+ "ix86_unary_operator_ok (NOT, <MODE>mode, operands,
+ ix86_can_use_ndd_p (NOT))"
"@
not{<imodesuffix>}\t%0
+ not{<imodesuffix>}\t{%1, %0|%0, %1}
#"
- [(set_attr "isa" "*,<kmov_isa>")
- (set_attr "type" "negnot,msklog")
+ [(set_attr "isa" "*,apx_ndd,<kmov_isa>")
+ (set_attr "type" "negnot,negnot,msklog")
(set_attr "mode" "<MODE>")])
(define_insn "*one_cmplsi2_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,?k")
+ [(set (match_operand:DI 0 "register_operand" "=r,r,?k")
(zero_extend:DI
- (not:SI (match_operand:SI 1 "register_operand" "0,k"))))]
- "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
+ (not:SI (match_operand:SI 1 "register_operand" "0,r,k"))))]
+ "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands,
+ ix86_can_use_ndd_p (NOT))"
"@
not{l}\t%k0
+ not{l}\t{%k1, %k0|%k0, %k1}
#"
- [(set_attr "isa" "x64,avx512bw_512")
- (set_attr "type" "negnot,msklog")
- (set_attr "mode" "SI,SI")])
+ [(set_attr "isa" "x64,apx_ndd,avx512bw_512")
+ (set_attr "type" "negnot,negnot,msklog")
+ (set_attr "mode" "SI,SI,SI")])
(define_insn "*one_cmplqi2_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,?k")
- (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,k")))]
- "ix86_unary_operator_ok (NOT, QImode, operands)"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r,?k")
+ (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,rm,k")))]
+ "ix86_unary_operator_ok (NOT, QImode, operands,
+ ix86_can_use_ndd_p (NOT))"
"@
not{b}\t%0
not{l}\t%k0
+ not{l}\t{%k1, %k0|%k0, %k1}
#"
- [(set_attr "isa" "*,*,avx512f")
- (set_attr "type" "negnot,negnot,msklog")
+ [(set_attr "isa" "*,*,apx_ndd,avx512f")
+ (set_attr "type" "negnot,negnot,negnot,msklog")
(set (attr "mode")
- (cond [(eq_attr "alternative" "1")
+ (cond [(eq_attr "alternative" "1,2")
(const_string "SI")
- (and (eq_attr "alternative" "2")
+ (and (eq_attr "alternative" "3")
(match_test "!TARGET_AVX512DQ"))
(const_string "HI")
]
(const_string "QI")))
;; Potential partial reg stall on alternative 1.
(set (attr "preferred_for_speed")
- (cond [(eq_attr "alternative" "1")
+ (cond [(eq_attr "alternative" "1,2")
(symbol_ref "!TARGET_PARTIAL_REG_STALL")]
(symbol_ref "true")))])
@@ -13753,14 +13762,16 @@ (define_insn_and_split "*one_cmpl<mode>_1_slp"
(define_insn "*one_cmpl<mode>2_2"
[(set (reg FLAGS_REG)
- (compare (not:SWI (match_operand:SWI 1 "nonimmediate_operand" "0"))
+ (compare (not:SWI (match_operand:SWI 1 "nonimmediate_operand" "0,rm"))
(const_int 0)))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,r")
(not:SWI (match_dup 1)))]
"ix86_match_ccmode (insn, CCNOmode)
- && ix86_unary_operator_ok (NOT, <MODE>mode, operands)"
+ && ix86_unary_operator_ok (NOT, <MODE>mode, operands,
+ ix86_can_use_ndd_p (NOT))"
"#"
[(set_attr "type" "alu1")
+ (set_attr "isa" "*,apx_ndd")
(set_attr "mode" "<MODE>")])
(define_split
@@ -13779,14 +13790,16 @@ (define_split
(define_insn "*one_cmplsi2_2_zext"
[(set (reg FLAGS_REG)
- (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
+ (compare (not:SI (match_operand:SI 1 "register_operand" "0,r"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
+ (set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (not:SI (match_dup 1))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
- && ix86_unary_operator_ok (NOT, SImode, operands)"
+ && ix86_unary_operator_ok (NOT, SImode, operands,
+ ix86_can_use_ndd_p (NOT))"
"#"
[(set_attr "type" "alu1")
+ (set_attr "isa" "*,apx_ndd")
(set_attr "mode" "SI")])
(define_split
diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd.c b/gcc/testsuite/gcc.target/i386/apx-ndd.c
index 18b423258ea..9af72d1a46d 100644
--- a/gcc/testsuite/gcc.target/i386/apx-ndd.c
+++ b/gcc/testsuite/gcc.target/i386/apx-ndd.c
@@ -76,6 +76,15 @@ F (int, neg, -)
F1 (int, neg, -)
F (long, neg, -)
F1 (long, neg, -)
+
+F (char, not, ~)
+F1 (char, not, ~)
+F (short, not, ~)
+F1 (short, not, ~)
+F (int, not, ~)
+F1 (int, not, ~)
+F (long, not, ~)
+F1 (long, not, ~)
/* { dg-final { scan-assembler-times "add(?:l|w|q)\[^\n\r]*1, \\(%rdi\\), %(?:|r|e)ax" 4 } } */
/* { dg-final { scan-assembler-times "lea(?:l|q)\[^\n\r]\\(%r(?:d|s)i,%r(?:d|s)i\\), %(?:|r|e)ax" 4 } } */
/* { dg-final { scan-assembler-times "add(?:l|w|q)\[^\n\r]%(?:|r|e)si, \\(%rdi\\), %(?:|r|e)ax" 4 } } */
@@ -84,3 +93,5 @@ F1 (long, neg, -)
/* { dg-final { scan-assembler-times "negb\[^\n\r]\\(%rdi\\), %(?:|r|e)al" 1 } } */
/* { dg-final { scan-assembler-times "neg(?:l|w|q)\[^\n\r]\\(%rdi\\), %(?:|r|e)ax" 3 } } */
/* { dg-final { scan-assembler-times "neg(?:l|w|q)\[^\n\r]%(?:|r|e)di, %(?:|r|e)ax" 4 } } */
+/* { dg-final { scan-assembler-times "not(?:l|w|q)\[^\n\r]\\(%rdi\\), %(?:|r|e)ax" 4 } } */
+/* { dg-final { scan-assembler-times "not(?:l|w|q)\[^\n\r]%(?:|r|e)di, %(?:|r|e)ax" 4 } } */
--
2.31.1
next prev parent reply other threads:[~2023-11-15 9:47 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-15 9:46 [PATCH 00/16] Support Intel APX NDD Hongyu Wang
2023-11-15 9:46 ` [PATCH 01/16] [APX NDD] Support Intel APX NDD for legacy add insn Hongyu Wang
2023-11-15 9:46 ` [PATCH 02/16] [APX NDD] Restrict TImode register usage when NDD enabled Hongyu Wang
2023-11-15 9:46 ` [PATCH 03/16] [APX NDD] Support APX NDD for optimization patterns of add Hongyu Wang
2023-11-15 9:46 ` [PATCH 04/16] [APX NDD] Disable seg_prefixed memory usage for NDD add Hongyu Wang
2023-11-15 9:46 ` [PATCH 05/16] [APX NDD] Support APX NDD for adc insns Hongyu Wang
2023-11-15 9:46 ` [PATCH 06/16] [APX NDD] Support APX NDD for sub insns Hongyu Wang
2023-11-15 9:46 ` [PATCH 07/16] [APX NDD] Support APX NDD for sbb insn Hongyu Wang
2023-11-15 9:46 ` [PATCH 08/16] [APX NDD] Support APX NDD for neg insn Hongyu Wang
2023-11-15 9:46 ` Hongyu Wang [this message]
2023-11-15 9:46 ` [PATCH 10/16] [APX NDD] Support APX NDD for and insn Hongyu Wang
2023-11-15 9:47 ` [PATCH 11/16] [APX NDD] Support APX NDD for or/xor insn Hongyu Wang
2023-11-15 9:47 ` [PATCH 12/16] [APX NDD] Support APX NDD for left shift insns Hongyu Wang
2023-11-15 9:47 ` [PATCH 13/16] [APX NDD] Support APX NDD for right " Hongyu Wang
2023-11-15 9:47 ` [PATCH 14/16] [APX NDD] Support APX NDD for rotate insns Hongyu Wang
2023-11-15 9:47 ` [PATCH 15/16] [APX NDD] Support APX NDD for shld/shrd insns Hongyu Wang
2023-11-15 9:47 ` [PATCH 16/16] [APX NDD] Support APX NDD for cmove insns Hongyu Wang
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