[PATCH 02/16] [APX NDD] Restrict TImode register usage when NDD enabled

[Hongyu Wang <hongyu.wang@intel.com>]

Under APX NDD, previous TImode allocation will have issue that it was
originally allocated using continuous pair, like rax:rdi, rdi:rdx.

This will cause issue for all TImode NDD patterns. For NDD we will not
assume the arithmetic operations like add have dependency between dest
and src1, then write to 1st highpart rdi will be overrided by the 2nd
lowpart rdi if 2nd lowpart rdi have different src as input, then the write
to 1st highpart rdi will missed and cause miscompliation.

To resolve this, under TARGET_APX_NDD we'd only allow register with even
regno to be allocated with TImode, then TImode registers will be allocated
with non-overlapping pairs.

There could be some error for inline assembly if it forcely allocate __int128
with odd number general register.

gcc/ChangeLog:

	* config/i386/i386.cc (ix86_hard_regno_mode_ok): Restrict even regno
	for TImode if APX NDD enabled.
---
 gcc/config/i386/i386.cc | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index 683ac643bc8..3779d5b1206 100644
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -20824,6 +20824,16 @@ ix86_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
        return true;
       return !can_create_pseudo_p ();
     }
+  /* With TImode we previously have assumption that src1/dest will use same
+     register, so the allocation of highpart/lowpart can be consecutive, and
+     2 TImode insn would held their low/highpart in continuous sequence like
+     rax:rdx, rdx:rcx. This will not work for APX_NDD since NDD allows
+     different registers as dest/src1, when writes to 2nd lowpart will impact
+     the writes to 1st highpart, then the insn will be optimized out. So for
+     TImode pattern if we support NDD form, the allowed register number should
+     be even to avoid such mixed high/low part override. */
+  else if (TARGET_APX_NDD && mode == TImode)
+    return regno % 2 == 0;
   /* We handle both integer and floats in the general purpose registers.  */
   else if (VALID_INT_MODE_P (mode)
 	   || VALID_FP_MODE_P (mode))
-- 
2.31.1