From: Hongyu Wang <hongyu.wang@intel.com>
To: gcc-patches@gcc.gnu.org
Cc: ubizjak@gmail.com, hongtao.liu@intel.com,
Kong Lingling <lingling.kong@intel.com>
Subject: [PATCH 06/16] [APX NDD] Support APX NDD for sub insns
Date: Wed, 15 Nov 2023 17:46:55 +0800 [thread overview]
Message-ID: <20231115094705.3976553-7-hongyu.wang@intel.com> (raw)
In-Reply-To: <20231115094705.3976553-1-hongyu.wang@intel.com>
From: Kong Lingling <lingling.kong@intel.com>
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_fixup_binary_operands_no_copy):
Add use_ndd parameter.
(ix86_can_use_ndd_p): ADD MINUS.
* config/i386/i386-protos.h (ix86_fixup_binary_operands_no_copy):
Change define.
* config/i386/i386.md (sub<mode>3): Add NDD constraints.
(*sub<mode>_1): Likewise.
(*subsi_1_zext): Likewise.
(*sub<mode>_2): Likewise.
(*subsi_2_zext): Likewise.
(subv<mode>4): Likewise.
(*subv<mode>4): Likewise.
(subv<mode>4_1): Likewise.
(usubv<mode>4): Likewise.
(*sub<mode>_3): Likewise.
(*subsi_3_zext): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-ndd.c: Add test for ndd sub.
[APX NDD] Support APX NDD for more optimized sub insn
gcc/ChangeLog:
* config/i386/i386.md
---
gcc/config/i386/i386-expand.cc | 6 +-
gcc/config/i386/i386-protos.h | 2 +-
gcc/config/i386/i386.md | 152 ++++++++++++++++--------
gcc/testsuite/gcc.target/i386/apx-ndd.c | 13 ++
4 files changed, 118 insertions(+), 55 deletions(-)
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index ea0e5881087..e5f75875e3b 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -1270,6 +1270,7 @@ bool ix86_can_use_ndd_p (enum rtx_code code)
switch (code)
{
case PLUS:
+ case MINUS:
return true;
default:
return false;
@@ -1342,9 +1343,10 @@ ix86_fixup_binary_operands (enum rtx_code code, machine_mode mode,
void
ix86_fixup_binary_operands_no_copy (enum rtx_code code,
- machine_mode mode, rtx operands[])
+ machine_mode mode, rtx operands[],
+ bool use_ndd)
{
- rtx dst = ix86_fixup_binary_operands (code, mode, operands);
+ rtx dst = ix86_fixup_binary_operands (code, mode, operands, use_ndd);
gcc_assert (dst == operands[0]);
}
diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h
index 5d902e2925b..ad895fac72d 100644
--- a/gcc/config/i386/i386-protos.h
+++ b/gcc/config/i386/i386-protos.h
@@ -111,7 +111,7 @@ extern void ix86_expand_vector_move_misalign (machine_mode, rtx[]);
extern rtx ix86_fixup_binary_operands (enum rtx_code,
machine_mode, rtx[], bool = false);
extern void ix86_fixup_binary_operands_no_copy (enum rtx_code,
- machine_mode, rtx[]);
+ machine_mode, rtx[], bool = false);
extern void ix86_expand_binary_operator (enum rtx_code,
machine_mode, rtx[], bool = false);
extern void ix86_expand_vector_logical_operator (enum rtx_code,
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index f23859d1172..1aa8469d666 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -7637,7 +7637,8 @@ (define_expand "sub<mode>3"
(minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")
(match_operand:SDWIM 2 "<general_hilo_operand>")))]
""
- "ix86_expand_binary_operator (MINUS, <MODE>mode, operands); DONE;")
+ "ix86_expand_binary_operator (MINUS, <MODE>mode, operands,
+ ix86_can_use_ndd_p (MINUS)); DONE;")
(define_insn_and_split "*sub<dwi>3_doubleword"
[(set (match_operand:<DWI> 0 "nonimmediate_operand" "=ro,r")
@@ -7663,7 +7664,10 @@ (define_insn_and_split "*sub<dwi>3_doubleword"
split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);
if (operands[2] == const0_rtx)
{
- ix86_expand_binary_operator (MINUS, <MODE>mode, &operands[3]);
+ if (!rtx_equal_p (operands[0], operands[1]))
+ emit_move_insn (operands[0], operands[1]);
+ ix86_expand_binary_operator (MINUS, <MODE>mode, &operands[3],
+ ix86_can_use_ndd_p (MINUS));
DONE;
}
})
@@ -7692,25 +7696,35 @@ (define_insn_and_split "*sub<dwi>3_doubleword_zext"
"split_double_mode (<DWI>mode, &operands[0], 2, &operands[0], &operands[3]);")
(define_insn "*sub<mode>_1"
- [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>i,r,r")
(minus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "0,0")
- (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>")))
+ (match_operand:SWI 1 "nonimmediate_operand" "0,0,rm,r")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>,r<i>,<m>")))
(clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
- "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
+ "ix86_binary_operator_ok (MINUS, <MODE>mode, operands,
+ ix86_can_use_ndd_p (MINUS))"
+ "@
+ sub{<imodesuffix>}\t{%2, %0|%0, %2}
+ sub{<imodesuffix>}\t{%2, %0|%0, %2}
+ sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(define_insn "*subsi_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
- (minus:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "x86_64_general_operand" "rBMe"))))
+ (minus:SI (match_operand:SI 1 "register_operand" "0,r")
+ (match_operand:SI 2 "x86_64_general_operand" "rBMe,rBMe"))))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "alu")
+ "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands,
+ ix86_can_use_ndd_p (MINUS))"
+ "@
+ sub{l}\t{%2, %k0|%k0, %2}
+ sub{l}\t{%2, %1, %k0|%k0, %1, %2}"
+ [(set_attr "isa" "*,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "mode" "SI")])
;; Alternative 1 is needed to work around LRA limitation, see PR82524.
@@ -7738,31 +7752,41 @@ (define_insn "*sub<mode>_2"
[(set (reg FLAGS_REG)
(compare
(minus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "0,0")
- (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>"))
+ (match_operand:SWI 1 "nonimmediate_operand" "0,0,rm,r")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>,r<i>,<m>"))
(const_int 0)))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>,r,r")
(minus:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
- "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
+ && ix86_binary_operator_ok (MINUS, <MODE>mode, operands,
+ ix86_can_use_ndd_p (MINUS))"
+ "@
+ sub{<imodesuffix>}\t{%2, %0|%0, %2}
+ sub{<imodesuffix>}\t{%2, %0|%0, %2}
+ sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(define_insn "*subsi_2_zext"
[(set (reg FLAGS_REG)
(compare
- (minus:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "x86_64_general_operand" "rBMe"))
+ (minus:SI (match_operand:SI 1 "register_operand" "0,r")
+ (match_operand:SI 2 "x86_64_general_operand" "rBMe,rBMe"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
+ (set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(minus:SI (match_dup 1)
(match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "alu")
+ && ix86_binary_operator_ok (MINUS, SImode, operands,
+ ix86_can_use_ndd_p (MINUS))"
+ "@
+ sub{l}\t{%2, %k0|%k0, %2}
+ sub{l}\t{%2, %1, %k0|%k0, %1, %2}"
+ [(set_attr "isa" "*,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "mode" "SI")])
(define_insn "*subqi_ext<mode>_0"
@@ -7841,7 +7865,8 @@ (define_expand "subv<mode>4"
(pc)))]
""
{
- ix86_fixup_binary_operands_no_copy (MINUS, <MODE>mode, operands);
+ ix86_fixup_binary_operands_no_copy (MINUS, <MODE>mode, operands,
+ ix86_can_use_ndd_p (MINUS));
if (CONST_SCALAR_INT_P (operands[2]))
operands[4] = operands[2];
else
@@ -7852,35 +7877,45 @@ (define_insn "*subv<mode>4"
[(set (reg:CCO FLAGS_REG)
(eq:CCO (minus:<DWI>
(sign_extend:<DWI>
- (match_operand:SWI 1 "nonimmediate_operand" "0,0"))
+ (match_operand:SWI 1 "nonimmediate_operand" "0,0,rm,r"))
(sign_extend:<DWI>
- (match_operand:SWI 2 "<general_sext_operand>" "<r>We,m")))
+ (match_operand:SWI 2 "<general_sext_operand>" "<r>We,m,rWe,m")))
(sign_extend:<DWI>
(minus:SWI (match_dup 1) (match_dup 2)))))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>,r,r")
(minus:SWI (match_dup 1) (match_dup 2)))]
- "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
- "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
+ "ix86_binary_operator_ok (MINUS, <MODE>mode, operands,
+ ix86_can_use_ndd_p (MINUS))"
+ "@
+ sub{<imodesuffix>}\t{%2, %0|%0, %2}
+ sub{<imodesuffix>}\t{%2, %0|%0, %2}
+ sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(define_insn "subv<mode>4_1"
[(set (reg:CCO FLAGS_REG)
(eq:CCO (minus:<DWI>
(sign_extend:<DWI>
- (match_operand:SWI 1 "nonimmediate_operand" "0"))
+ (match_operand:SWI 1 "nonimmediate_operand" "0,rm"))
(match_operand:<DWI> 3 "const_int_operand"))
(sign_extend:<DWI>
(minus:SWI
(match_dup 1)
- (match_operand:SWI 2 "x86_64_immediate_operand" "<i>")))))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m")
+ (match_operand:SWI 2 "x86_64_immediate_operand" "<i>,<i>")))))
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,r")
(minus:SWI (match_dup 1) (match_dup 2)))]
- "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)
+ "ix86_binary_operator_ok (MINUS, <MODE>mode, operands,
+ ix86_can_use_ndd_p (MINUS))
&& CONST_INT_P (operands[2])
&& INTVAL (operands[2]) == INTVAL (operands[3])"
- "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
+ "@
+ sub{<imodesuffix>}\t{%2, %0|%0, %2}
+ sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "mode" "<MODE>")
(set (attr "length_immediate")
(cond [(match_test "IN_RANGE (INTVAL (operands[2]), -128, 127)")
@@ -7976,6 +8011,8 @@ (define_insn_and_split "*subv<dwi>4_doubleword_1"
split_double_mode (<DWI>mode, &operands[0], 3, &operands[0], &operands[3]);
if (operands[2] == const0_rtx)
{
+ if (!rtx_equal_p (operands[0], operands[1]))
+ emit_move_insn (operands[0], operands[1]);
emit_insn (gen_subv<mode>4_1 (operands[3], operands[4], operands[5],
operands[5]));
DONE;
@@ -8057,18 +8094,25 @@ (define_expand "usubv<mode>4"
(label_ref (match_operand 3))
(pc)))]
""
- "ix86_fixup_binary_operands_no_copy (MINUS, <MODE>mode, operands);")
+ "ix86_fixup_binary_operands_no_copy (MINUS, <MODE>mode, operands,
+ ix86_can_use_ndd_p (MINUS));")
(define_insn "*sub<mode>_3"
[(set (reg FLAGS_REG)
- (compare (match_operand:SWI 1 "nonimmediate_operand" "0,0")
- (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>")))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
+ (compare (match_operand:SWI 1 "nonimmediate_operand" "0,0,rm,r")
+ (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>,r<i>,<m>")))
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>i,r,r")
(minus:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCmode)
- && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
- "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
- [(set_attr "type" "alu")
+ && ix86_binary_operator_ok (MINUS, <MODE>mode, operands,
+ ix86_can_use_ndd_p (MINUS))"
+ "@
+ sub{<imodesuffix>}\t{%2, %0|%0, %2}
+ sub{<imodesuffix>}\t{%2, %0|%0, %2}
+ sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}
+ sub{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,*,apx_ndd,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
(define_peephole2
@@ -8156,16 +8200,20 @@ (define_insn_and_split "*dec_cmov<mode>"
(define_insn "*subsi_3_zext"
[(set (reg FLAGS_REG)
- (compare (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "x86_64_general_operand" "rBMe")))
- (set (match_operand:DI 0 "register_operand" "=r")
+ (compare (match_operand:SI 1 "register_operand" "0,r")
+ (match_operand:SI 2 "x86_64_general_operand" "rBMe,rBMe")))
+ (set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(minus:SI (match_dup 1)
(match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
- && ix86_binary_operator_ok (MINUS, SImode, operands)"
- "sub{l}\t{%2, %1|%1, %2}"
- [(set_attr "type" "alu")
+ && ix86_binary_operator_ok (MINUS, SImode, operands,
+ ix86_can_use_ndd_p (MINUS))"
+ "@
+ sub{l}\t{%2, %1|%1, %2}
+ sub{l}\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,apx_ndd")
+ (set_attr "type" "alu")
(set_attr "mode" "SI")])
\f
;; Add with carry and subtract with borrow
diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd.c b/gcc/testsuite/gcc.target/i386/apx-ndd.c
index 6c136174d24..9d444e0d830 100644
--- a/gcc/testsuite/gcc.target/i386/apx-ndd.c
+++ b/gcc/testsuite/gcc.target/i386/apx-ndd.c
@@ -42,3 +42,16 @@ FOO (long, add, +)
FOO1 (long, add, +)
FOO2 (long, add, +)
+FOO (char, sub, -)
+FOO1 (char, sub, -)
+FOO (short, sub, -)
+FOO1 (short, sub, -)
+FOO (int, sub, -)
+FOO1 (int, sub, -)
+FOO (long, sub, -)
+FOO1 (long, sub, -)
+/* { dg-final { scan-assembler-times "add(?:l|w|q)\[^\n\r]*1, \\(%rdi\\), %(?:|r|e)ax" 4 } } */
+/* { dg-final { scan-assembler-times "lea(?:l|q)\[^\n\r]\\(%r(?:d|s)i,%r(?:d|s)i\\), %(?:|r|e)ax" 4 } } */
+/* { dg-final { scan-assembler-times "add(?:l|w|q)\[^\n\r]%(?:|r|e)si, \\(%rdi\\), %(?:|r|e)ax" 4 } } */
+/* { dg-final { scan-assembler-times "sub(?:l|w|q)\[^\n\r]*1, \\(%rdi\\), %(?:|r|e)ax" 4 } } */
+/* { dg-final { scan-assembler-times "sub(?:l|w|q)\[^\n\r]%(?:|r|e)si, %(?:|r|e)di, %(?:|r|e)ax" 4 } } */
--
2.31.1
next prev parent reply other threads:[~2023-11-15 9:47 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-15 9:46 [PATCH 00/16] Support Intel APX NDD Hongyu Wang
2023-11-15 9:46 ` [PATCH 01/16] [APX NDD] Support Intel APX NDD for legacy add insn Hongyu Wang
2023-11-15 9:46 ` [PATCH 02/16] [APX NDD] Restrict TImode register usage when NDD enabled Hongyu Wang
2023-11-15 9:46 ` [PATCH 03/16] [APX NDD] Support APX NDD for optimization patterns of add Hongyu Wang
2023-11-15 9:46 ` [PATCH 04/16] [APX NDD] Disable seg_prefixed memory usage for NDD add Hongyu Wang
2023-11-15 9:46 ` [PATCH 05/16] [APX NDD] Support APX NDD for adc insns Hongyu Wang
2023-11-15 9:46 ` Hongyu Wang [this message]
2023-11-15 9:46 ` [PATCH 07/16] [APX NDD] Support APX NDD for sbb insn Hongyu Wang
2023-11-15 9:46 ` [PATCH 08/16] [APX NDD] Support APX NDD for neg insn Hongyu Wang
2023-11-15 9:46 ` [PATCH 09/16] [APX NDD] Support APX NDD for not insn Hongyu Wang
2023-11-15 9:46 ` [PATCH 10/16] [APX NDD] Support APX NDD for and insn Hongyu Wang
2023-11-15 9:47 ` [PATCH 11/16] [APX NDD] Support APX NDD for or/xor insn Hongyu Wang
2023-11-15 9:47 ` [PATCH 12/16] [APX NDD] Support APX NDD for left shift insns Hongyu Wang
2023-11-15 9:47 ` [PATCH 13/16] [APX NDD] Support APX NDD for right " Hongyu Wang
2023-11-15 9:47 ` [PATCH 14/16] [APX NDD] Support APX NDD for rotate insns Hongyu Wang
2023-11-15 9:47 ` [PATCH 15/16] [APX NDD] Support APX NDD for shld/shrd insns Hongyu Wang
2023-11-15 9:47 ` [PATCH 16/16] [APX NDD] Support APX NDD for cmove insns Hongyu Wang
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