From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oo1-xc31.google.com (mail-oo1-xc31.google.com [IPv6:2607:f8b0:4864:20::c31]) by sourceware.org (Postfix) with ESMTPS id 81B053858D32 for ; Wed, 15 Nov 2023 23:31:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 81B053858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 81B053858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::c31 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700091075; cv=none; b=AYK7l82CZNDqprSduCjK34Pe+Ya1TG94K9qi4/JWIv33vI3ZtohRYwpFCxPzIHZh8migCkxsFp4lnfgk3qibisrqphzBYaU/xjLTPiLe1vPX7Rxr3ope7H9UHvXSTXKcVl2pn3ZXyLJzTQrjuiynpA5rYpSQwryfHp96BTwR2R8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700091075; c=relaxed/simple; bh=jN8xZHHPSwN3rG2W4yuhBdwuNxEk0Di+G/4Hz/tY8sI=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=kcwRBF5gLz9RpneZJTCpVsv2dit5OVRoBDP/OCcMIBLuCeOCwDGKzL9Q9Yq5kF1muTCaBRjxlQxw64XI2572U3NtL2F6Cd5VV5kjJQ7A6dF1q2hkzn//Vh9kPyub4jiYCyenUmHTLPhGweICBtLRk1vyr+xqsr1gX7VUWNbeLVM= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-oo1-xc31.google.com with SMTP id 006d021491bc7-586ae6edf77so118319eaf.1 for ; Wed, 15 Nov 2023 15:31:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1700091071; x=1700695871; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=H5gDidkoXjvCAeKY6UMc+od2APo0z3moTI4vOjZoIr4=; b=3V094GJFGZaM8J/PAoOXvI5LeU9DJVE7icgYH/aT8I6r+98DDwfDkT94r/kCHm77zf Rl7h7V1NHSmNcygptqvDl8W2NIj0ncNMyJ0/E6XsnZmCBuRzqYKF4R7ujCQHZYgcVFNf F9XopPYf8kKHOX27rDxefl717mDZ9kn2qTAIDdGmDUdXzjUOcsDCMyGCxBLYAVU416VL lCJ3aqiyteYrLkRyFTvV4DIGyCwNpNRnvxjBK1dB0mgjmpNQVEmey1ACr1Oh+E5Kc9NB ZiqVxg4h3QSAbpMyfeVLkKA0nOF4RhlpvdAuuizd7JGWVpgUGFqztySuFSJTT/5UATMe NxFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700091071; x=1700695871; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=H5gDidkoXjvCAeKY6UMc+od2APo0z3moTI4vOjZoIr4=; b=bQKIcnErbWwc50xEBk9fD4SqAvCS6BJ2MGlohQQJsrkCqmAD5AvdcgR01ipn81bFoA tjlalIH3+oCV+Nv+aM2toCtbT3O7nPgbotiP73lAVB7xcPIpcD7Ron0I21+5v4J01gUH ORMOvheuxk2CdK10opRkp2s5OCKCwLhve/uGinyUgYcMZt7DTxrAIOFSOTjmYarq3nMc LVQO91mdJEF2nUw+Qp8+U1oNyccWI/I605gYDPXQJ3hEj1p3l213rKaS7MWMPM1sWahg I8CCpRdvXxY0gUEHzarcQPcDoV5zU7mJoWlc7bK8W7E0/5L9rJo+WJ2pZAZx0l+8v8j2 qxIA== X-Gm-Message-State: AOJu0Yzot4Kk2jMXbWFgr4O8/vlEIhddcyzkLQROE0pexXeSfIIDLl4M VQhqW5uJepPUSJC0uxk7mgabvCEDnDoWSDNJOOA= X-Google-Smtp-Source: AGHT+IFeRwijRJt8aPV3418HZB0wSrq4M1MiJe0FcSM78D/89cneY7vDJ5Ft++3Xk9p5Akr7xP9Ytw== X-Received: by 2002:a4a:924a:0:b0:589:df75:2d7b with SMTP id g10-20020a4a924a000000b00589df752d7bmr12795743ooh.2.1700091071666; Wed, 15 Nov 2023 15:31:11 -0800 (PST) Received: from ewlu.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d8-20020a4aaa88000000b0058a133c3641sm347740oon.6.2023.11.15.15.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 15:31:11 -0800 (PST) From: Edwin Lu To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, Edwin Lu Subject: [PATCH] RISC-V: Change unaligned fast/slow/avoid macros to misaligned [PR111557] Date: Wed, 15 Nov 2023 15:30:42 -0800 Message-Id: <20231115233042.557245-1-ewlu@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Fix __riscv_unaligned_fast/slow/avoid macro name to __riscv_misaligned_fast/slow/avoid to be consistent with the RISC-V API Spec gcc/ChangeLog: * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): update macro name gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-1.c: update macro name * gcc.target/riscv/attribute-4.c: ditto * gcc.target/riscv/attribute-5.c: ditto * gcc.target/riscv/predef-align-1.c: ditto * gcc.target/riscv/predef-align-2.c: ditto * gcc.target/riscv/predef-align-3.c: ditto * gcc.target/riscv/predef-align-4.c: ditto * gcc.target/riscv/predef-align-5.c: ditto * gcc.target/riscv/predef-align-6.c: ditto Signed-off-by: Edwin Lu --- gcc/config/riscv/riscv-c.cc | 6 +++--- gcc/testsuite/gcc.target/riscv/attribute-1.c | 10 +++++----- gcc/testsuite/gcc.target/riscv/attribute-4.c | 8 ++++---- gcc/testsuite/gcc.target/riscv/attribute-5.c | 10 +++++----- gcc/testsuite/gcc.target/riscv/predef-align-1.c | 10 +++++----- gcc/testsuite/gcc.target/riscv/predef-align-2.c | 8 ++++---- gcc/testsuite/gcc.target/riscv/predef-align-3.c | 10 +++++----- gcc/testsuite/gcc.target/riscv/predef-align-4.c | 10 +++++----- gcc/testsuite/gcc.target/riscv/predef-align-5.c | 8 ++++---- gcc/testsuite/gcc.target/riscv/predef-align-6.c | 10 +++++----- 10 files changed, 45 insertions(+), 45 deletions(-) diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index b7f9ba204f7..dd1bd0596fc 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -109,11 +109,11 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) } if (riscv_user_wants_strict_align) - builtin_define_with_int_value ("__riscv_unaligned_avoid", 1); + builtin_define_with_int_value ("__riscv_misaligned_avoid", 1); else if (riscv_slow_unaligned_access_p) - builtin_define_with_int_value ("__riscv_unaligned_slow", 1); + builtin_define_with_int_value ("__riscv_misaligned_slow", 1); else - builtin_define_with_int_value ("__riscv_unaligned_fast", 1); + builtin_define_with_int_value ("__riscv_misaligned_fast", 1); if (TARGET_MIN_VLEN != 0) builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN); diff --git a/gcc/testsuite/gcc.target/riscv/attribute-1.c b/gcc/testsuite/gcc.target/riscv/attribute-1.c index abfb0b498e0..a39efb3e6ff 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-1.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-1.c @@ -4,13 +4,13 @@ int foo() { /* In absence of -m[no-]strict-align, default mcpu is currently - set to rocket. rocket has slow_unaligned_access=true. */ -#if !defined(__riscv_unaligned_slow) -#error "__riscv_unaligned_slow is not set" + set to rocket. rocket has slow_misaligned_access=true. */ +#if !defined(__riscv_misaligned_slow) +#error "__riscv_misaligned_slow is not set" #endif -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast) +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set" #endif return 0; diff --git a/gcc/testsuite/gcc.target/riscv/attribute-4.c b/gcc/testsuite/gcc.target/riscv/attribute-4.c index 545f87cb899..a5a95042a31 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-4.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-4.c @@ -3,12 +3,12 @@ int foo() { -#if !defined(__riscv_unaligned_avoid) -#error "__riscv_unaligned_avoid is not set" +#if !defined(__riscv_misaligned_avoid) +#error "__riscv_misaligned_avoid is not set" #endif -#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) -#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set" +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpectedly set" #endif return 0; diff --git a/gcc/testsuite/gcc.target/riscv/attribute-5.c b/gcc/testsuite/gcc.target/riscv/attribute-5.c index 753043c31e9..ad1a1811fa3 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-5.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-5.c @@ -3,13 +3,13 @@ int foo() { -/* Default mcpu is rocket which has slow_unaligned_access=true. */ -#if !defined(__riscv_unaligned_slow) -#error "__riscv_unaligned_slow is not set" +/* Default mcpu is rocket which has slow_misaligned_access=true. */ +#if !defined(__riscv_misaligned_slow) +#error "__riscv_misaligned_slow is not set" #endif -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast) +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set" #endif return 0; diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-1.c b/gcc/testsuite/gcc.target/riscv/predef-align-1.c index 9dde37a721e..fb8c5f74035 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-align-1.c +++ b/gcc/testsuite/gcc.target/riscv/predef-align-1.c @@ -3,13 +3,13 @@ int main() { -/* thead-c906 default is cpu tune param unaligned access fast */ -#if !defined(__riscv_unaligned_fast) -#error "__riscv_unaligned_fast is not set" +/* thead-c906 default is cpu tune param misaligned access fast */ +#if !defined(__riscv_misaligned_fast) +#error "__riscv_misaligned_fast is not set" #endif -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow) -#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedly set" +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_slow) +#error "__riscv_misaligned_avoid or __riscv_misaligned_slow is unexpectedly set" #endif return 0; diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-2.c b/gcc/testsuite/gcc.target/riscv/predef-align-2.c index 33d604f5aa0..50ab67e04f5 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-align-2.c +++ b/gcc/testsuite/gcc.target/riscv/predef-align-2.c @@ -3,12 +3,12 @@ int main() { -#if !defined(__riscv_unaligned_avoid) -#error "__riscv_unaligned_avoid is not set" +#if !defined(__riscv_misaligned_avoid) +#error "__riscv_misaligned_avoid is not set" #endif -#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) -#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set" +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpectedly set" #endif return 0; diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-3.c b/gcc/testsuite/gcc.target/riscv/predef-align-3.c index daf5718a39f..5c586907cb0 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-align-3.c +++ b/gcc/testsuite/gcc.target/riscv/predef-align-3.c @@ -3,13 +3,13 @@ int main() { -/* thead-c906 default is cpu tune param unaligned access fast */ -#if !defined(__riscv_unaligned_fast) -#error "__riscv_unaligned_fast is not set" +/* thead-c906 default is cpu tune param misaligned access fast */ +#if !defined(__riscv_misaligned_fast) +#error "__riscv_misaligned_fast is not set" #endif -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_slow) -#error "__riscv_unaligned_avoid or __riscv_unaligned_slow is unexpectedly set" +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_slow) +#error "__riscv_misaligned_avoid or __riscv_misaligned_slow is unexpectedly set" #endif return 0; diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-4.c b/gcc/testsuite/gcc.target/riscv/predef-align-4.c index d46a46f252d..6fbdc7f7d41 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-align-4.c +++ b/gcc/testsuite/gcc.target/riscv/predef-align-4.c @@ -3,13 +3,13 @@ int main() { -/* rocket default is cpu tune param unaligned access slow */ -#if !defined(__riscv_unaligned_slow) -#error "__riscv_unaligned_slow is not set" +/* rocket default is cpu tune param misaligned access slow */ +#if !defined(__riscv_misaligned_slow) +#error "__riscv_misaligned_slow is not set" #endif -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast) +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set" #endif return 0; diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-5.c b/gcc/testsuite/gcc.target/riscv/predef-align-5.c index 3aa25f8e0e0..4a40081d86d 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-align-5.c +++ b/gcc/testsuite/gcc.target/riscv/predef-align-5.c @@ -3,12 +3,12 @@ int main() { -#if !defined(__riscv_unaligned_avoid) -#error "__riscv_unaligned_avoid is not set" +#if !defined(__riscv_misaligned_avoid) +#error "__riscv_misaligned_avoid is not set" #endif -#if defined(__riscv_unaligned_fast) || defined(__riscv_unaligned_slow) -#error "__riscv_unaligned_fast or __riscv_unaligned_slow is unexpectedly set" +#if defined(__riscv_misaligned_fast) || defined(__riscv_misaligned_slow) +#error "__riscv_misaligned_fast or __riscv_misaligned_slow is unexpectedly set" #endif return 0; diff --git a/gcc/testsuite/gcc.target/riscv/predef-align-6.c b/gcc/testsuite/gcc.target/riscv/predef-align-6.c index cb64d7e7778..18eb72cfc60 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-align-6.c +++ b/gcc/testsuite/gcc.target/riscv/predef-align-6.c @@ -3,13 +3,13 @@ int main() { -/* rocket default is cpu tune param unaligned access slow */ -#if !defined(__riscv_unaligned_slow) -#error "__riscv_unaligned_slow is not set" +/* rocket default is cpu tune param misaligned access slow */ +#if !defined(__riscv_misaligned_slow) +#error "__riscv_misaligned_slow is not set" #endif -#if defined(__riscv_unaligned_avoid) || defined(__riscv_unaligned_fast) -#error "__riscv_unaligned_avoid or __riscv_unaligned_fast is unexpectedly set" +#if defined(__riscv_misaligned_avoid) || defined(__riscv_misaligned_fast) +#error "__riscv_misaligned_avoid or __riscv_misaligned_fast is unexpectedly set" #endif return 0; -- 2.34.1