[PATCH 2/5] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution

[Xi Ruoyao <xry111@xry111.site>]

LoongArch v1.10 introduced the concept of ISA evolution.  During ISA
evolution, many independent features can be added and enumerated via
CPUCFG.

Add a data file into genopts storing the CPUCFG word, bit, the name
of the command line option controlling if this feature should be used
for compilation, and the text description.  Make genstr.sh process these
info and add the command line options into loongarch.opt and
loongarch-str.h, and generate a new file loongarch-cpucfg-map.h for
mapping CPUCFG output to the corresponding option.  When handling
-march=native, use the information in loongarch-cpucfg-map.h to generate
the corresponding option mask.  Enable the features implied by -march
setting unless the user has explicitly disabled the feature.

The added options (-mdiv32 and -mld-seq-sa) are not really handled yet.
They'll be used in the following patches.

gcc/ChangeLog:

	* config/loongarch/genopts/isa-evolution.in: New data file.
	* config/loongarch/genopts/genstr.sh: Translate info in
	isa-evolution.in when generating loongarch-str.h, loongarch.opt,
	and loongarch-cpucfg-map.h.
	* config/loongarch/genopts/loongarch.opt.in (isa_evolution):
	New variable.
	* config/loongarch/t-loongarch: (loongarch-cpucfg-map.h): New
	rule.
	(loongarch-str.h): Depend on isa-evolution.in.
	(loongarch.opt): Depend on isa-evolution.in.
	(loongarch-cpu.o): Depend on loongarch-cpucfg-map.h.
	* config/loongarch/loongarch-str.h: Regenerate.
	* config/loongarch/loongarch.opt: Regenerate.
	* config/loongarch/loongarch-cpucfg-map.h: Generate.
	* config/loongarch/loongarch-def.h (loongarch_isa):  Add field
	for evolution features.  Add helper function to enable features
	in this field.
	Probe native CPU capability and save the corresponding options
	into preset.
	* config/loongarch/loongarch-cpu.cc (fill_native_cpu_config):
	Probe native CPU capability and save the corresponding options
	into preset.
	* config/loongarch/loongarch.cc
	(loongarch_option_override_internal): Enable the ISA evolution
	feature options implied by -march and not explicitly disabled.
	* config/loongarch/loongarch-def.cc: Define IN_TARGET_CODE to 1
	so it's possible to include config.h and system.h for
	HOST_WIDE_INT.
---
 gcc/config/loongarch/genopts/genstr.sh        | 78 +++++++++++++++++--
 gcc/config/loongarch/genopts/isa-evolution.in |  2 +
 gcc/config/loongarch/genopts/loongarch.opt.in |  7 ++
 gcc/config/loongarch/loongarch-cpu.cc         | 37 +++++----
 gcc/config/loongarch/loongarch-cpucfg-map.h   | 36 +++++++++
 gcc/config/loongarch/loongarch-def.cc         |  3 +
 gcc/config/loongarch/loongarch-def.h          | 11 ++-
 gcc/config/loongarch/loongarch-str.h          |  7 +-
 gcc/config/loongarch/loongarch.cc             |  4 +
 gcc/config/loongarch/loongarch.opt            | 20 ++++-
 gcc/config/loongarch/t-loongarch              | 21 ++++-
 11 files changed, 196 insertions(+), 30 deletions(-)
 create mode 100644 gcc/config/loongarch/genopts/isa-evolution.in
 create mode 100644 gcc/config/loongarch/loongarch-cpucfg-map.h

diff --git a/gcc/config/loongarch/genopts/genstr.sh b/gcc/config/loongarch/genopts/genstr.sh
index 04e785576bb..7f461118a97 100755
--- a/gcc/config/loongarch/genopts/genstr.sh
+++ b/gcc/config/loongarch/genopts/genstr.sh
@@ -25,8 +25,8 @@ cd "$(dirname "$0")"
 # Generate a header containing definitions from the string table.
 gen_defines() {
     cat <<EOF
-/* Generated automatically by "genstr" from "loongarch-strings".
-   Please do not edit this file directly.
+/* Generated automatically by "genstr" from "loongarch-strings" and
+   "isa-evolution.in".  Please do not edit this file directly.
 
    Copyright (C) 2021-2023 Free Software Foundation, Inc.
    Contributed by Loongson Ltd.
@@ -55,6 +55,15 @@ EOF
 	-e 's@^\([^ \t]\+\)[ \t]*\([^ \t]*\)@#define \1 "\2"@' \
 	loongarch-strings
 
+    echo
+
+	# Generate the strings from isa-evolution.in.
+	awk '{
+	  a=$3
+	  gsub(/-/, "_", a)
+	  print("#define OPTSTR_"toupper(a)"\t\""$3"\"")
+	}' isa-evolution.in
+
     echo
     echo "#endif /* LOONGARCH_STR_H */"
 }
@@ -77,11 +86,12 @@ gen_options() {
 	# print a header
 	cat << EOF
 ; Generated by "genstr" from the template "loongarch.opt.in"
-; and definitions from "loongarch-strings".
+; and definitions from "loongarch-strings" and "isa-evolution.in".
 ;
 ; Please do not edit this file directly.
 ; It will be automatically updated during a gcc build
-; if you change "loongarch.opt.in" or "loongarch-strings".
+; if you change "loongarch.opt.in", "loongarch-strings", or
+; "isa-evolution.in".
 ;
 EOF
 
@@ -91,13 +101,71 @@ EOF
 		eval "echo \"$line\""
 	    done
     }
+
+	# Generate the strings from isa-evolution.in.
+	awk '{
+	  print("")
+	  print("m"$3)
+	  gsub(/-/, "_", $3)
+	  print("Target Mask(ISA_"toupper($3)") Var(isa_evolution)")
+	  $1=""; $2=""; $3=""
+	  sub(/^ */, "", $0)
+	  print($0)
+	}' isa-evolution.in
+}
+
+gen_cpucfg_map() {
+    cat <<EOF
+/* Generated automatically by "genstr" from "isa-evolution.in".
+   Please do not edit this file directly.
+
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#ifndef LOONGARCH_CPUCFG_MAP_H
+#define LOONGARCH_CPUCFG_MAP_H
+
+#include "options.h"
+
+static constexpr struct {
+  int cpucfg_word;
+  unsigned int cpucfg_bit;
+  HOST_WIDE_INT isa_evolution_bit;
+} cpucfg_map[] = {
+EOF
+
+	# Generate the strings from isa-evolution.in.
+	awk '{
+	  gsub(/-/, "_", $3)
+	  print("  { "$1", 1u << "$2", OPTION_MASK_ISA_"toupper($3)" },")
+	}' isa-evolution.in
+
+    echo "};"
+    echo
+    echo "#endif /* LOONGARCH_STR_H */"
 }
 
 main() {
     case "$1" in
+	cpucfg-map) gen_cpucfg_map;;
 	header) gen_defines;;
 	opt) gen_options;;
-	*) echo "Unknown Command: \"$1\". Available: header, opt"; exit 1;;
+	*) echo "Unknown Command: \"$1\". Available: cpucfg-map, header, opt"; exit 1;;
     esac
 }
 
diff --git a/gcc/config/loongarch/genopts/isa-evolution.in b/gcc/config/loongarch/genopts/isa-evolution.in
new file mode 100644
index 00000000000..7525be762fb
--- /dev/null
+++ b/gcc/config/loongarch/genopts/isa-evolution.in
@@ -0,0 +1,2 @@
+0x2	26	div32		Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
+0x3	23	ld-seq-sa	Do not need load-load barriers (dbar 0x700).
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index 158701d327a..4a22039681f 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -241,3 +241,10 @@ Target Undocumented Joined UInteger Var(loongarch_vect_issue_info) Init(4) Integ
 Indicate how many non memory access vector instructions can be issued per
 cycle, it's used in unroll factor determination for autovectorizer.  The
 default value is 4.
+
+; Features added during ISA evolution.  This concept is different from ISA
+; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the
+; explanation.  These features may be implemented and enumerated with
+; CPUCFG independantly, so we use bit flags to specify them.
+Variable
+HOST_WIDE_INT isa_evolution = 0
diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
index 7a2866f60f9..03acf632353 100644
--- a/gcc/config/loongarch/loongarch-cpu.cc
+++ b/gcc/config/loongarch/loongarch-cpu.cc
@@ -29,6 +29,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "loongarch-def.h"
 #include "loongarch-opts.h"
 #include "loongarch-cpu.h"
+#include "loongarch-cpucfg-map.h"
 #include "loongarch-str.h"
 
 /* Native CPU detection with "cpucfg" */
@@ -121,11 +122,12 @@ fill_native_cpu_config (struct loongarch_target *tgt)
       int tmp;
       tgt->cpu_arch = native_cpu_type;
 
+      auto &preset = loongarch_cpu_default_isa[tgt->cpu_arch];
+
       /* Fill: loongarch_cpu_default_isa[tgt->cpu_arch].base
 	 With: base architecture (ARCH)
 	 At:   cpucfg_words[1][1:0] */
 
-      #define PRESET_ARCH (loongarch_cpu_default_isa[tgt->cpu_arch].base)
       switch (cpucfg_cache[1] & 0x3)
 	{
 	  case 0x02:
@@ -140,19 +142,18 @@ fill_native_cpu_config (struct loongarch_target *tgt)
 	}
 
       /* Check consistency with PRID presets.  */
-      if (native_cpu_type != CPU_NATIVE && tmp != PRESET_ARCH)
+      if (native_cpu_type != CPU_NATIVE && tmp != preset.base)
 	warning (0, "base architecture %qs differs from PRID preset %qs",
 		 loongarch_isa_base_strings[tmp],
-		 loongarch_isa_base_strings[PRESET_ARCH]);
+		 loongarch_isa_base_strings[preset.base]);
 
       /* Use the native value anyways.  */
-      PRESET_ARCH = tmp;
+      preset.base = tmp;
 
       /* Fill: loongarch_cpu_default_isa[tgt->cpu_arch].fpu
 	 With: FPU type (FP, FP_SP, FP_DP)
 	 At:   cpucfg_words[2][2:0] */
 
-      #define PRESET_FPU (loongarch_cpu_default_isa[tgt->cpu_arch].fpu)
       switch (cpucfg_cache[2] & 0x7)
 	{
 	  case 0x07:
@@ -175,20 +176,19 @@ fill_native_cpu_config (struct loongarch_target *tgt)
 	}
 
       /* Check consistency with PRID presets.  */
-      if (native_cpu_type != CPU_NATIVE && tmp != PRESET_FPU)
+      if (native_cpu_type != CPU_NATIVE && tmp != preset.fpu)
 	warning (0, "floating-point unit %qs differs from PRID preset %qs",
 		 loongarch_isa_ext_strings[tmp],
-		 loongarch_isa_ext_strings[PRESET_FPU]);
+		 loongarch_isa_ext_strings[preset.fpu]);
 
       /* Use the native value anyways.  */
-      PRESET_FPU = tmp;
+      preset.fpu = tmp;
 
 
       /* Fill: loongarch_cpu_default_isa[CPU_NATIVE].simd
 	 With: SIMD extension type (LSX, LASX)
 	 At:   cpucfg_words[2][7:6] */
 
-      #define PRESET_SIMD (loongarch_cpu_default_isa[tgt->cpu_arch].simd)
       switch (cpucfg_cache[2] & 0xc0)
 	{
 	  case 0xc0:
@@ -215,14 +215,19 @@ fill_native_cpu_config (struct loongarch_target *tgt)
       /* Check consistency with PRID presets.  */
 
       /*
-      if (native_cpu_type != CPU_NATIVE && tmp != PRESET_SIMD)
+      if (native_cpu_type != CPU_NATIVE && tmp != preset.simd)
 	warning (0, "SIMD extension %qs differs from PRID preset %qs",
 		 loongarch_isa_ext_strings[tmp],
-		 loongarch_isa_ext_strings[PRESET_SIMD]);
+		 loongarch_isa_ext_strings[preset.simd]);
       */
 
       /* Use the native value anyways.  */
-      PRESET_SIMD = tmp;
+      preset.simd = tmp;
+
+      /* Features added during ISA evolution.  */
+      for (const auto &entry: cpucfg_map)
+	if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit)
+	  preset.evol_add_feat (entry.isa_evolution_bit);
     }
 
   if (tune_native_p)
@@ -233,7 +238,7 @@ fill_native_cpu_config (struct loongarch_target *tgt)
 	 With: cache size info
 	 At:   cpucfg_words[16:20][31:0] */
 
-      #define PRESET_CACHE (loongarch_cpu_cache[tgt->cpu_tune])
+      auto &preset_cache = loongarch_cpu_cache[tgt->cpu_tune];
       struct loongarch_cache native_cache;
       int l1d_present = 0, l1u_present = 0;
       int l2d_present = 0;
@@ -264,8 +269,8 @@ fill_native_cpu_config (struct loongarch_target *tgt)
 	>> 10;					  /* in kibibytes */
 
       /* Use the native value anyways.  */
-      PRESET_CACHE.l1d_line_size = native_cache.l1d_line_size;
-      PRESET_CACHE.l1d_size = native_cache.l1d_size;
-      PRESET_CACHE.l2d_size = native_cache.l2d_size;
+      preset_cache.l1d_line_size = native_cache.l1d_line_size;
+      preset_cache.l1d_size = native_cache.l1d_size;
+      preset_cache.l2d_size = native_cache.l2d_size;
     }
 }
diff --git a/gcc/config/loongarch/loongarch-cpucfg-map.h b/gcc/config/loongarch/loongarch-cpucfg-map.h
new file mode 100644
index 00000000000..78a4acf535b
--- /dev/null
+++ b/gcc/config/loongarch/loongarch-cpucfg-map.h
@@ -0,0 +1,36 @@
+/* Generated automatically by "genstr" from "isa-evolution.in".
+   Please do not edit this file directly.
+
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#ifndef LOONGARCH_CPUCFG_MAP_H
+#define LOONGARCH_CPUCFG_MAP_H
+
+#include "options.h"
+
+static constexpr struct {
+  int cpucfg_word;
+  unsigned int cpucfg_bit;
+  HOST_WIDE_INT isa_evolution_bit;
+} cpucfg_map[] = {
+  { 0x2, 1u << 26, OPTION_MASK_ISA_DIV32 },
+  { 0x3, 1u << 23, OPTION_MASK_ISA_LD_SEQ_SA },
+};
+
+#endif /* LOONGARCH_STR_H */
diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc
index 0200c48f43b..9c2ec1ec135 100644
--- a/gcc/config/loongarch/loongarch-def.cc
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -18,6 +18,9 @@ You should have received a copy of the GNU General Public License
 along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 
+#define IN_TARGET_CODE
+#include "config.h"
+#include "system.h"
 #include "loongarch-def.h"
 #include "loongarch-str.h"
 
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index d36c2769f78..e74036fda33 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -120,10 +120,19 @@ struct loongarch_isa
   int fpu;	    /* ISA_EXT_FPU_ */
   int simd;	    /* ISA_EXT_SIMD_ */
 
-  loongarch_isa () : base (0), fpu (0), simd (0) {}
+  /* ISA evolution features implied by cpu_arch or probed for native.  */
+  HOST_WIDE_INT evolution;
+
+  loongarch_isa () : base (0), fpu (0), simd (0), evolution (0) {}
   loongarch_isa base_ (int _base) { base = _base; return *this; }
   loongarch_isa fpu_ (int _fpu) { fpu = _fpu; return *this; }
   loongarch_isa simd_ (int _simd) { simd = _simd; return *this; }
+
+  loongarch_isa evol_add_feat (HOST_WIDE_INT bit)
+  {
+    evolution |= bit;
+    return *this;
+  }
 };
 
 struct loongarch_abi
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index 072558c28f1..3fa2ed5fc49 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -1,5 +1,5 @@
-/* Generated automatically by "genstr" from "loongarch-strings".
-   Please do not edit this file directly.
+/* Generated automatically by "genstr" from "loongarch-strings" and
+   "isa-evolution.in".  Please do not edit this file directly.
 
    Copyright (C) 2021-2023 Free Software Foundation, Inc.
    Contributed by Loongson Ltd.
@@ -67,4 +67,7 @@ along with GCC; see the file COPYING3.  If not see
 #define STR_EXPLICIT_RELOCS_NONE "none"
 #define STR_EXPLICIT_RELOCS_ALWAYS "always"
 
+#define OPTSTR_DIV32	"div32"
+#define OPTSTR_LD_SEQ_SA	"ld-seq-sa"
+
 #endif /* LOONGARCH_STR_H */
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 738911661d7..6f89d468795 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -7455,6 +7455,10 @@ loongarch_option_override_internal (struct gcc_options *opts,
   if (loongarch_branch_cost == 0)
     loongarch_branch_cost = loongarch_cost->branch_cost;
 
+  /* If the user hasn't disabled a feature added during ISA evolution,
+     use the processor's default.  */
+  isa_evolution |= (la_target.isa.evolution &
+		    ~global_options_set.x_isa_evolution);
 
   /* Enable sw prefetching at -O3 and higher.  */
   if (opts->x_flag_prefetch_loop_arrays < 0
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index a5988411fbb..b17df1302f7 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -1,9 +1,10 @@
 ; Generated by "genstr" from the template "loongarch.opt.in"
-; and definitions from "loongarch-strings".
+; and definitions from "loongarch-strings" and "isa-evolution.in".
 ;
 ; Please do not edit this file directly.
 ; It will be automatically updated during a gcc build
-; if you change "loongarch.opt.in" or "loongarch-strings".
+; if you change "loongarch.opt.in", "loongarch-strings", or
+; "isa-evolution.in".
 ;
 ; Copyright (C) 2021-2023 Free Software Foundation, Inc.
 ;
@@ -248,3 +249,18 @@ Target Undocumented Joined UInteger Var(loongarch_vect_issue_info) Init(4) Integ
 Indicate how many non memory access vector instructions can be issued per
 cycle, it's used in unroll factor determination for autovectorizer.  The
 default value is 4.
+
+; Features added during ISA evolution.  This concept is different from ISA
+; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the
+; explanation.  These features may be implemented and enumerated with
+; CPUCFG independantly, so we use bit flags to specify them.
+Variable
+HOST_WIDE_INT isa_evolution = 0
+
+mdiv32
+Target Mask(ISA_DIV32) Var(isa_evolution)
+Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
+
+mld-seq-sa
+Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution)
+Do not need load-load barriers (dbar 0x700).
diff --git a/gcc/config/loongarch/t-loongarch b/gcc/config/loongarch/t-loongarch
index 0a7eaf6271f..10a984f3cb1 100644
--- a/gcc/config/loongarch/t-loongarch
+++ b/gcc/config/loongarch/t-loongarch
@@ -18,8 +18,9 @@
 
 
 GTM_H += loongarch-multilib.h
-OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h \
-		   $(srcdir)/config/loongarch/loongarch-tune.h
+OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h	\
+		   $(srcdir)/config/loongarch/loongarch-tune.h	\
+		   $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
 
 # Canonical target triplet from config.gcc
 LA_MULTIARCH_TRIPLET = $(patsubst LA_MULTIARCH_TRIPLET=%,%,$\
@@ -31,7 +32,8 @@ LA_STR_H = $(srcdir)/config/loongarch/loongarch-str.h
 # String definition header
 $(LA_STR_H): s-loongarch-str ; @true
 s-loongarch-str: $(srcdir)/config/loongarch/genopts/genstr.sh \
-	$(srcdir)/config/loongarch/genopts/loongarch-strings
+	$(srcdir)/config/loongarch/genopts/loongarch-strings  \
+	$(srcdir)/config/loongarch/genopts/isa-evolution.in
 	$(SHELL) $(srcdir)/config/loongarch/genopts/genstr.sh header \
     $(srcdir)/config/loongarch/genopts/loongarch-strings > \
     tmp-loongarch-str.h
@@ -58,7 +60,8 @@ loongarch-driver.o : $(srcdir)/config/loongarch/loongarch-driver.cc $(LA_STR_H)
 loongarch-opts.o: $(srcdir)/config/loongarch/loongarch-opts.cc $(LA_STR_H)
 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
 
-loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H)
+loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H) \
+		 $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
 	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
 
 loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.cc $(LA_STR_H)
@@ -67,6 +70,7 @@ loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.cc $(LA_STR_H)
 $(srcdir)/config/loongarch/loongarch.opt: s-loongarch-opt ; @true
 s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \
 	$(srcdir)/config/loongarch/genopts/loongarch.opt.in \
+	$(srcdir)/config/loongarch/genopts/isa-evolution.in \
 	$(srcdir)/config/loongarch/genopts/loongarch-strings $(LA_STR_H)
 	$(SHELL) $(srcdir)/config/loongarch/genopts/genstr.sh opt \
     $(srcdir)/config/loongarch/genopts/loongarch.opt.in \
@@ -74,3 +78,12 @@ s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \
 	$(SHELL) $(srcdir)/../move-if-change tmp-loongarch.opt \
     $(srcdir)/config/loongarch/loongarch.opt
 	$(STAMP) s-loongarch-opt
+
+$(srcdir)/config/loongarch/loongarch-cpucfg-map.h: s-loongarch-cpucfg-map
+	@true
+s-loongarch-cpucfg-map: $(srcdir)/config/loongarch/genopts/genstr.sh \
+	$(srcdir)/config/loongarch/genopts/isa-evolution.in
+	$(SHELL) $< cpucfg-map > tmp-cpucfg.h
+	$(SHELL) $(srcdir)/../move-if-change tmp-cpucfg.h \
+	    $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
+	$(STAMP) $@
-- 
2.42.1