From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id 571453858D28 for ; Fri, 17 Nov 2023 07:35:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 571453858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 571453858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.243.244.52 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700206560; cv=none; b=L364fEW9gB3RVgyrmPW9jjBxr8uXrR5pLdTN2huEea/iEFsv3X1zld6DvG1S8Yr2uCZGptgiywWLgaPDW7mqg+ezoOiEyLPUhGSvWN5gz4XQlx6Ha+Epka+M/iOQVhnNaLHFlkugHfV0WpY0/zBnKNkGBHKrggYXCkaN/UnRl4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700206560; c=relaxed/simple; bh=Qp9Am3r68lDYlTrzxLUQ7T28E/H0gFKfp+J+4kvEOQQ=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=HXpRos2brFtA1K5VozUqknpLGy126GRd8GgrqFt+vHMTDXuhbwZ0wmTD8Lp6ia9Kp8CJv+WORUsFV1FjHvGON062BmKokoqWXBMvcG7GBeHJERdOsRxWtwGl1rrEzT2C/4CKCKcSe1GQ7MKqzQWxc2u4d/OB6Q+OTuaHv85AU40= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp83t1700206551tjkr27mc Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 17 Nov 2023 15:35:50 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: QityeSR92A2BNenm7EoNlTCmDo/0AuW45kAhVcFijIBnQDUDZlgmz/298DbO7 BYpTul/p8ObU8iEmo0ChmKDKEZgab0BYIhDtqnBVQEU6k4NdQOXTcYB3yyqUsSskTkw2QIV ggUso7/TMLmnDyl5GV4lcJjnbaIpCdAHS6HXt/HL6BFefP24xVJIgzxENuhUIAdFnXRz76i V1PLMXKxbj6Ps2s7VvLdGwhq30ub4StPffO29NihYYebD2CAluw7E9uk97nn8tlglzjzVAh 8r+Zv9hOyXf9aXXF5ot5PmkuZHA5cmu6pf+1DgC5gh7ZnROChbLBX/S/GYIXNDJqLSdk8qX RME7KmIwjs/+Dj0emGDvrKWLU9zslCQ1Fb3VfVdngiNAb1csXFiWGhbPzBoMFGDgAxkBSjx HHAIz/qQcK4= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 827745176810110729 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix bug of tuple move splitter[PR112561] Date: Fri, 17 Nov 2023 15:35:49 +0800 Message-Id: <20231117073549.1841897-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00,GIT_PATCH_0,HEXHASH_WORD,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Fix segment fault on tuple move: bbl loader z 0000000000000000 ra 00000000000102ac sp 0000003ffffffaf0 gp 000000000001c0b8 tp 0000000000000000 t0 00000000000104a0 t1 000000000000000f t2 0000000000000000 s0 0000000000000000 s1 0000000000000000 a0 0000003ffffffb30 a1 0000003ffffffb58 a2 0000000000000000 a3 0000000000000000 a4 0000000000000000 a5 000000000001c340 a6 0000000000000004 a7 0000000000000004 s2 0000000000000000 s3 0000000000000000 s4 0000000000000000 s5 0000000000000000 s6 0000000000000000 s7 0000000000000000 s8 0000000000000000 s9 0000000000000000 sA 0000000000000000 sB 0000000000000000 t3 0000000000000000 t4 0000000000000000 t5 0000000000000000 t6 0000000000000000 pc 00000000000101aa va/inst 0000000000000004 sr 8000000200006620 User store segfault @ 0x0000000000000004 PR target/112561 gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Add VLS optimization. (expand_tuple_move): Fix bug gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112561.c: New test. --- gcc/config/riscv/riscv-v.cc | 21 ++++++++++++++++--- .../gcc.target/riscv/rvv/autovec/pr112561.c | 16 ++++++++++++++ 2 files changed, 34 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 6a2009ffb05..08bbb657a06 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -374,10 +374,24 @@ void emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) { gcc_assert (!can_create_pseudo_p ()); + machine_mode mode = GET_MODE (ops[0]); - insn_expander e (insn_flags, true); - e.set_vl (vl); - e.emit_insn ((enum insn_code) icode, ops); + if (imm_avl_p (mode)) + { + /* Even though VL is a real hardreg already allocated since + it is post-RA now, we still gain benefits that we emit + vsetivli zero, imm instead of vsetvli VL, zero which is + we can be more flexible in post-RA instruction scheduling. */ + insn_expander e (insn_flags, false); + e.set_vl (gen_int_mode (GET_MODE_NUNITS (mode), Pmode)); + e.emit_insn ((enum insn_code) icode, ops); + } + else + { + insn_expander e (insn_flags, true); + e.set_vl (vl); + e.emit_insn ((enum insn_code) icode, ops); + } } /* Emit an RVV insn with a predefined vector length. Contrary to @@ -2148,6 +2162,7 @@ expand_tuple_move (rtx *ops) offset = ops[2]; } + emit_vlmax_vsetvl (subpart_mode, ops[4]); if (MEM_P (ops[1])) { /* Load operations. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c new file mode 100644 index 00000000000..25e61fa12c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-options "-O3 -ftree-vectorize --param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */ + +int printf(char *, ...); +int a, b, c, e; +short d[7][7] = {}; +int main() { + short f; + c = 0; + for (; c <= 6; c++) { + e |= d[c][c] & 1; + b &= f & 3; + } + printf("%d\n", a); + return 0; +} -- 2.36.3