* [PATCH v2 1/6] LoongArch: Fix internal error running "gcc -march=native" on LA664
2023-11-17 20:43 [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support Xi Ruoyao
@ 2023-11-17 20:43 ` Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 2/6] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution Xi Ruoyao
` (5 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Xi Ruoyao @ 2023-11-17 20:43 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
On LA664, the PRID preset is ISA_BASE_LA64V110 but the base architecture
is guessed ISA_BASE_LA64V100. This causes a warning to be outputed:
cc1: warning: base architecture 'la64' differs from PRID preset '?'
But we've not set the "?" above in loongarch_isa_base_strings, thus it's
a nullptr and then an ICE is triggered.
Add ISA_BASE_LA64V110 to genopts and initialize
loongarch_isa_base_strings[ISA_BASE_LA64V110] correctly to fix the ICE.
The warning itself will be fixed later.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings:
(STR_ISA_BASE_LA64V110): Add.
* config/loongarch/genopts/loongarch.opt.in:
(ISA_BASE_LA64V110): Add.
* config/loongarch/loongarch-def.c
(loongarch_isa_base_strings): Initialize [ISA_BASE_LA64V110]
to STR_ISA_BASE_LA64V110.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-str.h: Regenerate.
---
gcc/config/loongarch/genopts/loongarch-strings | 1 +
gcc/config/loongarch/genopts/loongarch.opt.in | 3 +++
gcc/config/loongarch/loongarch-def.c | 1 +
gcc/config/loongarch/loongarch-str.h | 1 +
gcc/config/loongarch/loongarch.opt | 3 +++
5 files changed, 9 insertions(+)
diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
index 7bc4824007e..b2070c83ed0 100644
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -30,6 +30,7 @@ STR_CPU_LA664 la664
# Base architecture
STR_ISA_BASE_LA64V100 la64
+STR_ISA_BASE_LA64V110 la64v1.1
# -mfpu
OPTSTR_ISA_EXT_FPU fpu
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index 00b4733d75b..b274b3fb21e 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -32,6 +32,9 @@ Basic ISAs of LoongArch:
EnumValue
Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100)
+EnumValue
+Enum(isa_base) String(@@STR_ISA_BASE_LA64V110@@) Value(ISA_BASE_LA64V110)
+
;; ISA extensions / adjustments
Enum
Name(isa_ext_fpu) Type(int)
diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c
index 067629141b6..f22d488acb2 100644
--- a/gcc/config/loongarch/loongarch-def.c
+++ b/gcc/config/loongarch/loongarch-def.c
@@ -165,6 +165,7 @@ loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = {
const char*
loongarch_isa_base_strings[N_ISA_BASE_TYPES] = {
[ISA_BASE_LA64V100] = STR_ISA_BASE_LA64V100,
+ [ISA_BASE_LA64V110] = STR_ISA_BASE_LA64V110,
};
const char*
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index fc4f41bfc1e..114dbc692d7 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -33,6 +33,7 @@ along with GCC; see the file COPYING3. If not see
#define STR_CPU_LA664 "la664"
#define STR_ISA_BASE_LA64V100 "la64"
+#define STR_ISA_BASE_LA64V110 "la64v1.1"
#define OPTSTR_ISA_EXT_FPU "fpu"
#define STR_NONE "none"
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index 7f129e53ba5..350ca30d232 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -39,6 +39,9 @@ Basic ISAs of LoongArch:
EnumValue
Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100)
+EnumValue
+Enum(isa_base) String(la64v1.1) Value(ISA_BASE_LA64V110)
+
;; ISA extensions / adjustments
Enum
Name(isa_ext_fpu) Type(int)
--
2.42.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 2/6] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution
2023-11-17 20:43 [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 1/6] LoongArch: Fix internal error running "gcc -march=native" on LA664 Xi Ruoyao
@ 2023-11-17 20:43 ` Xi Ruoyao
2023-11-20 23:15 ` Joseph Myers
2023-11-17 20:43 ` [PATCH v2 3/6] LoongArch: Add evolution features of base ISA revisions Xi Ruoyao
` (4 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Xi Ruoyao @ 2023-11-17 20:43 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
LoongArch v1.10 introduced the concept of ISA evolution. During ISA
evolution, many independent features can be added and enumerated via
CPUCFG.
Add a data file into genopts storing the CPUCFG word, bit, the name
of the command line option controlling if this feature should be used
for compilation, and the text description. Make genstr.sh process these
info and add the command line options into loongarch.opt and
loongarch-str.h, and generate a new file loongarch-cpucfg-map.h for
mapping CPUCFG output to the corresponding option. When handling
-march=native, use the information in loongarch-cpucfg-map.h to generate
the corresponding option mask. Enable the features implied by -march
setting unless the user has explicitly disabled the feature.
The added options (-mdiv32 and -mld-seq-sa) are not really handled yet.
They'll be used in the following patches.
gcc/ChangeLog:
* config/loongarch/genopts/isa-evolution.in: New data file.
* config/loongarch/genopts/genstr.sh: Translate info in
isa-evolution.in when generating loongarch-str.h, loongarch.opt,
and loongarch-cpucfg-map.h.
* config/loongarch/genopts/loongarch.opt.in (isa_evolution):
New variable.
* config/loongarch/t-loongarch: (loongarch-cpucfg-map.h): New
rule.
(loongarch-str.h): Depend on isa-evolution.in.
(loongarch.opt): Depend on isa-evolution.in.
(loongarch-cpu.o): Depend on loongarch-cpucfg-map.h.
* config/loongarch/loongarch-str.h: Regenerate.
* config/loongarch/loongarch-def.h (loongarch_isa): Add field
for evolution features. Add helper function to enable features
in this field.
Probe native CPU capability and save the corresponding options
into preset.
* config/loongarch/loongarch-cpu.cc (fill_native_cpu_config):
Probe native CPU capability and save the corresponding options
into preset.
(cache_cpucfg): Simplify with C++11-style for loop.
(cpucfg_useful_idx, N_CPUCFG_WORDS): Move to ...
* config/loongarch/loongarch.cc
(loongarch_option_override_internal): Enable the ISA evolution
feature options implied by -march and not explicitly disabled.
(loongarch_asm_code_end): New function, print ISA information as
comments in the assembly if -fverbose-asm. It makes easier to
debug things like -march=native.
(TARGET_ASM_CODE_END): Define.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-cpucfg-map.h: Generate.
(cpucfg_useful_idx, N_CPUCFG_WORDS) ... here.
---
gcc/config/loongarch/genopts/genstr.sh | 92 ++++++++++++++++++-
gcc/config/loongarch/genopts/isa-evolution.in | 2 +
gcc/config/loongarch/genopts/loongarch.opt.in | 7 ++
gcc/config/loongarch/loongarch-cpu.cc | 46 +++++-----
gcc/config/loongarch/loongarch-cpucfg-map.h | 48 ++++++++++
gcc/config/loongarch/loongarch-def.h | 7 ++
gcc/config/loongarch/loongarch-str.h | 7 +-
gcc/config/loongarch/loongarch.cc | 31 +++++++
gcc/config/loongarch/loongarch.opt | 20 +++-
gcc/config/loongarch/t-loongarch | 21 ++++-
10 files changed, 245 insertions(+), 36 deletions(-)
create mode 100644 gcc/config/loongarch/genopts/isa-evolution.in
create mode 100644 gcc/config/loongarch/loongarch-cpucfg-map.h
diff --git a/gcc/config/loongarch/genopts/genstr.sh b/gcc/config/loongarch/genopts/genstr.sh
index 04e785576bb..cc83496ae38 100755
--- a/gcc/config/loongarch/genopts/genstr.sh
+++ b/gcc/config/loongarch/genopts/genstr.sh
@@ -25,8 +25,8 @@ cd "$(dirname "$0")"
# Generate a header containing definitions from the string table.
gen_defines() {
cat <<EOF
-/* Generated automatically by "genstr" from "loongarch-strings".
- Please do not edit this file directly.
+/* Generated automatically by "genstr" from "loongarch-strings" and
+ "isa-evolution.in". Please do not edit this file directly.
Copyright (C) 2021-2023 Free Software Foundation, Inc.
Contributed by Loongson Ltd.
@@ -55,6 +55,15 @@ EOF
-e 's@^\([^ \t]\+\)[ \t]*\([^ \t]*\)@#define \1 "\2"@' \
loongarch-strings
+ echo
+
+ # Generate the strings from isa-evolution.in.
+ awk '{
+ a=$3
+ gsub(/-/, "_", a)
+ print("#define OPTSTR_"toupper(a)"\t\""$3"\"")
+ }' isa-evolution.in
+
echo
echo "#endif /* LOONGARCH_STR_H */"
}
@@ -77,11 +86,12 @@ gen_options() {
# print a header
cat << EOF
; Generated by "genstr" from the template "loongarch.opt.in"
-; and definitions from "loongarch-strings".
+; and definitions from "loongarch-strings" and "isa-evolution.in".
;
; Please do not edit this file directly.
; It will be automatically updated during a gcc build
-; if you change "loongarch.opt.in" or "loongarch-strings".
+; if you change "loongarch.opt.in", "loongarch-strings", or
+; "isa-evolution.in".
;
EOF
@@ -91,13 +101,85 @@ EOF
eval "echo \"$line\""
done
}
+
+ # Generate the strings from isa-evolution.in.
+ awk '{
+ print("")
+ print("m"$3)
+ gsub(/-/, "_", $3)
+ print("Target Mask(ISA_"toupper($3)") Var(isa_evolution)")
+ $1=""; $2=""; $3=""
+ sub(/^ */, "", $0)
+ print($0)
+ }' isa-evolution.in
+}
+
+gen_cpucfg_map() {
+ cat <<EOF
+/* Generated automatically by "genstr" from "isa-evolution.in".
+ Please do not edit this file directly.
+
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef LOONGARCH_CPUCFG_MAP_H
+#define LOONGARCH_CPUCFG_MAP_H
+
+#include "options.h"
+
+static constexpr struct {
+ int cpucfg_word;
+ unsigned int cpucfg_bit;
+ HOST_WIDE_INT isa_evolution_bit;
+} cpucfg_map[] = {
+EOF
+
+ # Generate the strings from isa-evolution.in.
+ awk '{
+ gsub(/-/, "_", $3)
+ print(" { "$1", 1u << "$2", OPTION_MASK_ISA_"toupper($3)" },")
+ }' isa-evolution.in
+
+ echo "};"
+ echo
+ echo "static constexpr int cpucfg_useful_idx[] = {"
+
+ awk 'BEGIN { print(" 0,\n 1,\n 2,\n 16,\n 17,\n 18,\n 19,") }
+ {if ($1+0 > max+0) max=$1; print(" "$1",")}' \
+ isa-evolution.in | sort -n | uniq
+
+ echo "};"
+ echo ""
+
+ awk 'BEGIN { max=19 }
+ { if ($1+0 > max+0) max=$1 }
+ END { print "static constexpr int N_CPUCFG_WORDS = "1+max";" }' \
+ isa-evolution.in
+
+ echo "#endif /* LOONGARCH_CPUCFG_MAP_H */"
}
main() {
case "$1" in
+ cpucfg-map) gen_cpucfg_map;;
header) gen_defines;;
opt) gen_options;;
- *) echo "Unknown Command: \"$1\". Available: header, opt"; exit 1;;
+ *) echo "Unknown Command: \"$1\". Available: cpucfg-map, header, opt"; exit 1;;
esac
}
diff --git a/gcc/config/loongarch/genopts/isa-evolution.in b/gcc/config/loongarch/genopts/isa-evolution.in
new file mode 100644
index 00000000000..e58f0d6a1a1
--- /dev/null
+++ b/gcc/config/loongarch/genopts/isa-evolution.in
@@ -0,0 +1,2 @@
+2 26 div32 Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
+3 23 ld-seq-sa Do not need load-load barriers (dbar 0x700).
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index b274b3fb21e..8af6cc6f532 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -247,3 +247,10 @@ Target Undocumented Joined UInteger Var(loongarch_vect_issue_info) Init(4) Integ
Indicate how many non memory access vector instructions can be issued per
cycle, it's used in unroll factor determination for autovectorizer. The
default value is 4.
+
+; Features added during ISA evolution. This concept is different from ISA
+; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the
+; explanation. These features may be implemented and enumerated with
+; CPUCFG independantly, so we use bit flags to specify them.
+Variable
+HOST_WIDE_INT isa_evolution = 0
diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
index f3a13414143..f41e175257a 100644
--- a/gcc/config/loongarch/loongarch-cpu.cc
+++ b/gcc/config/loongarch/loongarch-cpu.cc
@@ -29,12 +29,11 @@ along with GCC; see the file COPYING3. If not see
#include "loongarch-def.h"
#include "loongarch-opts.h"
#include "loongarch-cpu.h"
+#include "loongarch-cpucfg-map.h"
#include "loongarch-str.h"
/* Native CPU detection with "cpucfg" */
-#define N_CPUCFG_WORDS 0x15
static uint32_t cpucfg_cache[N_CPUCFG_WORDS] = { 0 };
-static const int cpucfg_useful_idx[] = {0, 1, 2, 16, 17, 18, 19};
static uint32_t
read_cpucfg_word (int wordno)
@@ -56,11 +55,8 @@ read_cpucfg_word (int wordno)
void
cache_cpucfg (void)
{
- for (unsigned int i = 0; i < sizeof (cpucfg_useful_idx) / sizeof (int); i++)
- {
- cpucfg_cache[cpucfg_useful_idx[i]]
- = read_cpucfg_word (cpucfg_useful_idx[i]);
- }
+ for (int idx: cpucfg_useful_idx)
+ cpucfg_cache[idx] = read_cpucfg_word (idx);
}
uint32_t
@@ -125,11 +121,12 @@ fill_native_cpu_config (struct loongarch_target *tgt)
int tmp;
tgt->cpu_arch = native_cpu_type;
+ auto &preset = loongarch_cpu_default_isa[tgt->cpu_arch];
+
/* Fill: loongarch_cpu_default_isa[tgt->cpu_arch].base
With: base architecture (ARCH)
At: cpucfg_words[1][1:0] */
- #define PRESET_ARCH (loongarch_cpu_default_isa[tgt->cpu_arch].base)
switch (cpucfg_cache[1] & 0x3)
{
case 0x02:
@@ -144,19 +141,18 @@ fill_native_cpu_config (struct loongarch_target *tgt)
}
/* Check consistency with PRID presets. */
- if (native_cpu_type != CPU_NATIVE && tmp != PRESET_ARCH)
+ if (native_cpu_type != CPU_NATIVE && tmp != preset.base)
warning (0, "base architecture %qs differs from PRID preset %qs",
loongarch_isa_base_strings[tmp],
- loongarch_isa_base_strings[PRESET_ARCH]);
+ loongarch_isa_base_strings[preset.base]);
/* Use the native value anyways. */
- PRESET_ARCH = tmp;
+ preset.base = tmp;
/* Fill: loongarch_cpu_default_isa[tgt->cpu_arch].fpu
With: FPU type (FP, FP_SP, FP_DP)
At: cpucfg_words[2][2:0] */
- #define PRESET_FPU (loongarch_cpu_default_isa[tgt->cpu_arch].fpu)
switch (cpucfg_cache[2] & 0x7)
{
case 0x07:
@@ -179,20 +175,19 @@ fill_native_cpu_config (struct loongarch_target *tgt)
}
/* Check consistency with PRID presets. */
- if (native_cpu_type != CPU_NATIVE && tmp != PRESET_FPU)
+ if (native_cpu_type != CPU_NATIVE && tmp != preset.fpu)
warning (0, "floating-point unit %qs differs from PRID preset %qs",
loongarch_isa_ext_strings[tmp],
- loongarch_isa_ext_strings[PRESET_FPU]);
+ loongarch_isa_ext_strings[preset.fpu]);
/* Use the native value anyways. */
- PRESET_FPU = tmp;
+ preset.fpu = tmp;
/* Fill: loongarch_cpu_default_isa[CPU_NATIVE].simd
With: SIMD extension type (LSX, LASX)
At: cpucfg_words[2][7:6] */
- #define PRESET_SIMD (loongarch_cpu_default_isa[tgt->cpu_arch].simd)
switch (cpucfg_cache[2] & 0xc0)
{
case 0xc0:
@@ -219,14 +214,19 @@ fill_native_cpu_config (struct loongarch_target *tgt)
/* Check consistency with PRID presets. */
/*
- if (native_cpu_type != CPU_NATIVE && tmp != PRESET_SIMD)
+ if (native_cpu_type != CPU_NATIVE && tmp != preset.simd)
warning (0, "SIMD extension %qs differs from PRID preset %qs",
loongarch_isa_ext_strings[tmp],
- loongarch_isa_ext_strings[PRESET_SIMD]);
+ loongarch_isa_ext_strings[preset.simd]);
*/
/* Use the native value anyways. */
- PRESET_SIMD = tmp;
+ preset.simd = tmp;
+
+ /* Features added during ISA evolution. */
+ for (const auto &entry: cpucfg_map)
+ if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit)
+ preset.evolution |= entry.isa_evolution_bit;
}
if (tune_native_p)
@@ -237,7 +237,7 @@ fill_native_cpu_config (struct loongarch_target *tgt)
With: cache size info
At: cpucfg_words[16:20][31:0] */
- #define PRESET_CACHE (loongarch_cpu_cache[tgt->cpu_tune])
+ auto &preset_cache = loongarch_cpu_cache[tgt->cpu_tune];
struct loongarch_cache native_cache;
int l1d_present = 0, l1u_present = 0;
int l2d_present = 0;
@@ -268,8 +268,8 @@ fill_native_cpu_config (struct loongarch_target *tgt)
>> 10; /* in kibibytes */
/* Use the native value anyways. */
- PRESET_CACHE.l1d_line_size = native_cache.l1d_line_size;
- PRESET_CACHE.l1d_size = native_cache.l1d_size;
- PRESET_CACHE.l2d_size = native_cache.l2d_size;
+ preset_cache.l1d_line_size = native_cache.l1d_line_size;
+ preset_cache.l1d_size = native_cache.l1d_size;
+ preset_cache.l2d_size = native_cache.l2d_size;
}
}
diff --git a/gcc/config/loongarch/loongarch-cpucfg-map.h b/gcc/config/loongarch/loongarch-cpucfg-map.h
new file mode 100644
index 00000000000..0c078c39786
--- /dev/null
+++ b/gcc/config/loongarch/loongarch-cpucfg-map.h
@@ -0,0 +1,48 @@
+/* Generated automatically by "genstr" from "isa-evolution.in".
+ Please do not edit this file directly.
+
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef LOONGARCH_CPUCFG_MAP_H
+#define LOONGARCH_CPUCFG_MAP_H
+
+#include "options.h"
+
+static constexpr struct {
+ int cpucfg_word;
+ unsigned int cpucfg_bit;
+ HOST_WIDE_INT isa_evolution_bit;
+} cpucfg_map[] = {
+ { 2, 1u << 26, OPTION_MASK_ISA_DIV32 },
+ { 3, 1u << 23, OPTION_MASK_ISA_LD_SEQ_SA },
+};
+
+static constexpr int cpucfg_useful_idx[] = {
+ 0,
+ 1,
+ 2,
+ 3,
+ 16,
+ 17,
+ 18,
+ 19,
+};
+
+static constexpr int N_CPUCFG_WORDS = 20;
+#endif /* LOONGARCH_CPUCFG_MAP_H */
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index b319cded456..6123c8e0f19 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -46,6 +46,7 @@ along with GCC; see the file COPYING3. If not see
#ifndef LOONGARCH_DEF_H
#define LOONGARCH_DEF_H
+#include <stdint.h>
#include "loongarch-tune.h"
#ifdef __cplusplus
@@ -121,6 +122,12 @@ struct loongarch_isa
int base; /* ISA_BASE_ */
int fpu; /* ISA_EXT_FPU_ */
int simd; /* ISA_EXT_SIMD_ */
+
+ /* ISA evolution features implied by -march=, for -march=native probed
+ via CPUCFG. The features implied by base may be not included here.
+
+ Using int64_t instead of HOST_WIDE_INT for C compatibility. */
+ int64_t evolution;
};
struct loongarch_abi
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index 114dbc692d7..889962e9ab0 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -1,5 +1,5 @@
-/* Generated automatically by "genstr" from "loongarch-strings".
- Please do not edit this file directly.
+/* Generated automatically by "genstr" from "loongarch-strings" and
+ "isa-evolution.in". Please do not edit this file directly.
Copyright (C) 2021-2023 Free Software Foundation, Inc.
Contributed by Loongson Ltd.
@@ -69,4 +69,7 @@ along with GCC; see the file COPYING3. If not see
#define STR_EXPLICIT_RELOCS_NONE "none"
#define STR_EXPLICIT_RELOCS_ALWAYS "always"
+#define OPTSTR_DIV32 "div32"
+#define OPTSTR_LD_SEQ_SA "ld-seq-sa"
+
#endif /* LOONGARCH_STR_H */
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 5bec10d7418..b4bb2b6eeb5 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -7451,6 +7451,10 @@ loongarch_option_override_internal (struct gcc_options *opts,
if (loongarch_branch_cost == 0)
loongarch_branch_cost = loongarch_cost->branch_cost;
+ /* If the user hasn't disabled a feature added during ISA evolution,
+ use the processor's default. */
+ isa_evolution |= (la_target.isa.evolution &
+ ~global_options_set.x_isa_evolution);
/* Enable sw prefetching at -O3 and higher. */
if (opts->x_flag_prefetch_loop_arrays < 0
@@ -11430,6 +11434,30 @@ loongarch_builtin_support_vector_misalignment (machine_mode mode,
is_packed);
}
+/* If -fverbose-asm, dump some info for debugging. */
+static void
+loongarch_asm_code_end (void)
+{
+#define DUMP_FEATURE(PRED) \
+ fprintf (asm_out_file, "%s %s: %s\n", ASM_COMMENT_START, #PRED, \
+ (PRED) ? "enabled" : "disabled")
+
+ if (flag_verbose_asm)
+ {
+ fprintf (asm_out_file, "\n%s CPU: %s\n", ASM_COMMENT_START,
+ loongarch_cpu_strings [la_target.cpu_arch]);
+ fprintf (asm_out_file, "%s Tune: %s\n", ASM_COMMENT_START,
+ loongarch_cpu_strings [la_target.cpu_tune]);
+ fprintf (asm_out_file, "%s Base ISA: %s\n", ASM_COMMENT_START,
+ loongarch_isa_base_strings [la_target.isa.base]);
+ DUMP_FEATURE (TARGET_DIV32);
+ DUMP_FEATURE (TARGET_LD_SEQ_SA);
+ }
+
+ fputs ("\n\n", asm_out_file);
+#undef DUMP_FEATURE
+}
+
/* Initialize the GCC target structure. */
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -11449,6 +11477,9 @@ loongarch_builtin_support_vector_misalignment (machine_mode mode,
#undef TARGET_ASM_FUNCTION_RODATA_SECTION
#define TARGET_ASM_FUNCTION_RODATA_SECTION loongarch_function_rodata_section
+#undef TARGET_ASM_CODE_END
+#define TARGET_ASM_CODE_END loongarch_asm_code_end
+
#undef TARGET_SCHED_INIT
#define TARGET_SCHED_INIT loongarch_sched_init
#undef TARGET_SCHED_REORDER
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index 350ca30d232..a39eddc108b 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -1,9 +1,10 @@
; Generated by "genstr" from the template "loongarch.opt.in"
-; and definitions from "loongarch-strings".
+; and definitions from "loongarch-strings" and "isa-evolution.in".
;
; Please do not edit this file directly.
; It will be automatically updated during a gcc build
-; if you change "loongarch.opt.in" or "loongarch-strings".
+; if you change "loongarch.opt.in", "loongarch-strings", or
+; "isa-evolution.in".
;
; Copyright (C) 2021-2023 Free Software Foundation, Inc.
;
@@ -254,3 +255,18 @@ Target Undocumented Joined UInteger Var(loongarch_vect_issue_info) Init(4) Integ
Indicate how many non memory access vector instructions can be issued per
cycle, it's used in unroll factor determination for autovectorizer. The
default value is 4.
+
+; Features added during ISA evolution. This concept is different from ISA
+; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the
+; explanation. These features may be implemented and enumerated with
+; CPUCFG independantly, so we use bit flags to specify them.
+Variable
+HOST_WIDE_INT isa_evolution = 0
+
+mdiv32
+Target Mask(ISA_DIV32) Var(isa_evolution)
+Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
+
+mld-seq-sa
+Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution)
+Do not need load-load barriers (dbar 0x700).
diff --git a/gcc/config/loongarch/t-loongarch b/gcc/config/loongarch/t-loongarch
index 667a6bb3b50..7e65bb6e2a8 100644
--- a/gcc/config/loongarch/t-loongarch
+++ b/gcc/config/loongarch/t-loongarch
@@ -18,8 +18,9 @@
GTM_H += loongarch-multilib.h
-OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h \
- $(srcdir)/config/loongarch/loongarch-tune.h
+OPTIONS_H_EXTRA += $(srcdir)/config/loongarch/loongarch-def.h \
+ $(srcdir)/config/loongarch/loongarch-tune.h \
+ $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
# Canonical target triplet from config.gcc
LA_MULTIARCH_TRIPLET = $(patsubst LA_MULTIARCH_TRIPLET=%,%,$\
@@ -31,7 +32,8 @@ LA_STR_H = $(srcdir)/config/loongarch/loongarch-str.h
# String definition header
$(LA_STR_H): s-loongarch-str ; @true
s-loongarch-str: $(srcdir)/config/loongarch/genopts/genstr.sh \
- $(srcdir)/config/loongarch/genopts/loongarch-strings
+ $(srcdir)/config/loongarch/genopts/loongarch-strings \
+ $(srcdir)/config/loongarch/genopts/isa-evolution.in
$(SHELL) $(srcdir)/config/loongarch/genopts/genstr.sh header \
$(srcdir)/config/loongarch/genopts/loongarch-strings > \
tmp-loongarch-str.h
@@ -58,7 +60,8 @@ loongarch-driver.o : $(srcdir)/config/loongarch/loongarch-driver.cc $(LA_STR_H)
loongarch-opts.o: $(srcdir)/config/loongarch/loongarch-opts.cc $(LA_STR_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
-loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H)
+loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H) \
+ $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.c $(LA_STR_H)
@@ -67,6 +70,7 @@ loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.c $(LA_STR_H)
$(srcdir)/config/loongarch/loongarch.opt: s-loongarch-opt ; @true
s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \
$(srcdir)/config/loongarch/genopts/loongarch.opt.in \
+ $(srcdir)/config/loongarch/genopts/isa-evolution.in \
$(srcdir)/config/loongarch/genopts/loongarch-strings $(LA_STR_H)
$(SHELL) $(srcdir)/config/loongarch/genopts/genstr.sh opt \
$(srcdir)/config/loongarch/genopts/loongarch.opt.in \
@@ -74,3 +78,12 @@ s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \
$(SHELL) $(srcdir)/../move-if-change tmp-loongarch.opt \
$(srcdir)/config/loongarch/loongarch.opt
$(STAMP) s-loongarch-opt
+
+$(srcdir)/config/loongarch/loongarch-cpucfg-map.h: s-loongarch-cpucfg-map
+ @true
+s-loongarch-cpucfg-map: $(srcdir)/config/loongarch/genopts/genstr.sh \
+ $(srcdir)/config/loongarch/genopts/isa-evolution.in
+ $(SHELL) $< cpucfg-map > tmp-cpucfg.h
+ $(SHELL) $(srcdir)/../move-if-change tmp-cpucfg.h \
+ $(srcdir)/config/loongarch/loongarch-cpucfg-map.h
+ $(STAMP) $@
--
2.42.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 2/6] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution
2023-11-17 20:43 ` [PATCH v2 2/6] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution Xi Ruoyao
@ 2023-11-20 23:15 ` Joseph Myers
2023-11-21 0:00 ` Xi Ruoyao
0 siblings, 1 reply; 12+ messages in thread
From: Joseph Myers @ 2023-11-20 23:15 UTC (permalink / raw)
To: Xi Ruoyao; +Cc: gcc-patches, chenglulu, i, xuchenghua
On Sat, 18 Nov 2023, Xi Ruoyao wrote:
> diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
> index b319cded456..6123c8e0f19 100644
> --- a/gcc/config/loongarch/loongarch-def.h
> +++ b/gcc/config/loongarch/loongarch-def.h
> @@ -46,6 +46,7 @@ along with GCC; see the file COPYING3. If not see
> #ifndef LOONGARCH_DEF_H
> #define LOONGARCH_DEF_H
>
> +#include <stdint.h>
> #include "loongarch-tune.h"
>
> #ifdef __cplusplus
This has broken libgcc builds when target libc isn't yet available.
In file included from /scratch/jmyers/glibc-bot/src/gcc/libgcc/../gcc/config/loongarch/loongarch-def.h:49,
from /scratch/jmyers/glibc-bot/src/gcc/libgcc/../gcc/config/loongarch/loongarch-opts.h:24,
from ../.././gcc/options.h:8,
from ../.././gcc/tm.h:49,
from /scratch/jmyers/glibc-bot/src/gcc/libgcc/libgcc2.c:29:
/scratch/jmyers/glibc-bot/build/compilers/loongarch64-linux-gnu-lp64d/gcc-first/gcc/include/stdint.h:9:16: fatal error: stdint.h: No such file or directory
9 | # include_next <stdint.h>
| ^~~~~~~~~~
compilation terminated.
make[3]: *** [Makefile:505: _muldi3.o] Error 1
https://sourceware.org/pipermail/libc-testresults/2023q4/012109.html
My guess would be that the definitions needing <stdint.h> are not actually
needed in code built for the target, and so there should be more
#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
conditions like the one already present in loongarch-opts.h, to avoid
depending on a target header like this being present.
(Alternatively, one could argue for building much libgcc code with
-ffreestanding, which would also avoid GCC's <stdint.h> expecting a libc
header to be available - but that would have more risk for other targets.)
--
Joseph S. Myers
joseph@codesourcery.com
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 2/6] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution
2023-11-20 23:15 ` Joseph Myers
@ 2023-11-21 0:00 ` Xi Ruoyao
2023-11-21 3:09 ` Pushed: LoongArch: Fix libgcc build failure when libc is not available (was Re: genopts: Add infrastructure to generate code for new features in ISA evolution) Xi Ruoyao
0 siblings, 1 reply; 12+ messages in thread
From: Xi Ruoyao @ 2023-11-21 0:00 UTC (permalink / raw)
To: Joseph Myers; +Cc: gcc-patches, chenglulu, i, xuchenghua
On Mon, 2023-11-20 at 23:15 +0000, Joseph Myers wrote:
> On Sat, 18 Nov 2023, Xi Ruoyao wrote:
>
> > diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
> > index b319cded456..6123c8e0f19 100644
> > --- a/gcc/config/loongarch/loongarch-def.h
> > +++ b/gcc/config/loongarch/loongarch-def.h
> > @@ -46,6 +46,7 @@ along with GCC; see the file COPYING3. If not see
> > #ifndef LOONGARCH_DEF_H
> > #define LOONGARCH_DEF_H
> >
> > +#include <stdint.h>
> > #include "loongarch-tune.h"
> >
> > #ifdef __cplusplus
>
> This has broken libgcc builds when target libc isn't yet available.
>
> In file included from /scratch/jmyers/glibc-bot/src/gcc/libgcc/../gcc/config/loongarch/loongarch-def.h:49,
> from /scratch/jmyers/glibc-bot/src/gcc/libgcc/../gcc/config/loongarch/loongarch-opts.h:24,
> from ../.././gcc/options.h:8,
> from ../.././gcc/tm.h:49,
> from /scratch/jmyers/glibc-bot/src/gcc/libgcc/libgcc2.c:29:
> /scratch/jmyers/glibc-bot/build/compilers/loongarch64-linux-gnu-lp64d/gcc-first/gcc/include/stdint.h:9:16: fatal error: stdint.h: No such file or directory
> 9 | # include_next <stdint.h>
> | ^~~~~~~~~~
> compilation terminated.
> make[3]: *** [Makefile:505: _muldi3.o] Error 1
>
> https://sourceware.org/pipermail/libc-testresults/2023q4/012109.html
>
> My guess would be that the definitions needing <stdint.h> are not actually
> needed in code built for the target, and so there should be more
>
> #if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
>
> conditions like the one already present in loongarch-opts.h, to avoid
> depending on a target header like this being present.
Ah, makes sense. I thought stdint.h was usable without libc but it's
not true.
The only use for stdint.h is in struct loongarch_isa (using int64_t for
a 64-bit bitset). This struct is not used by target code.
I'll test building a cross compiler from x86_64 with stdint.h and struct
loongarch_isa guarded with the ifdef.
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 12+ messages in thread
* Pushed: LoongArch: Fix libgcc build failure when libc is not available (was Re: genopts: Add infrastructure to generate code for new features in ISA evolution)
2023-11-21 0:00 ` Xi Ruoyao
@ 2023-11-21 3:09 ` Xi Ruoyao
2023-11-21 14:16 ` Jeff Law
0 siblings, 1 reply; 12+ messages in thread
From: Xi Ruoyao @ 2023-11-21 3:09 UTC (permalink / raw)
To: Joseph Myers; +Cc: gcc-patches, chenglulu, i, xuchenghua
[-- Attachment #1: Type: text/plain, Size: 2061 bytes --]
On Tue, 2023-11-21 at 08:00 +0800, Xi Ruoyao wrote:
/* snip */
> > This has broken libgcc builds when target libc isn't yet available.
> >
> > In file included from /scratch/jmyers/glibc-bot/src/gcc/libgcc/../gcc/config/loongarch/loongarch-def.h:49,
> > from /scratch/jmyers/glibc-bot/src/gcc/libgcc/../gcc/config/loongarch/loongarch-opts.h:24,
> > from ../.././gcc/options.h:8,
> > from ../.././gcc/tm.h:49,
> > from /scratch/jmyers/glibc-bot/src/gcc/libgcc/libgcc2.c:29:
> > /scratch/jmyers/glibc-bot/build/compilers/loongarch64-linux-gnu-lp64d/gcc-first/gcc/include/stdint.h:9:16: fatal error: stdint.h: No such file or directory
> > 9 | # include_next <stdint.h>
> > | ^~~~~~~~~~
> > compilation terminated.
> > make[3]: *** [Makefile:505: _muldi3.o] Error 1
> >
> > https://sourceware.org/pipermail/libc-testresults/2023q4/012109.html
> >
> > My guess would be that the definitions needing <stdint.h> are not actually
> > needed in code built for the target, and so there should be more
> >
> > #if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
> >
> > conditions like the one already present in loongarch-opts.h, to avoid
> > depending on a target header like this being present.
>
> Ah, makes sense. I thought stdint.h was usable without libc but it's
> not true.
>
> The only use for stdint.h is in struct loongarch_isa (using int64_t for
> a 64-bit bitset). This struct is not used by target code.
>
> I'll test building a cross compiler from x86_64 with stdint.h and struct
> loongarch_isa guarded with the ifdef.
Pushed the attached patch r14-5634. Tested building a cross compiler
from x86_64 with cross Binutils but not target libc. Also tested
bootstrapping on loongarch64-linux-gnu.
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
[-- Attachment #2: 0007-LoongArch-Fix-libgcc-build-failure-when-libc-is-not-.patch --]
[-- Type: text/x-patch, Size: 2820 bytes --]
From d0faa1c8bad666c3e241d99871449aa60ccb8932 Mon Sep 17 00:00:00 2001
From: Xi Ruoyao <xry111@xry111.site>
Date: Tue, 21 Nov 2023 09:09:25 +0800
Subject: [PATCH 7/7] LoongArch: Fix libgcc build failure when libc is not
available
To use int64_t we included <stdint.h> in loongarch-def.h.
Unfortunately, loongarch-def.h is also used by libgcc etc., causing a
build failure when building a "stage1" cross compiler at which the
target libc is not built yet.
As int64_t is used for a C-compatible replacement of HOST_WIDE_INT, it's
not directly or indirectly referred by the target libraries. So
guard everything requiring stdint.h with #if then they'll not block
target libraries.
gcc/ChangeLog:
* config/loongarch/loongarch-def.h (stdint.h): Guard with #if to
exclude it for target libraries.
(loongarch_isa_base_features): Likewise.
(loongarch_isa): Likewise.
(loongarch_abi): Likewise.
(loongarch_target): Likewise.
(loongarch_cpu_default_isa): Likewise.
---
gcc/config/loongarch/loongarch-def.h | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index af7bd635d6e..851ff864eb2 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -46,7 +46,10 @@ along with GCC; see the file COPYING3. If not see
#ifndef LOONGARCH_DEF_H
#define LOONGARCH_DEF_H
+#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
#include <stdint.h>
+#endif
+
#include "loongarch-tune.h"
#ifdef __cplusplus
@@ -62,9 +65,11 @@ extern const char* loongarch_isa_base_strings[];
#define ISA_BASE_LA64V110 1
#define N_ISA_BASE_TYPES 2
+#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
/* Unlike other arrays, this is defined in loongarch-cpu.cc. The problem is
we cannot use the C++ header options.h in loongarch-def.c. */
extern int64_t loongarch_isa_base_features[];
+#endif
/* enum isa_ext_* */
extern const char* loongarch_isa_ext_strings[];
@@ -121,6 +126,7 @@ extern const char* loongarch_cmodel_strings[];
#define M_OPT_ABSENT(opt_enum) ((opt_enum) == M_OPT_UNSET)
+#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
/* Internal representation of the target. */
struct loongarch_isa
{
@@ -150,6 +156,9 @@ struct loongarch_target
int cmodel; /* CMODEL_ */
};
+extern struct loongarch_isa loongarch_cpu_default_isa[];
+#endif
+
/* CPU properties. */
/* index */
#define CPU_NATIVE 0
@@ -162,7 +171,6 @@ struct loongarch_target
/* parallel tables. */
extern const char* loongarch_cpu_strings[];
-extern struct loongarch_isa loongarch_cpu_default_isa[];
extern int loongarch_cpu_issue_rate[];
extern int loongarch_cpu_multipass_dfa_lookahead[];
--
2.42.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: Pushed: LoongArch: Fix libgcc build failure when libc is not available (was Re: genopts: Add infrastructure to generate code for new features in ISA evolution)
2023-11-21 3:09 ` Pushed: LoongArch: Fix libgcc build failure when libc is not available (was Re: genopts: Add infrastructure to generate code for new features in ISA evolution) Xi Ruoyao
@ 2023-11-21 14:16 ` Jeff Law
0 siblings, 0 replies; 12+ messages in thread
From: Jeff Law @ 2023-11-21 14:16 UTC (permalink / raw)
To: Xi Ruoyao, Joseph Myers; +Cc: gcc-patches, chenglulu, i, xuchenghua
On 11/20/23 20:09, Xi Ruoyao wrote:
> On Tue, 2023-11-21 at 08:00 +0800, Xi Ruoyao wrote:
>
> /* snip */
>
>>> This has broken libgcc builds when target libc isn't yet available.
>>>
>>> In file included from /scratch/jmyers/glibc-bot/src/gcc/libgcc/../gcc/config/loongarch/loongarch-def.h:49,
>>> from /scratch/jmyers/glibc-bot/src/gcc/libgcc/../gcc/config/loongarch/loongarch-opts.h:24,
>>> from ../.././gcc/options.h:8,
>>> from ../.././gcc/tm.h:49,
>>> from /scratch/jmyers/glibc-bot/src/gcc/libgcc/libgcc2.c:29:
>>> /scratch/jmyers/glibc-bot/build/compilers/loongarch64-linux-gnu-lp64d/gcc-first/gcc/include/stdint.h:9:16: fatal error: stdint.h: No such file or directory
>>> 9 | # include_next <stdint.h>
>>> | ^~~~~~~~~~
>>> compilation terminated.
>>> make[3]: *** [Makefile:505: _muldi3.o] Error 1
[ ... ]
Thanks. My tester had been tripping over that for a couple days.
Jeff
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/6] LoongArch: Add evolution features of base ISA revisions
2023-11-17 20:43 [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 1/6] LoongArch: Fix internal error running "gcc -march=native" on LA664 Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 2/6] LoongArch: genopts: Add infrastructure to generate code for new features in ISA evolution Xi Ruoyao
@ 2023-11-17 20:43 ` Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 4/6] LoongArch: Take the advantage of -mdiv32 if it's enabled Xi Ruoyao
` (3 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Xi Ruoyao @ 2023-11-17 20:43 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
* config/loongarch/loongarch-def.h:
(loongarch_isa_base_features): Declare. Define it in ...
* config/loongarch/loongarch-cpu.cc
(loongarch_isa_base_features): ... here.
(fill_native_cpu_config): If we know the base ISA of the CPU
model from PRID, use it instead of la64 (v1.0). Check if all
expected features of this base ISA is available, emit a warning
if not.
* config/loongarch/loongarch-opts.cc (config_target_isa): Enable
the features implied by the base ISA if not -march=native.
---
gcc/config/loongarch/loongarch-cpu.cc | 62 ++++++++++++++++++--------
gcc/config/loongarch/loongarch-def.h | 5 +++
gcc/config/loongarch/loongarch-opts.cc | 3 ++
3 files changed, 52 insertions(+), 18 deletions(-)
diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
index f41e175257a..7acf1a9121d 100644
--- a/gcc/config/loongarch/loongarch-cpu.cc
+++ b/gcc/config/loongarch/loongarch-cpu.cc
@@ -32,6 +32,19 @@ along with GCC; see the file COPYING3. If not see
#include "loongarch-cpucfg-map.h"
#include "loongarch-str.h"
+/* loongarch_isa_base_features defined here instead of loongarch-def.c
+ because we need to use options.h. Pay attention on the order of elements
+ in the initializer becaue ISO C++ does not allow C99 designated
+ initializers! */
+
+#define ISA_BASE_LA64V110_FEATURES \
+ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA)
+
+int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = {
+ /* [ISA_BASE_LA64V100] = */ 0,
+ /* [ISA_BASE_LA64V110] = */ ISA_BASE_LA64V110_FEATURES,
+};
+
/* Native CPU detection with "cpucfg" */
static uint32_t cpucfg_cache[N_CPUCFG_WORDS] = { 0 };
@@ -127,24 +140,22 @@ fill_native_cpu_config (struct loongarch_target *tgt)
With: base architecture (ARCH)
At: cpucfg_words[1][1:0] */
- switch (cpucfg_cache[1] & 0x3)
- {
- case 0x02:
- tmp = ISA_BASE_LA64V100;
- break;
-
- default:
- fatal_error (UNKNOWN_LOCATION,
- "unknown native base architecture %<0x%x%>, "
- "%qs failed", (unsigned int) (cpucfg_cache[1] & 0x3),
- "-m" OPTSTR_ARCH "=" STR_CPU_NATIVE);
- }
-
- /* Check consistency with PRID presets. */
- if (native_cpu_type != CPU_NATIVE && tmp != preset.base)
- warning (0, "base architecture %qs differs from PRID preset %qs",
- loongarch_isa_base_strings[tmp],
- loongarch_isa_base_strings[preset.base]);
+ if (native_cpu_type != CPU_NATIVE)
+ tmp = loongarch_cpu_default_isa[native_cpu_type].base;
+ else
+ switch (cpucfg_cache[1] & 0x3)
+ {
+ case 0x02:
+ tmp = ISA_BASE_LA64V100;
+ break;
+
+ default:
+ fatal_error (UNKNOWN_LOCATION,
+ "unknown native base architecture %<0x%x%>, "
+ "%qs failed",
+ (unsigned int) (cpucfg_cache[1] & 0x3),
+ "-m" OPTSTR_ARCH "=" STR_CPU_NATIVE);
+ }
/* Use the native value anyways. */
preset.base = tmp;
@@ -227,6 +238,21 @@ fill_native_cpu_config (struct loongarch_target *tgt)
for (const auto &entry: cpucfg_map)
if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit)
preset.evolution |= entry.isa_evolution_bit;
+
+ if (native_cpu_type != CPU_NATIVE)
+ {
+ /* Check if the local CPU really supports the features of the base
+ ISA of probed native_cpu_type. If any feature is not detected,
+ either GCC or the hardware is buggy. */
+ auto base_isa_feature = loongarch_isa_base_features[preset.base];
+ if ((preset.evolution & base_isa_feature) != base_isa_feature)
+ warning (0,
+ "detected base architecture %qs, but some of its "
+ "features are not detected; the detected base "
+ "architecture may be unreliable, only detected "
+ "features will be enabled",
+ loongarch_isa_base_strings[preset.base]);
+ }
}
if (tune_native_p)
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index 6123c8e0f19..af7bd635d6e 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -55,12 +55,17 @@ extern "C" {
/* enum isa_base */
extern const char* loongarch_isa_base_strings[];
+
/* LoongArch V1.00. */
#define ISA_BASE_LA64V100 0
/* LoongArch V1.10. */
#define ISA_BASE_LA64V110 1
#define N_ISA_BASE_TYPES 2
+/* Unlike other arrays, this is defined in loongarch-cpu.cc. The problem is
+ we cannot use the C++ header options.h in loongarch-def.c. */
+extern int64_t loongarch_isa_base_features[];
+
/* enum isa_ext_* */
extern const char* loongarch_isa_ext_strings[];
#define ISA_EXT_NONE 0
diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index 67a59152a01..b5836f198c0 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -284,6 +284,9 @@ config_target_isa:
/* Get default ISA from "-march" or its default value. */
t.isa = loongarch_cpu_default_isa[t.cpu_arch];
+ if (t.cpu_arch != CPU_NATIVE)
+ t.isa.evolution |= loongarch_isa_base_features[t.isa.base];
+
/* Apply incremental changes. */
/* "-march=native" overrides the default FPU type. */
--
2.42.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 4/6] LoongArch: Take the advantage of -mdiv32 if it's enabled
2023-11-17 20:43 [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support Xi Ruoyao
` (2 preceding siblings ...)
2023-11-17 20:43 ` [PATCH v2 3/6] LoongArch: Add evolution features of base ISA revisions Xi Ruoyao
@ 2023-11-17 20:43 ` Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 5/6] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa Xi Ruoyao
` (2 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Xi Ruoyao @ 2023-11-17 20:43 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
With -mdiv32, we can assume div.w[u] and mod.w[u] works on low 32 bits
of a 64-bit GPR even if it's not sign-extended.
gcc/ChangeLog:
* config/loongarch/loongarch.md (DIV): New mode iterator.
(<optab:ANY_DIV><mode:GPR>3): Don't expand if TARGET_DIV32.
(<optab:ANY_DIV>di3_fake): Disable if TARGET_DIV32.
(*<optab:ANY_DIV><mode:GPR>3): Allow SImode if TARGET_DIV32.
(<optab:ANY_DIV>si3_extended): New insn if TARGET_DIV32.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/div-div32.c: New test.
* gcc.target/loongarch/div-no-div32.c: New test.
---
gcc/config/loongarch/loongarch.md | 31 ++++++++++++++++---
.../gcc.target/loongarch/div-div32.c | 31 +++++++++++++++++++
.../gcc.target/loongarch/div-no-div32.c | 11 +++++++
3 files changed, 68 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/loongarch/div-div32.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/div-no-div32.c
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 22814a3679c..a97e5ee094a 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -408,6 +408,10 @@ (define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF])
;; st.w.
(define_mode_iterator ST_ANY [QHWD ANYF])
+;; A mode for anything legal as a input of a div or mod instruction.
+(define_mode_iterator DIV [(DI "TARGET_64BIT")
+ (SI "!TARGET_64BIT || TARGET_DIV32")])
+
;; In GPR templates, a string like "mul.<d>" will expand to "mul.w" in the
;; 32-bit version and "mul.d" in the 64-bit version.
(define_mode_attr d [(SI "w") (DI "d")])
@@ -914,7 +918,7 @@ (define_expand "<optab><mode>3"
(match_operand:GPR 2 "register_operand")))]
""
{
- if (GET_MODE (operands[0]) == SImode && TARGET_64BIT)
+ if (GET_MODE (operands[0]) == SImode && TARGET_64BIT && !TARGET_DIV32)
{
rtx reg1 = gen_reg_rtx (DImode);
rtx reg2 = gen_reg_rtx (DImode);
@@ -934,9 +938,9 @@ (define_expand "<optab><mode>3"
})
(define_insn "*<optab><mode>3"
- [(set (match_operand:X 0 "register_operand" "=r,&r,&r")
- (any_div:X (match_operand:X 1 "register_operand" "r,r,0")
- (match_operand:X 2 "register_operand" "r,r,r")))]
+ [(set (match_operand:DIV 0 "register_operand" "=r,&r,&r")
+ (any_div:DIV (match_operand:DIV 1 "register_operand" "r,r,0")
+ (match_operand:DIV 2 "register_operand" "r,r,r")))]
""
{
return loongarch_output_division ("<insn>.<d><u>\t%0,%1,%2", operands);
@@ -949,6 +953,23 @@ (define_insn "*<optab><mode>3"
(const_string "yes")
(const_string "no")))])
+(define_insn "<optab>si3_extended"
+ [(set (match_operand:DI 0 "register_operand" "=r,&r,&r")
+ (sign_extend
+ (any_div:SI (match_operand:SI 1 "register_operand" "r,r,0")
+ (match_operand:SI 2 "register_operand" "r,r,r"))))]
+ "TARGET_64BIT && TARGET_DIV32"
+{
+ return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
+}
+ [(set_attr "type" "idiv")
+ (set_attr "mode" "SI")
+ (set (attr "enabled")
+ (if_then_else
+ (match_test "!!which_alternative == loongarch_check_zero_div_p()")
+ (const_string "yes")
+ (const_string "no")))])
+
(define_insn "<optab>di3_fake"
[(set (match_operand:DI 0 "register_operand" "=r,&r,&r")
(sign_extend:DI
@@ -957,7 +978,7 @@ (define_insn "<optab>di3_fake"
(any_div:DI (match_operand:DI 1 "register_operand" "r,r,0")
(match_operand:DI 2 "register_operand" "r,r,r")) 0)]
UNSPEC_FAKE_ANY_DIV)))]
- "TARGET_64BIT"
+ "TARGET_64BIT && !TARGET_DIV32"
{
return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
}
diff --git a/gcc/testsuite/gcc.target/loongarch/div-div32.c b/gcc/testsuite/gcc.target/loongarch/div-div32.c
new file mode 100644
index 00000000000..8b1f686eca2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/div-div32.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mdiv32" } */
+/* { dg-final { scan-assembler "div\.w" } } */
+/* { dg-final { scan-assembler "div\.wu" } } */
+/* { dg-final { scan-assembler "mod\.w" } } */
+/* { dg-final { scan-assembler "mod\.wu" } } */
+/* { dg-final { scan-assembler-not "slli\.w.*,0" } } */
+
+int
+divw (long a, long b)
+{
+ return (int)a / (int)b;
+}
+
+unsigned int
+divwu (long a, long b)
+{
+ return (unsigned int)a / (unsigned int)b;
+}
+
+int
+modw (long a, long b)
+{
+ return (int)a % (int)b;
+}
+
+unsigned int
+modwu (long a, long b)
+{
+ return (unsigned int)a % (unsigned int)b;
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/div-no-div32.c b/gcc/testsuite/gcc.target/loongarch/div-no-div32.c
new file mode 100644
index 00000000000..f0f697ba589
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/div-no-div32.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
+/* { dg-final { scan-assembler "div\.w" } } */
+/* { dg-final { scan-assembler "div\.wu" } } */
+/* { dg-final { scan-assembler "mod\.w" } } */
+/* { dg-final { scan-assembler "mod\.wu" } } */
+
+/* -mno-div32 should be implied by -march=loongarch64. */
+/* { dg-final { scan-assembler-times "slli\.w\[^\n\]*0" 8 } } */
+
+#include "div-div32.c"
--
2.42.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 5/6] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa
2023-11-17 20:43 [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support Xi Ruoyao
` (3 preceding siblings ...)
2023-11-17 20:43 ` [PATCH v2 4/6] LoongArch: Take the advantage of -mdiv32 if it's enabled Xi Ruoyao
@ 2023-11-17 20:43 ` Xi Ruoyao
2023-11-17 20:43 ` [PATCH v2 6/6] LoongArch: Add fine-grained control for LAM_BH and LAMCAS Xi Ruoyao
2023-11-18 8:13 ` [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support chenglulu
6 siblings, 0 replies; 12+ messages in thread
From: Xi Ruoyao @ 2023-11-17 20:43 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
This option (CPUCFG word 0x3 bit 23) means "the hardware guarantee that
two loads on the same address won't be reordered with each other". Thus
we can omit the "load-load" barrier dbar 0x700.
This is only a micro-optimization because dbar 0x700 is already treated
as nop if the hardware supports LD_SEQ_SA.
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_print_operand): Don't
print dbar 0x700 if TARGET_LD_SEQ_SA.
* config/loongarch/sync.md (atomic_load<mode>): Likewise.
---
gcc/config/loongarch/loongarch.cc | 2 +-
gcc/config/loongarch/sync.md | 9 +++++----
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index b4bb2b6eeb5..5d3282c5e93 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6057,7 +6057,7 @@ loongarch_print_operand (FILE *file, rtx op, int letter)
if (loongarch_cas_failure_memorder_needs_acquire (
memmodel_from_int (INTVAL (op))))
fputs ("dbar\t0b10100", file);
- else
+ else if (!TARGET_LD_SEQ_SA)
fputs ("dbar\t0x700", file);
break;
diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index 67848d72b87..ce3ce89a61d 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -119,13 +119,14 @@ (define_insn "atomic_load<mode>"
case MEMMODEL_SEQ_CST:
return "dbar\t0x11\\n\\t"
"ld.<size>\t%0,%1\\n\\t"
- "dbar\t0x14\\n\\t";
+ "dbar\t0x14";
case MEMMODEL_ACQUIRE:
return "ld.<size>\t%0,%1\\n\\t"
- "dbar\t0x14\\n\\t";
+ "dbar\t0x14";
case MEMMODEL_RELAXED:
- return "ld.<size>\t%0,%1\\n\\t"
- "dbar\t0x700\\n\\t";
+ return TARGET_LD_SEQ_SA ? "ld.<size>\t%0,%1\\n\\t"
+ : "ld.<size>\t%0,%1\\n\\t"
+ "dbar\t0x700";
default:
/* The valid memory order variants are __ATOMIC_RELAXED, __ATOMIC_SEQ_CST,
--
2.42.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 6/6] LoongArch: Add fine-grained control for LAM_BH and LAMCAS
2023-11-17 20:43 [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support Xi Ruoyao
` (4 preceding siblings ...)
2023-11-17 20:43 ` [PATCH v2 5/6] LoongArch: Don't emit dbar 0x700 if -mld-seq-sa Xi Ruoyao
@ 2023-11-17 20:43 ` Xi Ruoyao
2023-11-18 8:13 ` [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support chenglulu
6 siblings, 0 replies; 12+ messages in thread
From: Xi Ruoyao @ 2023-11-17 20:43 UTC (permalink / raw)
To: gcc-patches; +Cc: chenglulu, i, xuchenghua, Xi Ruoyao
gcc/ChangeLog:
* config/loongarch/genopts/isa-evolution.in: (lam-bh, lamcas):
Add.
* config/loongarch/loongarch-str.h: Regenerate.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-cpucfg-map.h: Regenerate.
* config/loongarch/loongarch-cpu.cc
(ISA_BASE_LA64V110_FEATURES): Include OPTION_MASK_ISA_LAM_BH
and OPTION_MASK_ISA_LAMCAS.
* config/loongarch/sync.md (atomic_add<mode:SHORT>): Use
TARGET_LAM_BH instead of ISA_BASE_IS_LA64V110. Remove empty
lines from assembly output.
(atomic_exchange<mode>_short): Likewise.
(atomic_exchange<mode:SHORT>): Likewise.
(atomic_fetch_add<mode>_short): Likewise.
(atomic_fetch_add<mode:SHORT>): Likewise.
(atomic_cas_value_strong<mode>_amcas): Use TARGET_LAMCAS instead
of ISA_BASE_IS_LA64V110.
(atomic_compare_and_swap<mode>): Likewise.
(atomic_compare_and_swap<mode:GPR>): Likewise.
(atomic_compare_and_swap<mode:SHORT>): Likewise.
* config/loongarch/loongarch.cc (loongarch_asm_code_end): Dump
status if -mlam-bh and -mlamcas if -fverbose-asm.
---
gcc/config/loongarch/genopts/isa-evolution.in | 2 ++
gcc/config/loongarch/loongarch-cpu.cc | 3 ++-
gcc/config/loongarch/loongarch-cpucfg-map.h | 2 ++
gcc/config/loongarch/loongarch-str.h | 2 ++
gcc/config/loongarch/loongarch.cc | 2 ++
gcc/config/loongarch/loongarch.opt | 8 ++++++++
gcc/config/loongarch/sync.md | 18 +++++++++---------
7 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/gcc/config/loongarch/genopts/isa-evolution.in b/gcc/config/loongarch/genopts/isa-evolution.in
index e58f0d6a1a1..a6bc3f87f20 100644
--- a/gcc/config/loongarch/genopts/isa-evolution.in
+++ b/gcc/config/loongarch/genopts/isa-evolution.in
@@ -1,2 +1,4 @@
2 26 div32 Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
+2 27 lam-bh Support am{swap/add}[_db].{b/h} instructions.
+2 28 lamcas Support amcas[_db].{b/h/w/d} instructions.
3 23 ld-seq-sa Do not need load-load barriers (dbar 0x700).
diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
index 7acf1a9121d..622df47916f 100644
--- a/gcc/config/loongarch/loongarch-cpu.cc
+++ b/gcc/config/loongarch/loongarch-cpu.cc
@@ -38,7 +38,8 @@ along with GCC; see the file COPYING3. If not see
initializers! */
#define ISA_BASE_LA64V110_FEATURES \
- (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA)
+ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA \
+ | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS)
int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = {
/* [ISA_BASE_LA64V100] = */ 0,
diff --git a/gcc/config/loongarch/loongarch-cpucfg-map.h b/gcc/config/loongarch/loongarch-cpucfg-map.h
index 0c078c39786..02ff1671255 100644
--- a/gcc/config/loongarch/loongarch-cpucfg-map.h
+++ b/gcc/config/loongarch/loongarch-cpucfg-map.h
@@ -30,6 +30,8 @@ static constexpr struct {
HOST_WIDE_INT isa_evolution_bit;
} cpucfg_map[] = {
{ 2, 1u << 26, OPTION_MASK_ISA_DIV32 },
+ { 2, 1u << 27, OPTION_MASK_ISA_LAM_BH },
+ { 2, 1u << 28, OPTION_MASK_ISA_LAMCAS },
{ 3, 1u << 23, OPTION_MASK_ISA_LD_SEQ_SA },
};
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index 889962e9ab0..0384493765c 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -70,6 +70,8 @@ along with GCC; see the file COPYING3. If not see
#define STR_EXPLICIT_RELOCS_ALWAYS "always"
#define OPTSTR_DIV32 "div32"
+#define OPTSTR_LAM_BH "lam-bh"
+#define OPTSTR_LAMCAS "lamcas"
#define OPTSTR_LD_SEQ_SA "ld-seq-sa"
#endif /* LOONGARCH_STR_H */
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 5d3282c5e93..46a898b79b7 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -11451,6 +11451,8 @@ loongarch_asm_code_end (void)
fprintf (asm_out_file, "%s Base ISA: %s\n", ASM_COMMENT_START,
loongarch_isa_base_strings [la_target.isa.base]);
DUMP_FEATURE (TARGET_DIV32);
+ DUMP_FEATURE (TARGET_LAM_BH);
+ DUMP_FEATURE (TARGET_LAMCAS);
DUMP_FEATURE (TARGET_LD_SEQ_SA);
}
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index a39eddc108b..4d36e3ec4de 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -267,6 +267,14 @@ mdiv32
Target Mask(ISA_DIV32) Var(isa_evolution)
Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
+mlam-bh
+Target Mask(ISA_LAM_BH) Var(isa_evolution)
+Support am{swap/add}[_db].{b/h} instructions.
+
+mlamcas
+Target Mask(ISA_LAMCAS) Var(isa_evolution)
+Support amcas[_db].{b/h/w/d} instructions.
+
mld-seq-sa
Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution)
Do not need load-load barriers (dbar 0x700).
diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index ce3ce89a61d..229fc50360a 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -124,7 +124,7 @@ (define_insn "atomic_load<mode>"
return "ld.<size>\t%0,%1\\n\\t"
"dbar\t0x14";
case MEMMODEL_RELAXED:
- return TARGET_LD_SEQ_SA ? "ld.<size>\t%0,%1\\n\\t"
+ return TARGET_LD_SEQ_SA ? "ld.<size>\t%0,%1"
: "ld.<size>\t%0,%1\\n\\t"
"dbar\t0x700";
@@ -193,7 +193,7 @@ (define_insn "atomic_add<mode>"
(match_operand:SHORT 1 "reg_or_0_operand" "rJ"))
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
- "ISA_BASE_IS_LA64V110"
+ "TARGET_LAM_BH"
"amadd%A2.<amo>\t$zero,%z1,%0"
[(set (attr "length") (const_int 4))])
@@ -230,7 +230,7 @@ (define_insn "atomic_exchange<mode>_short"
UNSPEC_SYNC_EXCHANGE))
(set (match_dup 1)
(match_operand:SHORT 2 "register_operand" "r"))]
- "ISA_BASE_IS_LA64V110"
+ "TARGET_LAM_BH"
"amswap%A3.<amo>\t%0,%z2,%1"
[(set (attr "length") (const_int 4))])
@@ -266,7 +266,7 @@ (define_insn "atomic_cas_value_strong<mode>_amcas"
(match_operand:QHWD 3 "reg_or_0_operand" "rJ")
(match_operand:SI 4 "const_int_operand")] ;; mod_s
UNSPEC_COMPARE_AND_SWAP))]
- "ISA_BASE_IS_LA64V110"
+ "TARGET_LAMCAS"
"ori\t%0,%z2,0\n\tamcas%A4.<amo>\t%0,%z3,%1"
[(set (attr "length") (const_int 8))])
@@ -296,7 +296,7 @@ (define_expand "atomic_compare_and_swap<mode>"
operands[6] = mod_s;
- if (ISA_BASE_IS_LA64V110)
+ if (TARGET_LAMCAS)
emit_insn (gen_atomic_cas_value_strong<mode>_amcas (operands[1], operands[2],
operands[3], operands[4],
operands[6]));
@@ -422,7 +422,7 @@ (define_expand "atomic_compare_and_swap<mode>"
operands[6] = mod_s;
- if (ISA_BASE_IS_LA64V110)
+ if (TARGET_LAMCAS)
emit_insn (gen_atomic_cas_value_strong<mode>_amcas (operands[1], operands[2],
operands[3], operands[4],
operands[6]));
@@ -642,7 +642,7 @@ (define_expand "atomic_exchange<mode>"
(match_operand:SHORT 2 "register_operand"))]
""
{
- if (ISA_BASE_IS_LA64V110)
+ if (TARGET_LAM_BH)
emit_insn (gen_atomic_exchange<mode>_short (operands[0], operands[1], operands[2], operands[3]));
else
{
@@ -663,7 +663,7 @@ (define_insn "atomic_fetch_add<mode>_short"
(match_operand:SHORT 2 "reg_or_0_operand" "rJ"))
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
- "ISA_BASE_IS_LA64V110"
+ "TARGET_LAM_BH"
"amadd%A3.<amo>\t%0,%z2,%1"
[(set (attr "length") (const_int 4))])
@@ -678,7 +678,7 @@ (define_expand "atomic_fetch_add<mode>"
UNSPEC_SYNC_OLD_OP))]
""
{
- if (ISA_BASE_IS_LA64V110)
+ if (TARGET_LAM_BH)
emit_insn (gen_atomic_fetch_add<mode>_short (operands[0], operands[1],
operands[2], operands[3]));
else
--
2.42.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support
2023-11-17 20:43 [PATCH v2 0/6] Add LoongArch v1.1 div32 and ld-seq-sa support Xi Ruoyao
` (5 preceding siblings ...)
2023-11-17 20:43 ` [PATCH v2 6/6] LoongArch: Add fine-grained control for LAM_BH and LAMCAS Xi Ruoyao
@ 2023-11-18 8:13 ` chenglulu
6 siblings, 0 replies; 12+ messages in thread
From: chenglulu @ 2023-11-18 8:13 UTC (permalink / raw)
To: Xi Ruoyao, gcc-patches; +Cc: i, xuchenghua
I have no problem, thanks for fixing the bug
在 2023/11/18 上午4:43, Xi Ruoyao 写道:
> Superseds
> https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636795.html.
>
> Requires
> https://gcc.gnu.org/pipermail/gcc-patches/2023-November/636946.html.
>
> Changes:
>
> - Rebase on top of "Add LoongarchV1.1 instructions support".
> - Not to translate loongarch-def.c C++. Use int64_t instead of
> HOST_WIDE_INT in loongarch-def.h.
> - In genopts, also generates cpucfg_useful_idx[] and N_CPUCFG_WORDS.
> Use decimals instead of hexidecimals for CPUCFG word index to make awk
> happy to perform numerical comparision.
> - Dump arch and feature info as comments in generated assembly if
> -fverbose-asm. It's helpful for testing and debugging.
>
> Xi Ruoyao (6):
> LoongArch: Fix internal error running "gcc -march=native" on LA664
> LoongArch: genopts: Add infrastructure to generate code for new
> features in ISA evolution
> LoongArch: Add evolution features of base ISA revisions
> LoongArch: Take the advantage of -mdiv32 if it's enabled
> LoongArch: Don't emit dbar 0x700 if -mld-seq-sa
> LoongArch: Add fine-grained control for LAM_BH and LAMCAS
>
> gcc/config/loongarch/genopts/genstr.sh | 92 ++++++++++++++-
> gcc/config/loongarch/genopts/isa-evolution.in | 4 +
> .../loongarch/genopts/loongarch-strings | 1 +
> gcc/config/loongarch/genopts/loongarch.opt.in | 10 ++
> gcc/config/loongarch/loongarch-cpu.cc | 105 +++++++++++-------
> gcc/config/loongarch/loongarch-cpucfg-map.h | 50 +++++++++
> gcc/config/loongarch/loongarch-def.c | 1 +
> gcc/config/loongarch/loongarch-def.h | 12 ++
> gcc/config/loongarch/loongarch-opts.cc | 3 +
> gcc/config/loongarch/loongarch-str.h | 10 +-
> gcc/config/loongarch/loongarch.cc | 35 +++++-
> gcc/config/loongarch/loongarch.md | 31 +++++-
> gcc/config/loongarch/loongarch.opt | 31 +++++-
> gcc/config/loongarch/sync.md | 25 +++--
> gcc/config/loongarch/t-loongarch | 21 +++-
> .../gcc.target/loongarch/div-div32.c | 31 ++++++
> .../gcc.target/loongarch/div-no-div32.c | 11 ++
> 17 files changed, 403 insertions(+), 70 deletions(-)
> create mode 100644 gcc/config/loongarch/genopts/isa-evolution.in
> create mode 100644 gcc/config/loongarch/loongarch-cpucfg-map.h
> create mode 100644 gcc/testsuite/gcc.target/loongarch/div-div32.c
> create mode 100644 gcc/testsuite/gcc.target/loongarch/div-no-div32.c
>
^ permalink raw reply [flat|nested] 12+ messages in thread